phy: stm32: add phy tuning support

It can be necessary to adjust the phys settings to compensate parasitics.
This patch adds support of new optional properties to configure the tune
interface of the phys of stm32-usbphyc.
Properties are optional, that's why each property is skipped if not
found (-EINVAL).
Phy tuning is restored on resume because if deep low power state is
achieved, phy tuning configuration is reset.

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20211015161427.220784-4-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c
index 083593a..7df6a63 100644 (file)
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -20,6 +20,7 @@
 #define STM32_USBPHYC_PLL      0x0
 #define STM32_USBPHYC_MISC     0x8
 #define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
+#define STM32_USBPHYC_TUNE(X)  (0x10C + ((X) * 0x100))
 #define STM32_USBPHYC_VERSION  0x3F4
 
 /* STM32_USBPHYC_PLL bit fields */
@@ -41,6 +42,83 @@
 #define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
 #define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
 
+/* STM32_USBPHYC_TUNE bit fields */
+#define INCURREN               BIT(0)
+#define INCURRINT              BIT(1)
+#define LFSCAPEN               BIT(2)
+#define HSDRVSLEW              BIT(3)
+#define HSDRVDCCUR             BIT(4)
+#define HSDRVDCLEV             BIT(5)
+#define HSDRVCURINCR           BIT(6)
+#define FSDRVRFADJ             BIT(7)
+#define HSDRVRFRED             BIT(8)
+#define HSDRVCHKITRM           GENMASK(12, 9)
+#define HSDRVCHKZTRM           GENMASK(14, 13)
+#define OTPCOMP                        GENMASK(19, 15)
+#define SQLCHCTL               GENMASK(21, 20)
+#define HDRXGNEQEN             BIT(22)
+#define HSRXOFF                        GENMASK(24, 23)
+#define HSFALLPREEM            BIT(25)
+#define SHTCCTCTLPROT          BIT(26)
+#define STAGSEL                        BIT(27)
+
+enum boosting_vals {
+       BOOST_1000_UA = 1000,
+       BOOST_2000_UA = 2000,
+};
+
+enum dc_level_vals {
+       DC_NOMINAL,
+       DC_PLUS_5_TO_7_MV,
+       DC_PLUS_10_TO_14_MV,
+       DC_MINUS_5_TO_7_MV,
+       DC_MAX,
+};
+
+enum current_trim {
+       CUR_NOMINAL,
+       CUR_PLUS_1_56_PCT,
+       CUR_PLUS_3_12_PCT,
+       CUR_PLUS_4_68_PCT,
+       CUR_PLUS_6_24_PCT,
+       CUR_PLUS_7_8_PCT,
+       CUR_PLUS_9_36_PCT,
+       CUR_PLUS_10_92_PCT,
+       CUR_PLUS_12_48_PCT,
+       CUR_PLUS_14_04_PCT,
+       CUR_PLUS_15_6_PCT,
+       CUR_PLUS_17_16_PCT,
+       CUR_PLUS_19_01_PCT,
+       CUR_PLUS_20_58_PCT,
+       CUR_PLUS_22_16_PCT,
+       CUR_PLUS_23_73_PCT,
+       CUR_MAX,
+};
+
+enum impedance_trim {
+       IMP_NOMINAL,
+       IMP_MINUS_2_OHMS,
+       IMP_MINUS_4_OMHS,
+       IMP_MINUS_6_OHMS,
+       IMP_MAX,
+};
+
+enum squelch_level {
+       SQLCH_NOMINAL,
+       SQLCH_PLUS_7_MV,
+       SQLCH_MINUS_5_MV,
+       SQLCH_PLUS_14_MV,
+       SQLCH_MAX,
+};
+
+enum rx_offset {
+       NO_RX_OFFSET,
+       RX_OFFSET_PLUS_5_MV,
+       RX_OFFSET_PLUS_10_MV,
+       RX_OFFSET_MINUS_5_MV,
+       RX_OFFSET_MAX,
+};
+
 /* STM32_USBPHYC_VERSION bit fields */
 #define MINREV                 GENMASK(3, 0)
 #define MAJREV                 GENMASK(7, 4)
@@ -60,6 +138,7 @@ struct stm32_usbphyc_phy {
        struct regulator *vbus;
        u32 index;
        bool active;
+       u32 tune;
 };
 
 struct stm32_usbphyc {
@@ -375,6 +454,107 @@ static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
        return ret;
 }
 
+static void stm32_usbphyc_phy_tuning(struct stm32_usbphyc *usbphyc,
+                                    struct device_node *np, u32 index)
+{
+       struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys[index];
+       u32 reg = STM32_USBPHYC_TUNE(index);
+       u32 otpcomp, val;
+       int ret;
+
+       /* Backup OTP compensation code */
+       otpcomp = FIELD_GET(OTPCOMP, readl_relaxed(usbphyc->base + reg));
+
+       ret = of_property_read_u32(np, "st,current-boost-microamp", &val);
+       if (ret != -EINVAL) {
+               if (!ret && (val == BOOST_1000_UA || val == BOOST_2000_UA)) {
+                       val = (val == BOOST_2000_UA) ? 1 : 0;
+                       usbphyc_phy->tune |= INCURREN | FIELD_PREP(INCURRINT, val);
+               } else {
+                       dev_warn(usbphyc->dev, "phy%d: invalid st,current-boost-microamp\n", index);
+               }
+       }
+
+       if (!of_property_read_bool(np, "st,no-lsfs-fb-cap"))
+               usbphyc_phy->tune |= LFSCAPEN;
+
+       if (of_property_read_bool(np, "st,slow-hs-slew-rate"))
+               usbphyc_phy->tune |= HSDRVSLEW;
+
+       ret = of_property_read_u32(np, "st,tune-hs-dc-level", &val);
+       if (ret != -EINVAL) {
+               if (!ret && val < DC_MAX) {
+                       if (val == DC_MINUS_5_TO_7_MV) {/* Decreases HS driver DC level */
+                               usbphyc_phy->tune |= HSDRVDCCUR;
+                       } else if (val > 0) {           /* Increases HS driver DC level */
+                               val = (val == DC_PLUS_10_TO_14_MV) ? 1 : 0;
+                               usbphyc_phy->tune |= HSDRVCURINCR | FIELD_PREP(HSDRVDCLEV, val);
+                       }
+               } else {
+                       dev_warn(usbphyc->dev, "phy%d: invalid st,tune-hs-dc-level\n", index);
+               }
+       }
+
+       if (of_property_read_bool(np, "st,enable-fs-rftime-tuning"))
+               usbphyc_phy->tune |= FSDRVRFADJ;
+
+       if (of_property_read_bool(np, "st,enable-hs-rftime-reduction"))
+               usbphyc_phy->tune |= HSDRVRFRED;
+
+       ret = of_property_read_u32(np, "st,trim-hs-current", &val);
+       if (ret != -EINVAL) {
+               if (!ret && val < CUR_MAX)
+                       usbphyc_phy->tune |= FIELD_PREP(HSDRVCHKITRM, val);
+               else
+                       dev_warn(usbphyc->dev, "phy%d: invalid st,trim-hs-current\n", index);
+       }
+
+       ret = of_property_read_u32(np, "st,trim-hs-impedance", &val);
+       if (ret != -EINVAL) {
+               if (!ret && val < IMP_MAX)
+                       usbphyc_phy->tune |= FIELD_PREP(HSDRVCHKZTRM, val);
+               else
+                       dev_warn(usbphyc->dev, "phy%d: invalid st,trim-hs-impedance\n", index);
+       }
+
+       ret = of_property_read_u32(np, "st,tune-squelch-level", &val);
+       if (ret != -EINVAL) {
+               if (!ret && val < SQLCH_MAX)
+                       usbphyc_phy->tune |= FIELD_PREP(SQLCHCTL, val);
+               else
+                       dev_warn(usbphyc->dev, "phy%d: invalid st,tune-squelch\n", index);
+       }
+
+       if (of_property_read_bool(np, "st,enable-hs-rx-gain-eq"))
+               usbphyc_phy->tune |= HDRXGNEQEN;
+
+       ret = of_property_read_u32(np, "st,tune-hs-rx-offset", &val);
+       if (ret != -EINVAL) {
+               if (!ret && val < RX_OFFSET_MAX)
+                       usbphyc_phy->tune |= FIELD_PREP(HSRXOFF, val);
+               else
+                       dev_warn(usbphyc->dev, "phy%d: invalid st,tune-hs-rx-offset\n", index);
+       }
+
+       if (of_property_read_bool(np, "st,no-hs-ftime-ctrl"))
+               usbphyc_phy->tune |= HSFALLPREEM;
+
+       if (!of_property_read_bool(np, "st,no-lsfs-sc"))
+               usbphyc_phy->tune |= SHTCCTCTLPROT;
+
+       if (of_property_read_bool(np, "st,enable-hs-tx-staggering"))
+               usbphyc_phy->tune |= STAGSEL;
+
+       /* Restore OTP compensation code */
+       usbphyc_phy->tune |= FIELD_PREP(OTPCOMP, otpcomp);
+
+       /*
+        * By default, if no st,xxx tuning property is used, usbphyc_phy->tune is equal to
+        * STM32_USBPHYC_TUNE reset value (LFSCAPEN | SHTCCTCTLPROT | OTPCOMP).
+        */
+       writel_relaxed(usbphyc_phy->tune, usbphyc->base + reg);
+}
+
 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
                                       u32 utmi_switch)
 {
@@ -550,6 +730,9 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
                        usbphyc->phys[port]->vbus = NULL;
                }
 
+               /* Configure phy tuning */
+               stm32_usbphyc_phy_tuning(usbphyc, child, index);
+
                port++;
        }
 
@@ -601,10 +784,17 @@ static int stm32_usbphyc_remove(struct platform_device *pdev)
 static int __maybe_unused stm32_usbphyc_resume(struct device *dev)
 {
        struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
+       struct stm32_usbphyc_phy *usbphyc_phy;
+       int port;
 
        if (usbphyc->switch_setup >= 0)
                stm32_usbphyc_switch_setup(usbphyc, usbphyc->switch_setup);
 
+       for (port = 0; port < usbphyc->nphys; port++) {
+               usbphyc_phy = usbphyc->phys[port];
+               writel_relaxed(usbphyc_phy->tune, usbphyc->base + STM32_USBPHYC_TUNE(port));
+       }
+
        return 0;
 }