A faster version of 4tap horizontal scaling causes segfaults in ORC
presumably because it uses too many registers so disable it to avoid
crashing in the ORC tests.
convlw w1, t1
convsuswb d1, w1
-.function video_orc_resample_h_4tap_8
-.source 1 s1 guint32
-.source 1 s2 guint32
-.source 1 s3 guint32
-.source 1 s4 guint32
-.source 2 t1 gint16
-.source 2 t2 gint16
-.source 2 t3 gint16
-.source 2 t4 gint16
-.dest 1 d1 guint8
-.temp 2 w1
-.temp 2 w2
-.temp 4 l1
-.temp 4 l2
-
-convubw w1, s1
-mulswl l1, w1, t1
-convubw w2, s2
-mulswl l2, w2, t2
-addl l1, l1, l2
-convubw w2, s3
-mulswl l2, w2, t3
-addl l1, l1, l2
-convubw w2, s4
-mulswl l2, w2, t4
-addl l1, l1, l2
-addl l1, l1, 4095
-shrsl l1, l1, 12
-convlw w1, l1
-convsuswb d1, w1
+#.function video_orc_resample_h_4tap_8
+#.source 1 s1 guint32
+#.source 1 s2 guint32
+#.source 1 s3 guint32
+#.source 1 s4 guint32
+#.source 2 t1 gint16
+#.source 2 t2 gint16
+#.source 2 t3 gint16
+#.source 2 t4 gint16
+#.dest 1 d1 guint8
+#.temp 2 w1
+#.temp 2 w2
+#.temp 4 l1
+#.temp 4 l2
+#
+#convubw w1, s1
+#mulswl l1, w1, t1
+#convubw w2, s2
+#mulswl l2, w2, t2
+#addl l1, l1, l2
+#convubw w2, s3
+#mulswl l2, w2, t3
+#addl l1, l1, l2
+#convubw w2, s4
+#mulswl l2, w2, t4
+#addl l1, l1, l2
+#addl l1, l1, 4095
+#shrsl l1, l1, 12
+#convlw w1, l1
+#convsuswb d1, w1
.function video_orc_resample_h_multaps_8