reg = <0x0 0x1f22c000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "sataphy2clk";
- status = "ok";
+ status = "okay";
csr-offset = <0x4>;
csr-mask = <0x3a>;
enable-offset = <0x0>;
reg = <0x0 0x1f23c000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "sataphy3clk";
- status = "ok";
+ status = "okay";
csr-offset = <0x4>;
csr-mask = <0x3a>;
enable-offset = <0x0>;
reg = <0x0 0x1f22a000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&sataphy2clk 0>;
- status = "ok";
+ status = "okay";
apm,tx-boost-gain = <30 30 30 30 30 30>;
apm,tx-eye-tuning = <1 10 10 2 10 10>;
};
reg = <0x0 0x1f23a000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&sataphy3clk 0>;
- status = "ok";
+ status = "okay";
apm,tx-boost-gain = <31 31 31 31 31 31>;
apm,tx-eye-tuning = <2 10 10 2 10 10>;
};
<0x0 0x1f227000 0x0 0x1000>;
interrupts = <0x0 0x87 0x4>;
dma-coherent;
- status = "ok";
+ status = "okay";
clocks = <&sata23clk 0>;
phys = <&phy2 0>;
phy-names = "sata-phy";
<0x0 0x1f23e000 0x0 0x1000>;
interrupts = <0x0 0x88 0x4>;
dma-coherent;
- status = "ok";
+ status = "okay";
clocks = <&sata45clk 0>;
phys = <&phy3 0>;
phy-names = "sata-phy";