The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID
value if the current FSBL image is found valid, otherwise BootROM will
look for next subsequent valid FSBL image when warm reset is triggered.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
*/
#ifndef _SYSTEM_MANAGER_ARRIA10_H_
#define SYSMGR_A10_NOC_IDLEACK 0xd0
#define SYSMGR_A10_NOC_IDLESTATUS 0xd4
#define SYSMGR_A10_FPGA2SOC_CTRL 0xd8
+#define SYSMGR_A10_ROMCODE_INITSWSTATE 0x20C
#define SYSMGR_SDMMC SYSMGR_A10_SDMMC
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2021 Altera Corporation <www.altera.com>
*/
#include <common.h>
#include <memalign.h>
#define FPGA_BUFSIZ 16 * 1024
+#define FSBL_IMAGE_IS_VALID 0x49535756
DECLARE_GLOBAL_DATA_PTR;
config_dedicated_pins(gd->fdt_blob);
WATCHDOG_RESET();
}
+
+/* board specific function prior loading SSBL / U-Boot proper */
+void spl_board_prepare_for_boot(void)
+{
+ writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ROMCODE_INITSWSTATE);
+}