PR target/59142
* config/arm/predicates.md (vfp_hard_register_operand): New predicate.
* config/arm/arm.md (vfp_pop_multiple_with_writeback): Use
vfp_hard_register_operand.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@206123
138bc75d-0d04-0410-961f-
82ee72b054a4
-o2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
+2013-12-19 Charles Baylis <charles.baylis@linaro.org>
+
+ PR target/59142
+ * config/arm/predicates.md (vfp_hard_register_operand): New predicate.
+ * config/arm/arm.md (vfp_pop_multiple_with_writeback): Use
+ vfp_hard_register_operand.
+
+2013-12-19 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_init_simd_builtins):
Define builtin types for poly64_t poly128_t.
[(set (match_operand:SI 1 "s_register_operand" "+rk")
(plus:SI (match_dup 1)
(match_operand:SI 2 "const_int_operand" "I")))
- (set (match_operand:DF 3 "arm_hard_register_operand" "")
+ (set (match_operand:DF 3 "vfp_hard_register_operand" "")
(mem:DF (match_dup 1)))])]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"*
&& REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
})
+(define_predicate "vfp_hard_register_operand"
+ (match_code "reg")
+{
+ return (IS_VFP_REGNUM (REGNO (op)));
+})
+
(define_predicate "zero_operand"
(and (match_code "const_int,const_double,const_vector")
(match_test "op == CONST0_RTX (mode)")))