drm/i915: Always check dp_m2_n2 on pre-bdw

No point in special casing the check of dp_m2_n2 on pre-bdw platforms.
Either the transcoder has M2/N2 in which case the values should be
set to something sensible, or it doesn't in which case dp_m2_n2 is
always zeroed.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220128103757.22461-17-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8db219b..d55f878 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6483,13 +6483,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
        PIPE_CONF_CHECK_I(lane_count);
        PIPE_CONF_CHECK_X(lane_lat_optim_mask);
 
-       if (DISPLAY_VER(dev_priv) < 8) {
-               PIPE_CONF_CHECK_M_N(dp_m_n);
-
-               if (current_config->has_drrs)
-                       PIPE_CONF_CHECK_M_N(dp_m2_n2);
-       } else
+       if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
                PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
+       } else {
+               PIPE_CONF_CHECK_M_N(dp_m_n);
+               PIPE_CONF_CHECK_M_N(dp_m2_n2);
+       }
 
        PIPE_CONF_CHECK_X(output_types);