PCI: dwc: Simplify config space handling

The config space is divided in half for type 0 and type 1 accesses, but
this is pointless as there's only one iATU window which is
reconfigured on each access.

The only platform doing something custom is TI Keystone (surprise!).
It does its own mapping of the config space to avoid spliting the
config space and never actually uses va_cfg1_base as it has its own
config space accessors. With the splitting removed, Keystone can use the
default mapping of config space.

Link: https://lore.kernel.org/r/20200821035420.380495-20-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>

diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index d306914a1f9341288a79fc99c6ef4f4cf9e95c3a..983069a4a5610dbd3a78551ce6cdfb3b9da97fe7 100644 (file)
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -873,16 +873,8 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie,
        struct dw_pcie *pci = ks_pcie->pci;
        struct pcie_port *pp = &pci->pp;
        struct device *dev = &pdev->dev;
-       struct resource *res;
        int ret;
 
-       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
-       pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res);
-       if (IS_ERR(pp->va_cfg0_base))
-               return PTR_ERR(pp->va_cfg0_base);
-
-       pp->va_cfg1_base = pp->va_cfg0_base;
-
        ret = dw_pcie_host_init(pp);
        if (ret) {
                dev_err(dev, "failed to initialize host\n");

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index b40aeae7880900c3ce1da2f2a8693bca7bc16db3..38d7c89dbb211655280f7ee2e17c798933fe368e 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -308,10 +308,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
 
        cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
        if (cfg_res) {
-               pp->cfg0_size = resource_size(cfg_res) >> 1;
-               pp->cfg1_size = resource_size(cfg_res) >> 1;
+               pp->cfg0_size = resource_size(cfg_res);
                pp->cfg0_base = cfg_res->start;
-               pp->cfg1_base = cfg_res->start + pp->cfg0_size;
        } else if (!pp->va_cfg0_base) {
                dev_err(dev, "Missing *config* reg space\n");
        }
@@ -331,25 +329,22 @@ int dw_pcie_host_init(struct pcie_port *pp)
                        pp->io_base = pci_pio_to_address(win->res->start);
                        break;
                case 0:
-                       pp->cfg = win->res;
-                       pp->cfg0_size = resource_size(pp->cfg) >> 1;
-                       pp->cfg1_size = resource_size(pp->cfg) >> 1;
-                       pp->cfg0_base = pp->cfg->start;
-                       pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
+                       dev_err(dev, "Missing *config* reg space\n");
+                       pp->cfg0_size = resource_size(win->res);
+                       pp->cfg0_base = win->res->start;
+                       if (!pci->dbi_base) {
+                               pci->dbi_base = devm_pci_remap_cfgspace(dev,
+                                                               pp->cfg0_base,
+                                                               pp->cfg0_size);
+                               if (!pci->dbi_base) {
+                                       dev_err(dev, "Error with ioremap\n");
+                                       return -ENOMEM;
+                               }
+                       }
                        break;
                }
        }
 
-       if (!pci->dbi_base) {
-               pci->dbi_base = devm_pci_remap_cfgspace(dev,
-                                               pp->cfg->start,
-                                               resource_size(pp->cfg));
-               if (!pci->dbi_base) {
-                       dev_err(dev, "Error with ioremap\n");
-                       return -ENOMEM;
-               }
-       }
-
        if (!pp->va_cfg0_base) {
                pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
                                        pp->cfg0_base, pp->cfg0_size);
@@ -359,16 +354,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
                }
        }
 
-       if (!pp->va_cfg1_base) {
-               pp->va_cfg1_base = devm_pci_remap_cfgspace(dev,
-                                               pp->cfg1_base,
-                                               pp->cfg1_size);
-               if (!pp->va_cfg1_base) {
-                       dev_err(dev, "Error with ioremap\n");
-                       return -ENOMEM;
-               }
-       }
-
        ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
        if (ret)
                pci->num_viewport = 2;
@@ -446,32 +431,24 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
                                                unsigned int devfn, int where)
 {
        int type;
-       u32 busdev, cfg_size;
-       u64 cpu_addr;
-       void __iomem *va_cfg_base;
+       u32 busdev;
        struct pcie_port *pp = bus->sysdata;
        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 
        busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
                 PCIE_ATU_FUNC(PCI_FUNC(devfn));
 
-       if (pci_is_root_bus(bus->parent)) {
+       if (pci_is_root_bus(bus->parent))
                type = PCIE_ATU_TYPE_CFG0;
-               cpu_addr = pp->cfg0_base;
-               cfg_size = pp->cfg0_size;
-               va_cfg_base = pp->va_cfg0_base;
-       } else {
+       else
                type = PCIE_ATU_TYPE_CFG1;
-               cpu_addr = pp->cfg1_base;
-               cfg_size = pp->cfg1_size;
-               va_cfg_base = pp->va_cfg1_base;
-       }
+
 
        dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
-                                 type, cpu_addr,
-                                 busdev, cfg_size);
+                                 type, pp->cfg0_base,
+                                 busdev, pp->cfg0_size);
 
-       return va_cfg_base + where;
+       return pp->va_cfg0_base + where;
 }
 
 static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 00f5a72572178e58540ca346771e935c38553b27..48f45f810551e777019035889b1c031bdfffdbf6 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -169,13 +169,9 @@ struct pcie_port {
        u64                     cfg0_base;
        void __iomem            *va_cfg0_base;
        u32                     cfg0_size;
-       u64                     cfg1_base;
-       void __iomem            *va_cfg1_base;
-       u32                     cfg1_size;
        resource_size_t         io_base;
        phys_addr_t             io_bus_addr;
        u32                     io_size;
-       struct resource         *cfg;
        int                     irq;
        const struct dw_pcie_host_ops *ops;
        int                     msi_irq;