/* Enable IRQ_WDMA_END and IRQ_WDMA_START. */
cal_write(ctx->cal, CAL_HL_IRQENABLE_SET(1),
- CAL_HL_IRQ_MASK(ctx->dma_ctx));
+ CAL_HL_IRQ_WDMA_END_MASK(ctx->dma_ctx));
cal_write(ctx->cal, CAL_HL_IRQENABLE_SET(2),
- CAL_HL_IRQ_MASK(ctx->dma_ctx));
+ CAL_HL_IRQ_WDMA_START_MASK(ctx->dma_ctx));
}
void cal_ctx_stop(struct cal_ctx *ctx)
/* Disable IRQ_WDMA_END and IRQ_WDMA_START. */
cal_write(ctx->cal, CAL_HL_IRQENABLE_CLR(1),
- CAL_HL_IRQ_MASK(ctx->dma_ctx));
+ CAL_HL_IRQ_WDMA_END_MASK(ctx->dma_ctx));
cal_write(ctx->cal, CAL_HL_IRQENABLE_CLR(2),
- CAL_HL_IRQ_MASK(ctx->dma_ctx));
+ CAL_HL_IRQ_WDMA_START_MASK(ctx->dma_ctx));
ctx->dma.state = CAL_DMA_STOPPED;
}
cal_write(cal, CAL_HL_IRQSTATUS(1), status);
for (i = 0; i < ARRAY_SIZE(cal->ctx); ++i) {
- if (status & CAL_HL_IRQ_MASK(i))
+ if (status & CAL_HL_IRQ_WDMA_END_MASK(i))
cal_irq_wdma_end(cal->ctx[i]);
}
}
cal_write(cal, CAL_HL_IRQSTATUS(2), status);
for (i = 0; i < ARRAY_SIZE(cal->ctx); ++i) {
- if (status & CAL_HL_IRQ_MASK(i))
+ if (status & CAL_HL_IRQ_WDMA_START_MASK(i))
cal_irq_wdma_start(cal->ctx[i]);
}
}