DECLARE_GLOBAL_DATA_PTR;
-struct cpu_type cpu_type_list [] = {
+static struct cpu_type cpu_type_list[] = {
#if defined(CONFIG_MPC85xx)
CPU_TYPE_ENTRY(8533, 8533, 1),
CPU_TYPE_ENTRY(8535, 8535, 1),
#define compute_ppc_cpumask() 1
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
-struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
+static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
struct cpu_type *identify_cpu(u32 ver)
{
/*
* Return a 32-bit mask indicating which cores are present on this SOC.
*/
-u32 cpu_mask()
+u32 cpu_mask(void)
{
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
struct cpu_type *cpu = gd->cpu;
/*
* Return the number of cores on this SOC.
*/
-int cpu_numcores() {
+int cpu_numcores(void)
+{
struct cpu_type *cpu = gd->cpu;
/*
#include "ddr.h"
-unsigned int
+#if defined(CONFIG_FSL_DDR3)
+static unsigned int
compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
unsigned int number_of_dimms)
return 0;
}
+#endif
/*
* compute_lowest_common_dimm_parameters()