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[Tizen] Add coreclr crossgen2 skips for RPI4 for arm64
authorGleb Balykov <g.balykov@samsung.com>
Thu, 29 Sep 2022 09:17:11 +0000 (12:17 +0300)
committerGleb Balykov <g.balykov@samsung.com>
Thu, 29 Sep 2022 09:17:11 +0000 (12:17 +0300)
These are mostly a subset of src/tests/issues.targets with some additional excludes:

- BasicTestWithMcj is skipped because it manually invokes crossgen2

unsupportedCrossgenLibs.arm64.txt [new file with mode: 0644] patch | blob
unsupportedCrossgenTests.arm64.txt [new file with mode: 0644] patch | blob

diff --git a/unsupportedCrossgenLibs.arm64.txt b/unsupportedCrossgenLibs.arm64.txt
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/unsupportedCrossgenTests.arm64.txt b/unsupportedCrossgenTests.arm64.txt
new file mode 100644 (file)
index 0000000..7844c4a
--- /dev/null
+++ b/unsupportedCrossgenTests.arm64.txt
@@ -0,0 +1,3 @@
+JIT/Directed/debugging/poison/poison.sh
+baseservices/TieredCompilation/BasicTestWithMcj/BasicTestWithMcj.sh
+Interop/StructMarshalling/PInvoke/MarshalStructAsLayoutExp/MarshalStructAsLayoutExp.sh
Domain: Dotnet / Core;