Improve bndmov encoding with zero displacement

If x86-64 assembler doesn't support MPX, we encode bndmov instruction by
hand.  When displacement is zero, assembler generates shorter encoding.
This patch improves bndmov encoding with zero displacement so that ld.so
is identical when using assemblers with and without MPX support.

	* sysdeps/x86_64/dl-trampoline.S (_dl_runtime_resolve): Improve
	bndmov encoding with zero displacement.

diff --git a/ChangeLog b/ChangeLog
index f8765bb..c48416b 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2015-07-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * sysdeps/x86_64/dl-trampoline.S (_dl_runtime_resolve): Improve
+       bndmov encoding with zero displacement.
+
 2015-07-09  Igor Zamyatin  <igor.zamyatin@intel.com>
            H.J. Lu  <hongjiu.lu@intel.com>
 

diff --git a/sysdeps/x86_64/dl-trampoline.S b/sysdeps/x86_64/dl-trampoline.S
index b151d35..678c57f 100644 (file)
--- a/sysdeps/x86_64/dl-trampoline.S
+++ b/sysdeps/x86_64/dl-trampoline.S
@@ -80,7 +80,11 @@ _dl_runtime_resolve:
        bndmov %bnd2, REGISTER_SAVE_BND2(%rsp)
        bndmov %bnd3, REGISTER_SAVE_BND3(%rsp)
 # else
+#  if REGISTER_SAVE_BND0 == 0
+       .byte 0x66,0x0f,0x1b,0x04,0x24
+#  else
        .byte 0x66,0x0f,0x1b,0x44,0x24,REGISTER_SAVE_BND0
+#  endif
        .byte 0x66,0x0f,0x1b,0x4c,0x24,REGISTER_SAVE_BND1
        .byte 0x66,0x0f,0x1b,0x54,0x24,REGISTER_SAVE_BND2
        .byte 0x66,0x0f,0x1b,0x5c,0x24,REGISTER_SAVE_BND3
@@ -104,7 +108,11 @@ _dl_runtime_resolve:
        .byte 0x66,0x0f,0x1a,0x5c,0x24,REGISTER_SAVE_BND3
        .byte 0x66,0x0f,0x1a,0x54,0x24,REGISTER_SAVE_BND2
        .byte 0x66,0x0f,0x1a,0x4c,0x24,REGISTER_SAVE_BND1
+#  if REGISTER_SAVE_BND0 == 0
+       .byte 0x66,0x0f,0x1a,0x04,0x24
+#  else
        .byte 0x66,0x0f,0x1a,0x44,0x24,REGISTER_SAVE_BND0
+#  endif
 # endif
 #endif
        # Get register content back.