ARM64: Fix cache line size computation.

BUG=
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/268673020

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21290 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

diff --git a/src/arm64/cpu-arm64.cc b/src/arm64/cpu-arm64.cc
index 0ed7e9f..a96a7b1 100644 (file)
--- a/src/arm64/cpu-arm64.cc
+++ b/src/arm64/cpu-arm64.cc
@@ -39,8 +39,9 @@ class CacheLineSizes {
 
  private:
   uint32_t ExtractCacheLineSize(int cache_line_size_shift) const {
-    // The cache type register holds the size of the caches as a power of two.
-    return 1 << ((cache_type_register_ >> cache_line_size_shift) & 0xf);
+    // The cache type register holds the size of cache lines in words as a
+    // power of two.
+    return 4 << ((cache_type_register_ >> cache_line_size_shift) & 0xf);
   }
 
   uint32_t cache_type_register_;