drm/amdgpu: Use legacy TLB flush for gfx943

Invalidate TLBs via a legacy flush request (flush_type=0) prior to the
heavyweight flush requests (flush_type=2) in gmc_v9_0.c. This is
temporarily required to mitigate a bug causing CPC UTCL1 to return stale
translations after invalidation requests in address range mode.

v2: squash in long term fix "drm/amdgpu: disable extra gfx943 legacy flush on rev1+"

Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 95c3253..2eb67b5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -833,6 +833,11 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
                 */
                inv_req = gmc_v9_0_get_invalidate_req(vmid, 2);
                inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type);
+       } else if (flush_type == 2 &&
+                  adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) &&
+                  adev->rev_id == 0) {
+               inv_req = gmc_v9_0_get_invalidate_req(vmid, 0);
+               inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type);
        } else {
                inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
                inv_req2 = 0;
@@ -976,6 +981,13 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
                if (vega20_xgmi_wa)
                        kiq->pmf->kiq_invalidate_tlbs(ring,
                                                      pasid, 2, all_hub);
+
+               if (flush_type == 2 &&
+                   adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) &&
+                   adev->rev_id == 0)
+                       kiq->pmf->kiq_invalidate_tlbs(ring,
+                                               pasid, 0, all_hub);
+
                kiq->pmf->kiq_invalidate_tlbs(ring,
                                        pasid, flush_type, all_hub);
                r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);