/** Last member index in sbi_trap_regs */
#define SBI_TRAP_REGS_last 35
-/** Index of epc member in sbi_trap_info */
-#define SBI_TRAP_INFO_epc 0
/** Index of cause member in sbi_trap_info */
-#define SBI_TRAP_INFO_cause 1
+#define SBI_TRAP_INFO_cause 0
/** Index of tval member in sbi_trap_info */
-#define SBI_TRAP_INFO_tval 2
+#define SBI_TRAP_INFO_tval 1
/** Index of tval2 member in sbi_trap_info */
-#define SBI_TRAP_INFO_tval2 3
+#define SBI_TRAP_INFO_tval2 2
/** Index of tinst member in sbi_trap_info */
-#define SBI_TRAP_INFO_tinst 4
+#define SBI_TRAP_INFO_tinst 3
/** Index of gva member in sbi_trap_info */
-#define SBI_TRAP_INFO_gva 5
+#define SBI_TRAP_INFO_gva 4
/** Last member index in sbi_trap_info */
-#define SBI_TRAP_INFO_last 6
+#define SBI_TRAP_INFO_last 5
/* clang-format on */
/** Representation of trap details */
struct sbi_trap_info {
- /** epc Trap program counter */
- unsigned long epc;
/** cause Trap exception cause */
unsigned long cause;
/** tval Trap value */
&hmask, &trap)) {
ret = sbi_ipi_send_smode(hmask, 0);
} else {
- trap.epc = regs->mepc;
sbi_trap_redirect(regs, &trap);
out->skip_regs_update = true;
}
SBI_TLB_FENCE_I, source_hart);
ret = sbi_tlb_request(hmask, 0, &tlb_info);
} else {
- trap.epc = regs->mepc;
sbi_trap_redirect(regs, &trap);
out->skip_regs_update = true;
}
SBI_TLB_SFENCE_VMA, source_hart);
ret = sbi_tlb_request(hmask, 0, &tlb_info);
} else {
- trap.epc = regs->mepc;
sbi_trap_redirect(regs, &trap);
out->skip_regs_update = true;
}
source_hart);
ret = sbi_tlb_request(hmask, 0, &tlb_info);
} else {
- trap.epc = regs->mepc;
sbi_trap_redirect(regs, &trap);
out->skip_regs_update = true;
}
.global __sbi_expected_trap
__sbi_expected_trap:
/* Without H-extension so, MTVAL2 and MTINST CSRs and GVA not available */
- csrr a4, CSR_MEPC
- REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
csrr a4, CSR_MCAUSE
REG_S a4, SBI_TRAP_INFO_OFFSET(cause)(a3)
csrr a4, CSR_MTVAL
.global __sbi_expected_trap_hext
__sbi_expected_trap_hext:
/* With H-extension so, MTVAL2 and MTINST CSRs and GVA available */
- csrr a4, CSR_MEPC
- REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
csrr a4, CSR_MCAUSE
REG_S a4, SBI_TRAP_INFO_OFFSET(cause)(a3)
csrr a4, CSR_MTVAL
{
struct sbi_trap_info trap;
- trap.epc = regs->mepc;
trap.cause = CAUSE_ILLEGAL_INSTRUCTION;
trap.tval = insn;
trap.tval2 = 0;
if (unlikely((insn & 3) != 3)) {
insn = sbi_get_insn(regs->mepc, &uptrap);
if (uptrap.cause) {
- uptrap.epc = regs->mepc;
return sbi_trap_redirect(regs, &uptrap);
}
if ((insn & 3) != 3)
if (next_virt) {
/* Update VS-mode exception info */
csr_write(CSR_VSTVAL, trap->tval);
- csr_write(CSR_VSEPC, trap->epc);
+ csr_write(CSR_VSEPC, regs->mepc);
csr_write(CSR_VSCAUSE, trap->cause);
/* Set MEPC to VS-mode exception vector base */
} else {
/* Update S-mode exception info */
csr_write(CSR_STVAL, trap->tval);
- csr_write(CSR_SEPC, trap->epc);
+ csr_write(CSR_SEPC, regs->mepc);
csr_write(CSR_SCAUSE, trap->cause);
/* Set MEPC to S-mode exception vector base */
return regs;
}
/* Original trap_info */
- trap.epc = regs->mepc;
trap.cause = mcause;
trap.tval = mtval;
trap.tval2 = mtval2;
*/
insn = sbi_get_insn(regs->mepc, &uptrap);
if (uptrap.cause) {
- uptrap.epc = regs->mepc;
return sbi_trap_redirect(regs, &uptrap);
}
insn_len = INSN_LEN(insn);
*/
insn = sbi_get_insn(regs->mepc, &uptrap);
if (uptrap.cause) {
- uptrap.epc = regs->mepc;
return sbi_trap_redirect(regs, &uptrap);
}
insn_len = INSN_LEN(insn);
out_val->data_bytes[i] =
sbi_load_u8((void *)(orig_trap->tval + i), &uptrap);
if (uptrap.cause) {
- uptrap.epc = regs->mepc;
uptrap.tinst = sbi_misaligned_tinst_fixup(
orig_trap->tinst, uptrap.tinst, i);
return sbi_trap_redirect(regs, &uptrap);
sbi_store_u8((void *)(orig_trap->tval + i),
in_val.data_bytes[i], &uptrap);
if (uptrap.cause) {
- uptrap.epc = regs->mepc;
uptrap.tinst = sbi_misaligned_tinst_fixup(
orig_trap->tinst, uptrap.tinst, i);
return sbi_trap_redirect(regs, &uptrap);