arm64/sysreg: Standardise naming for MTE feature enumeration

In preparation for conversion to automatic generation refresh the names
given to the items in the MTE feture enumeration to reflect our standard
pattern for naming, corresponding to the architecture feature names they
reflect. No functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-17-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 5fc43f7..79bb9e5 100644 (file)
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -633,7 +633,7 @@ static inline bool id_aa64pfr1_mte(u64 pfr1)
 {
        u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_MTE_SHIFT);
 
-       return val >= ID_AA64PFR1_EL1_MTE;
+       return val >= ID_AA64PFR1_EL1_MTE_MTE2;
 }
 
 void __init setup_cpu_features(void);

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index d6df8fe..385242a 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -727,9 +727,9 @@
 #define ID_AA64PFR1_EL1_SME            1
 
 #define ID_AA64PFR1_EL1_MTE_NI         0x0
-#define ID_AA64PFR1_EL1_MTE_EL0                0x1
-#define ID_AA64PFR1_EL1_MTE            0x2
-#define ID_AA64PFR1_EL1_MTE_ASYMM      0x3
+#define ID_AA64PFR1_EL1_MTE_IMP                0x1
+#define ID_AA64PFR1_EL1_MTE_MTE2       0x2
+#define ID_AA64PFR1_EL1_MTE_MTE3       0x3
 
 /* id_aa64mmfr0 */
 #define ID_AA64MMFR0_EL1_ECV_SHIFT             60

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 7e58cb5..2afc0a8 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2543,7 +2543,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
                .sys_reg = SYS_ID_AA64PFR1_EL1,
                .field_pos = ID_AA64PFR1_EL1_MTE_SHIFT,
                .field_width = 4,
-               .min_field_value = ID_AA64PFR1_EL1_MTE,
+               .min_field_value = ID_AA64PFR1_EL1_MTE_MTE2,
                .sign = FTR_UNSIGNED,
                .cpu_enable = cpu_enable_mte,
        },
@@ -2555,7 +2555,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
                .sys_reg = SYS_ID_AA64PFR1_EL1,
                .field_pos = ID_AA64PFR1_EL1_MTE_SHIFT,
                .field_width = 4,
-               .min_field_value = ID_AA64PFR1_EL1_MTE_ASYMM,
+               .min_field_value = ID_AA64PFR1_EL1_MTE_MTE3,
                .sign = FTR_UNSIGNED,
        },
 #endif /* CONFIG_ARM64_MTE */
@@ -2748,8 +2748,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
        HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
 #endif
 #ifdef CONFIG_ARM64_MTE
-       HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
-       HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),
+       HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE),
+       HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3),
 #endif /* CONFIG_ARM64_MTE */
        HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
        HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 15539da..5f7784e 100644 (file)
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -435,7 +435,7 @@ SYM_FUNC_START(__cpu_setup)
         */
        mrs     x10, ID_AA64PFR1_EL1
        ubfx    x10, x10, #ID_AA64PFR1_EL1_MTE_SHIFT, #4
-       cmp     x10, #ID_AA64PFR1_EL1_MTE
+       cmp     x10, #ID_AA64PFR1_EL1_MTE_MTE2
        b.lt    1f
 
        /* Normal Tagged memory type at the corresponding MAIR index */