RISC-V: Fix testsuite fail on RV32
authorKito Cheng <kito.cheng@sifive.com>
Fri, 14 Apr 2023 07:34:40 +0000 (15:34 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Mon, 17 Apr 2023 01:51:36 +0000 (09:51 +0800)
gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/scalar_move-2.c: Adjust include way
for riscv_vector.h
* gcc.target/riscv/rvv/base/spill-sp-adjust.c: Add missing
-mabi.

gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-2.c
gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c

index 39fc107..5b538ba 100644 (file)
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** foo1:
index f8c9f63..a6598a5 100644 (file)
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
 
 #include "spill-1.c"