let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1 in {
def PseudoReadVLENB : Pseudo<(outs GPR:$rd), (ins),
- [(set GPR:$rd, (riscv_read_vlenb))]>;
+ [(set GPR:$rd, (riscv_read_vlenb))]>,
+ Sched<[WriteRdVLENB]>;
}
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1,
//===----------------------------------------------------------------------===//
/// Define scheduler resources associated with def operands.
+// 3.6 Vector Byte Length vlenb
+def WriteRdVLENB : SchedWrite;
+
// 7. Vector Loads and Stores
// 7.4. Vector Unit-Stride Instructions
def WriteVLDE8 : SchedWrite;
multiclass UnsupportedSchedV {
let Unsupported = true in {
+// 3.6 Vector Byte Length vlenb
+def : WriteRes<WriteRdVLENB, []>;
+
// 7. Vector Loads and Stores
def : WriteRes<WriteVLDE8, []>;
def : WriteRes<WriteVLDE16, []>;