drm/amdgpu: Modify nbio block to fit for the unified ras block data and ops

1.Modify nbio block to fit for the unified ras block data and ops.
2.Change amdgpu_nbio_ras_funcs to amdgpu_nbio_ras, and the corresponding variable name remove _funcs suffix.
3.Remove the const flag of mmhub ras variable so that nbio ras block can be able to be inserted into amdgpu device ras block link list.
4.Invoke amdgpu_ras_register_ras_block function to register nbio ras block into amdgpu device ras block link list.
5.Remove the redundant code about nbio in amdgpu_ras.c after using the unified ras block.

Signed-off-by: yipechai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index f5cbc27..ea3e8c6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -199,13 +199,13 @@ static irqreturn_t amdgpu_irq_handler(int irq, void *arg)
         * ack the interrupt if it is there
         */
        if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) {
-               if (adev->nbio.ras_funcs &&
-                   adev->nbio.ras_funcs->handle_ras_controller_intr_no_bifring)
-                       adev->nbio.ras_funcs->handle_ras_controller_intr_no_bifring(adev);
+               if (adev->nbio.ras &&
+                   adev->nbio.ras->handle_ras_controller_intr_no_bifring)
+                       adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
 
-               if (adev->nbio.ras_funcs &&
-                   adev->nbio.ras_funcs->handle_ras_err_event_athub_intr_no_bifring)
-                       adev->nbio.ras_funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
+               if (adev->nbio.ras &&
+                   adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
+                       adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
        }
 
        return ret;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
index 6afb02f..6ace2e3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
@@ -22,7 +22,7 @@
 #include "amdgpu.h"
 #include "amdgpu_ras.h"
 
-int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev)
+int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, void *ras_info)
 {
        int r;
        struct ras_ih_if ih_info = {

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index 8430522..4afb76d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -47,15 +47,12 @@ struct nbio_hdp_flush_reg {
        u32 ref_and_mask_sdma7;
 };
 
-struct amdgpu_nbio_ras_funcs {
+struct amdgpu_nbio_ras {
+       struct amdgpu_ras_block_object ras_block;
        void (*handle_ras_controller_intr_no_bifring)(struct amdgpu_device *adev);
        void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
        int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
        int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
-       void (*query_ras_error_count)(struct amdgpu_device *adev,
-                                     void *ras_error_status);
-       int (*ras_late_init)(struct amdgpu_device *adev);
-       void (*ras_fini)(struct amdgpu_device *adev);
 };
 
 struct amdgpu_nbio_funcs {
@@ -104,9 +101,9 @@ struct amdgpu_nbio {
        struct amdgpu_irq_src ras_err_event_athub_irq;
        struct ras_common_if *ras_if;
        const struct amdgpu_nbio_funcs *funcs;
-       const struct amdgpu_nbio_ras_funcs *ras_funcs;
+       struct amdgpu_nbio_ras  *ras;
 };
 
-int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev);
+int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, void *ras_info);
 void amdgpu_nbio_ras_fini(struct amdgpu_device *adev);
 #endif

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 0ce26fd..6d1ca9e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -999,10 +999,6 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
                        block_obj->hw_ops->query_ras_error_status(adev);
                break;
        case AMDGPU_RAS_BLOCK__PCIE_BIF:
-               if (adev->nbio.ras_funcs &&
-                   adev->nbio.ras_funcs->query_ras_error_count)
-                       adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
-               break;
        case AMDGPU_RAS_BLOCK__XGMI_WAFL:
        case AMDGPU_RAS_BLOCK__HDP:
                if (!block_obj || !block_obj->hw_ops)   {
@@ -2385,24 +2381,26 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
        case CHIP_VEGA20:
        case CHIP_ARCTURUS:
        case CHIP_ALDEBARAN:
-               if (!adev->gmc.xgmi.connected_to_cpu)
-                       adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs;
+               if (!adev->gmc.xgmi.connected_to_cpu) {
+                       adev->nbio.ras = &nbio_v7_4_ras;
+                       amdgpu_ras_register_ras_block(adev, &adev->nbio.ras->ras_block);
+               }
                break;
        default:
                /* nbio ras is not available */
                break;
        }
 
-       if (adev->nbio.ras_funcs &&
-           adev->nbio.ras_funcs->init_ras_controller_interrupt) {
-               r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev);
+       if (adev->nbio.ras &&
+           adev->nbio.ras->init_ras_controller_interrupt) {
+               r = adev->nbio.ras->init_ras_controller_interrupt(adev);
                if (r)
                        goto release_con;
        }
 
-       if (adev->nbio.ras_funcs &&
-           adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) {
-               r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev);
+       if (adev->nbio.ras &&
+           adev->nbio.ras->init_ras_err_event_athub_interrupt) {
+               r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
                if (r)
                        goto release_con;
        }

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index dc5e937..39974b4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -658,16 +658,25 @@ static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev,
                       DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
 }
 
-const struct amdgpu_nbio_ras_funcs nbio_v7_4_ras_funcs = {
+const struct amdgpu_ras_block_hw_ops nbio_v7_4_ras_hw_ops = {
+       .query_ras_error_count = nbio_v7_4_query_ras_error_count,
+};
+
+struct amdgpu_nbio_ras nbio_v7_4_ras = {
+       .ras_block = {
+               .name = "pcie_bif",
+               .block = AMDGPU_RAS_BLOCK__PCIE_BIF,
+               .hw_ops = &nbio_v7_4_ras_hw_ops,
+               .ras_late_init = amdgpu_nbio_ras_late_init,
+               .ras_fini = amdgpu_nbio_ras_fini,
+       },
        .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
        .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
        .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
        .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
-       .query_ras_error_count = nbio_v7_4_query_ras_error_count,
-       .ras_late_init = amdgpu_nbio_ras_late_init,
-       .ras_fini = amdgpu_nbio_ras_fini,
 };
 
+
 static void nbio_v7_4_program_ltr(struct amdgpu_device *adev)
 {
        uint32_t def, data;

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
index cc5692d..7490022 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
@@ -29,6 +29,6 @@
 extern const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg;
 extern const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg_ald;
 extern const struct amdgpu_nbio_funcs nbio_v7_4_funcs;
-extern const struct amdgpu_nbio_ras_funcs nbio_v7_4_ras_funcs;
+extern struct amdgpu_nbio_ras nbio_v7_4_ras;
 
 #endif

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 0fc1747..6c8fcc4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1224,9 +1224,8 @@ static int soc15_common_late_init(void *handle)
        if (amdgpu_sriov_vf(adev))
                xgpu_ai_mailbox_get_irq(adev);
 
-       if (adev->nbio.ras_funcs &&
-           adev->nbio.ras_funcs->ras_late_init)
-               r = adev->nbio.ras_funcs->ras_late_init(adev);
+       if (adev->nbio.ras && adev->nbio.ras->ras_block.ras_late_init)
+               r = adev->nbio.ras->ras_block.ras_late_init(adev, NULL);
 
        return r;
 }
@@ -1249,9 +1248,8 @@ static int soc15_common_sw_fini(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       if (adev->nbio.ras_funcs &&
-           adev->nbio.ras_funcs->ras_fini)
-               adev->nbio.ras_funcs->ras_fini(adev);
+       if (adev->nbio.ras && adev->nbio.ras->ras_block.ras_fini)
+               adev->nbio.ras->ras_block.ras_fini(adev);
 
        if (adev->df.funcs &&
            adev->df.funcs->sw_fini)
@@ -1318,11 +1316,11 @@ static int soc15_common_hw_fini(void *handle)
 
        if (adev->nbio.ras_if &&
            amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
-               if (adev->nbio.ras_funcs &&
-                   adev->nbio.ras_funcs->init_ras_controller_interrupt)
+               if (adev->nbio.ras &&
+                   adev->nbio.ras->init_ras_controller_interrupt)
                        amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
-               if (adev->nbio.ras_funcs &&
-                   adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt)
+               if (adev->nbio.ras &&
+                   adev->nbio.ras->init_ras_err_event_athub_interrupt)
                        amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
        }