freedreno/a4xx+: Increase max texture size to 16384.
authorEric Anholt <eric@anholt.net>
Wed, 6 May 2020 21:43:02 +0000 (14:43 -0700)
committerMarge Bot <eric+marge@anholt.net>
Wed, 13 May 2020 19:18:16 +0000 (19:18 +0000)
Noticed when poking around with texture layouts and found that my big
texture layout from the blob buffer overflowed.  Values come from
http://vulkan.gpuinfo.org for Adreno 418, 512, 630.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4931>

src/freedreno/fdl/freedreno_layout.h
src/gallium/drivers/freedreno/freedreno_gmem.h
src/gallium/drivers/freedreno/freedreno_screen.c
src/gallium/drivers/freedreno/freedreno_util.h

index 011cf13..a6a12ba 100644 (file)
@@ -75,7 +75,7 @@
  * texture.
  */
 
-#define FDL_MAX_MIP_LEVELS 14
+#define FDL_MAX_MIP_LEVELS 15
 
 struct fdl_slice {
        uint32_t offset;         /* offset of first layer in slice */
index 35fc9c3..6a98e26 100644 (file)
@@ -62,7 +62,7 @@ struct fd_gmem_stateobj {
        uint8_t num_vsc_pipes;   /* number of pipes for a20x */
 
        struct fd_vsc_pipe vsc_pipe[32];
-       struct fd_tile     tile[512];
+       struct fd_tile     tile[2048];
 
        struct list_head node;
 };
index fd15e1f..d19f648 100644 (file)
@@ -403,9 +403,15 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 
        /* Texturing. */
        case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
-               return 1 << (MAX_MIP_LEVELS - 1);
+               if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
+                       return 16384;
+               else
+                       return 8192;
        case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
-               return MAX_MIP_LEVELS;
+               if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
+                       return 15;
+               else
+                       return 14;
        case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
                return 11;
 
index c2380c8..806f816 100644 (file)
@@ -50,8 +50,6 @@ enum adreno_pa_su_sc_draw fd_polygon_mode(unsigned mode);
 enum adreno_stencil_op fd_stencil_op(unsigned op);
 
 #define A3XX_MAX_MIP_LEVELS 14
-/* TBD if it is same on a2xx, but for now: */
-#define MAX_MIP_LEVELS A3XX_MAX_MIP_LEVELS
 
 #define A2XX_MAX_RENDER_TARGETS 1
 #define A3XX_MAX_RENDER_TARGETS 4