drm/amdgpu:enable MCBP for SR-IOV (v2)

Apply the new IB during IB emit for SRIOV with MCBP

v2: agd: use define instead of magic number

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 0050b09..c59bb38 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6564,6 +6564,9 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
        control |= ib->length_dw | (vm_id << 24);
 
+       if (amdgpu_sriov_vf(ring->adev) && ib->flags & AMDGPU_IB_FLAG_PREEMPT)
+               control |= INDIRECT_BUFFER_PRE_ENB(1);
+
        amdgpu_ring_write(ring, header);
        amdgpu_ring_write(ring,
 #ifdef __BIG_ENDIAN

diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
index 7a3863a..b3a86e0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vid.h
+++ b/drivers/gpu/drm/amd/amdgpu/vid.h
@@ -195,6 +195,7 @@
                 * 1 - Stream
                 * 2 - Bypass
                 */
+#define     INDIRECT_BUFFER_PRE_ENB(x)          ((x) << 21)
 #define        PACKET3_COPY_DATA                               0x40
 #define        PACKET3_PFP_SYNC_ME                             0x42
 #define        PACKET3_SURFACE_SYNC                            0x43