; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -mattr=+m,+zba -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64ZBA
+; RUN: | FileCheck %s -check-prefixes=RV64ZBA,RV64ZBANOZBB
+; RUN: llc -mtriple=riscv64 -mattr=+m,+zba,+zbb -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefixes=RV64ZBA,RV64ZBAZBB
define i64 @slliuw(i64 %a) nounwind {
; RV64I-LABEL: slliuw:
%e = add i64 %c, %d
ret i64 %e
}
+
+; Make sure we use sext.h+slli+srli for Zba+Zbb.
+; FIXME: The RV64I and Zba only cases can be done with only 3 shifts.
+define zeroext i32 @sext_ashr_zext_i8(i8 %a) nounwind {
+; RV64I-LABEL: sext_ashr_zext_i8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 56
+; RV64I-NEXT: srai a0, a0, 56
+; RV64I-NEXT: slli a0, a0, 23
+; RV64I-NEXT: srli a0, a0, 32
+; RV64I-NEXT: ret
+;
+; RV64ZBANOZBB-LABEL: sext_ashr_zext_i8:
+; RV64ZBANOZBB: # %bb.0:
+; RV64ZBANOZBB-NEXT: slli a0, a0, 56
+; RV64ZBANOZBB-NEXT: srai a0, a0, 56
+; RV64ZBANOZBB-NEXT: slli a0, a0, 23
+; RV64ZBANOZBB-NEXT: srli a0, a0, 32
+; RV64ZBANOZBB-NEXT: ret
+;
+; RV64ZBAZBB-LABEL: sext_ashr_zext_i8:
+; RV64ZBAZBB: # %bb.0:
+; RV64ZBAZBB-NEXT: sext.b a0, a0
+; RV64ZBAZBB-NEXT: slli a0, a0, 23
+; RV64ZBAZBB-NEXT: srli a0, a0, 32
+; RV64ZBAZBB-NEXT: ret
+ %ext = sext i8 %a to i32
+ %1 = ashr i32 %ext, 9
+ ret i32 %1
+}
+
+; Make sure we use sext.h+slli+srli for Zba+Zbb.
+; FIXME: The RV64I and Zba only cases can be done with only 3 shifts.
+define zeroext i32 @sext_ashr_zext_i16(i16 %a) nounwind {
+; RV64I-LABEL: sext_ashr_zext_i16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 48
+; RV64I-NEXT: srai a0, a0, 48
+; RV64I-NEXT: slli a0, a0, 23
+; RV64I-NEXT: srli a0, a0, 32
+; RV64I-NEXT: ret
+;
+; RV64ZBANOZBB-LABEL: sext_ashr_zext_i16:
+; RV64ZBANOZBB: # %bb.0:
+; RV64ZBANOZBB-NEXT: slli a0, a0, 48
+; RV64ZBANOZBB-NEXT: srai a0, a0, 48
+; RV64ZBANOZBB-NEXT: slli a0, a0, 23
+; RV64ZBANOZBB-NEXT: srli a0, a0, 32
+; RV64ZBANOZBB-NEXT: ret
+;
+; RV64ZBAZBB-LABEL: sext_ashr_zext_i16:
+; RV64ZBAZBB: # %bb.0:
+; RV64ZBAZBB-NEXT: sext.h a0, a0
+; RV64ZBAZBB-NEXT: slli a0, a0, 23
+; RV64ZBAZBB-NEXT: srli a0, a0, 32
+; RV64ZBAZBB-NEXT: ret
+ %ext = sext i16 %a to i32
+ %1 = ashr i32 %ext, 9
+ ret i32 %1
+}