drm/i915: Pass crtc state to DPIO PHY functions

Rather than digging through encoder->crtc and crtc->config in the
DPIO PHY functions, pass down the correct crtc state from the caller.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171031205123.13123-6-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5e6938d..19b679c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4200,18 +4200,25 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
                              u32 deemph_reg_value, u32 margin_reg_value,
                              bool uniq_trans_scale);
 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
+                             const struct intel_crtc_state *crtc_state,
                              bool reset);
-void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
-void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
+void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
+                           const struct intel_crtc_state *crtc_state);
+void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
+                               const struct intel_crtc_state *crtc_state);
 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
-void chv_phy_post_pll_disable(struct intel_encoder *encoder);
+void chv_phy_post_pll_disable(struct intel_encoder *encoder,
+                             const struct intel_crtc_state *old_crtc_state);
 
 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
                              u32 demph_reg_value, u32 preemph_reg_value,
                              u32 uniqtranscale_reg_value, u32 tx3_demph);
-void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
-void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
-void vlv_phy_reset_lanes(struct intel_encoder *encoder);
+void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
+                           const struct intel_crtc_state *crtc_state);
+void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
+                               const struct intel_crtc_state *crtc_state);
+void vlv_phy_reset_lanes(struct intel_encoder *encoder,
+                        const struct intel_crtc_state *old_crtc_state);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4f64d83..0151c8d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2781,7 +2781,7 @@ static void chv_post_disable_dp(struct intel_encoder *encoder,
        mutex_lock(&dev_priv->sb_lock);
 
        /* Assert data lane reset */
-       chv_data_lane_soft_reset(encoder, true);
+       chv_data_lane_soft_reset(encoder, old_crtc_state, true);
 
        mutex_unlock(&dev_priv->sb_lock);
 }
@@ -3091,7 +3091,7 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder,
                              const struct intel_crtc_state *pipe_config,
                              const struct drm_connector_state *conn_state)
 {
-       vlv_phy_pre_encoder_enable(encoder);
+       vlv_phy_pre_encoder_enable(encoder, pipe_config);
 
        intel_enable_dp(encoder, pipe_config, conn_state);
 }
@@ -3102,14 +3102,14 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
 {
        intel_dp_prepare(encoder, pipe_config);
 
-       vlv_phy_pre_pll_enable(encoder);
+       vlv_phy_pre_pll_enable(encoder, pipe_config);
 }
 
 static void chv_pre_enable_dp(struct intel_encoder *encoder,
                              const struct intel_crtc_state *pipe_config,
                              const struct drm_connector_state *conn_state)
 {
-       chv_phy_pre_encoder_enable(encoder);
+       chv_phy_pre_encoder_enable(encoder, pipe_config);
 
        intel_enable_dp(encoder, pipe_config, conn_state);
 
@@ -3123,14 +3123,14 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
 {
        intel_dp_prepare(encoder, pipe_config);
 
-       chv_phy_pre_pll_enable(encoder);
+       chv_phy_pre_pll_enable(encoder, pipe_config);
 }
 
 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
-                                   const struct intel_crtc_state *pipe_config,
-                                   const struct drm_connector_state *conn_state)
+                                   const struct intel_crtc_state *old_crtc_state,
+                                   const struct drm_connector_state *old_conn_state)
 {
-       chv_phy_post_pll_disable(encoder);
+       chv_phy_post_pll_disable(encoder, old_crtc_state);
 }
 
 /*

diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 490a42d..5958d3d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -733,11 +733,12 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 }
 
 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
+                             const struct intel_crtc_state *crtc_state,
                              bool reset)
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
-       struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
        enum pipe pipe = crtc->pipe;
        uint32_t val;
 
@@ -776,17 +777,16 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
        }
 }
 
-void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
+void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
+                           const struct intel_crtc_state *crtc_state)
 {
        struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-       struct drm_device *dev = encoder->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
-       struct intel_crtc *intel_crtc =
-               to_intel_crtc(encoder->base.crtc);
+       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
        enum dpio_channel ch = vlv_dport_to_channel(dport);
-       enum pipe pipe = intel_crtc->pipe;
+       enum pipe pipe = crtc->pipe;
        unsigned int lane_mask =
-               intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
+               intel_dp_unused_lane_mask(crtc_state->lane_count);
        u32 val;
 
        /*
@@ -802,7 +802,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
        mutex_lock(&dev_priv->sb_lock);
 
        /* Assert data lane reset */
-       chv_data_lane_soft_reset(encoder, true);
+       chv_data_lane_soft_reset(encoder, crtc_state, true);
 
        /* program left/right clock distribution */
        if (pipe != PIPE_B) {
@@ -832,7 +832,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
                val |= CHV_PCS_USEDCLKCHANNEL;
        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
 
-       if (intel_crtc->config->lane_count > 2) {
+       if (crtc_state->lane_count > 2) {
                val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
                val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
                if (pipe != PIPE_B)
@@ -857,16 +857,15 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
        mutex_unlock(&dev_priv->sb_lock);
 }
 
-void chv_phy_pre_encoder_enable(struct intel_encoder *encoder)
+void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
+                               const struct intel_crtc_state *crtc_state)
 {
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
-       struct drm_device *dev = encoder->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
-       struct intel_crtc *intel_crtc =
-               to_intel_crtc(encoder->base.crtc);
+       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
        enum dpio_channel ch = vlv_dport_to_channel(dport);
-       int pipe = intel_crtc->pipe;
+       enum pipe pipe = crtc->pipe;
        int data, i, stagger;
        u32 val;
 
@@ -877,16 +876,16 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder)
        val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
 
-       if (intel_crtc->config->lane_count > 2) {
+       if (crtc_state->lane_count > 2) {
                val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
                val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
                vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
        }
 
        /* Program Tx lane latency optimal setting*/
-       for (i = 0; i < intel_crtc->config->lane_count; i++) {
+       for (i = 0; i < crtc_state->lane_count; i++) {
                /* Set the upar bit */
-               if (intel_crtc->config->lane_count == 1)
+               if (crtc_state->lane_count == 1)
                        data = 0x0;
                else
                        data = (i == 1) ? 0x0 : 0x1;
@@ -895,13 +894,13 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder)
        }
 
        /* Data lane stagger programming */
-       if (intel_crtc->config->port_clock > 270000)
+       if (crtc_state->port_clock > 270000)
                stagger = 0x18;
-       else if (intel_crtc->config->port_clock > 135000)
+       else if (crtc_state->port_clock > 135000)
                stagger = 0xd;
-       else if (intel_crtc->config->port_clock > 67500)
+       else if (crtc_state->port_clock > 67500)
                stagger = 0x7;
-       else if (intel_crtc->config->port_clock > 33750)
+       else if (crtc_state->port_clock > 33750)
                stagger = 0x4;
        else
                stagger = 0x2;
@@ -910,7 +909,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder)
        val |= DPIO_TX2_STAGGER_MASK(0x1f);
        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
 
-       if (intel_crtc->config->lane_count > 2) {
+       if (crtc_state->lane_count > 2) {
                val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
                val |= DPIO_TX2_STAGGER_MASK(0x1f);
                vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
@@ -923,7 +922,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder)
                       DPIO_TX1_STAGGER_MULT(6) |
                       DPIO_TX2_STAGGER_MULT(0));
 
-       if (intel_crtc->config->lane_count > 2) {
+       if (crtc_state->lane_count > 2) {
                vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
                               DPIO_LANESTAGGER_STRAP(stagger) |
                               DPIO_LANESTAGGER_STRAP_OVRD |
@@ -933,7 +932,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder)
        }
 
        /* Deassert data lane reset */
-       chv_data_lane_soft_reset(encoder, false);
+       chv_data_lane_soft_reset(encoder, crtc_state, false);
 
        mutex_unlock(&dev_priv->sb_lock);
 }
@@ -949,10 +948,11 @@ void chv_phy_release_cl2_override(struct intel_encoder *encoder)
        }
 }
 
-void chv_phy_post_pll_disable(struct intel_encoder *encoder)
+void chv_phy_post_pll_disable(struct intel_encoder *encoder,
+                             const struct intel_crtc_state *old_crtc_state)
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-       enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
+       enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe;
        u32 val;
 
        mutex_lock(&dev_priv->sb_lock);
@@ -990,7 +990,7 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
        struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
        enum dpio_channel port = vlv_dport_to_channel(dport);
-       int pipe = intel_crtc->pipe;
+       enum pipe pipe = intel_crtc->pipe;
 
        mutex_lock(&dev_priv->sb_lock);
        vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
@@ -1008,15 +1008,14 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
        mutex_unlock(&dev_priv->sb_lock);
 }
 
-void vlv_phy_pre_pll_enable(struct intel_encoder *encoder)
+void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
+                           const struct intel_crtc_state *crtc_state)
 {
        struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-       struct drm_device *dev = encoder->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
-       struct intel_crtc *intel_crtc =
-               to_intel_crtc(encoder->base.crtc);
+       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
        enum dpio_channel port = vlv_dport_to_channel(dport);
-       int pipe = intel_crtc->pipe;
+       enum pipe pipe = crtc->pipe;
 
        /* Program Tx lane resets to default */
        mutex_lock(&dev_priv->sb_lock);
@@ -1036,15 +1035,15 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder)
        mutex_unlock(&dev_priv->sb_lock);
 }
 
-void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder)
+void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
+                               const struct intel_crtc_state *crtc_state)
 {
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
-       struct drm_device *dev = encoder->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
-       struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
        enum dpio_channel port = vlv_dport_to_channel(dport);
-       int pipe = intel_crtc->pipe;
+       enum pipe pipe = crtc->pipe;
        u32 val;
 
        mutex_lock(&dev_priv->sb_lock);
@@ -1066,14 +1065,14 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder)
        mutex_unlock(&dev_priv->sb_lock);
 }
 
-void vlv_phy_reset_lanes(struct intel_encoder *encoder)
+void vlv_phy_reset_lanes(struct intel_encoder *encoder,
+                        const struct intel_crtc_state *old_crtc_state)
 {
        struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-       struct intel_crtc *intel_crtc =
-               to_intel_crtc(encoder->base.crtc);
+       struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
        enum dpio_channel port = vlv_dport_to_channel(dport);
-       int pipe = intel_crtc->pipe;
+       enum pipe pipe = crtc->pipe;
 
        mutex_lock(&dev_priv->sb_lock);
        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index fa1c793..1f2258d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1683,10 +1683,9 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
                                const struct drm_connector_state *conn_state)
 {
        struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-       struct drm_device *dev = encoder->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-       vlv_phy_pre_encoder_enable(encoder);
+       vlv_phy_pre_encoder_enable(encoder, pipe_config);
 
        /* HDMI 1.0V-2dB */
        vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
@@ -1707,7 +1706,7 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
 {
        intel_hdmi_prepare(encoder, pipe_config);
 
-       vlv_phy_pre_pll_enable(encoder);
+       vlv_phy_pre_pll_enable(encoder, pipe_config);
 }
 
 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
@@ -1716,14 +1715,14 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
 {
        intel_hdmi_prepare(encoder, pipe_config);
 
-       chv_phy_pre_pll_enable(encoder);
+       chv_phy_pre_pll_enable(encoder, pipe_config);
 }
 
 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
                                      const struct intel_crtc_state *old_crtc_state,
                                      const struct drm_connector_state *old_conn_state)
 {
-       chv_phy_post_pll_disable(encoder);
+       chv_phy_post_pll_disable(encoder, old_crtc_state);
 }
 
 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
@@ -1731,7 +1730,7 @@ static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
                                  const struct drm_connector_state *old_conn_state)
 {
        /* Reset lanes to avoid HDMI flicker (VLV w/a) */
-       vlv_phy_reset_lanes(encoder);
+       vlv_phy_reset_lanes(encoder, old_crtc_state);
 }
 
 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
@@ -1744,7 +1743,7 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder,
        mutex_lock(&dev_priv->sb_lock);
 
        /* Assert data lane reset */
-       chv_data_lane_soft_reset(encoder, true);
+       chv_data_lane_soft_reset(encoder, old_crtc_state, true);
 
        mutex_unlock(&dev_priv->sb_lock);
 }
@@ -1757,7 +1756,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
 
-       chv_phy_pre_encoder_enable(encoder);
+       chv_phy_pre_encoder_enable(encoder, pipe_config);
 
        /* FIXME: Program the support xxx V-dB */
        /* Use 800mV-0dB */