[llvm-mca] Minor refactoring. NFCI

Also, removed a couple of unused methods from class Instruction.

llvm-svn: 328198

diff --git a/llvm/tools/llvm-mca/Instruction.cpp b/llvm/tools/llvm-mca/Instruction.cpp
index edf321a..de7c5c6 100644 (file)
--- a/llvm/tools/llvm-mca/Instruction.cpp
+++ b/llvm/tools/llvm-mca/Instruction.cpp
@@ -108,7 +108,7 @@ void Instruction::execute() {
   Stage = IS_EXECUTING;
 
   // Set the cycles left before the write-back stage.
-  setCyclesLeft(Desc.MaxLatency);
+  CyclesLeft = Desc.MaxLatency;
 
   for (UniqueDef &Def : Defs)
     Def->onInstructionIssued();

diff --git a/llvm/tools/llvm-mca/Instruction.h b/llvm/tools/llvm-mca/Instruction.h
index a4a1498..fb9551d 100644 (file)
--- a/llvm/tools/llvm-mca/Instruction.h
+++ b/llvm/tools/llvm-mca/Instruction.h
@@ -285,10 +285,7 @@ public:
   VecUses &getUses() { return Uses; }
   const VecUses &getUses() const { return Uses; }
   const InstrDesc &getDesc() const { return Desc; }
-
   unsigned getRCUTokenID() const { return RCUTokenID; }
-  int getCyclesLeft() const { return CyclesLeft; }
-  void setCyclesLeft(int Cycles) { CyclesLeft = Cycles; }
 
   // Transition to the dispatch stage, and assign a RCUToken to this
   // instruction. The RCUToken is used to track the completion of every

diff --git a/llvm/tools/llvm-mca/LSUnit.cpp b/llvm/tools/llvm-mca/LSUnit.cpp
index 672af52..115ef8f 100644 (file)
--- a/llvm/tools/llvm-mca/LSUnit.cpp
+++ b/llvm/tools/llvm-mca/LSUnit.cpp
@@ -12,6 +12,7 @@
 ///
 //===----------------------------------------------------------------------===//
 
+#include "Instruction.h"
 #include "LSUnit.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
@@ -49,9 +50,31 @@ void LSUnit::assignSQSlot(unsigned Index) {
   StoreQueue.insert(Index);
 }
 
+bool LSUnit::reserve(unsigned Index, const InstrDesc &Desc) {
+  unsigned MayLoad = Desc.MayLoad;
+  unsigned MayStore = Desc.MayStore;
+  unsigned IsMemBarrier = Desc.HasSideEffects;
+  if (!MayLoad && !MayStore)
+    return false;
+
+  if (MayLoad) {
+    if (IsMemBarrier)
+      LoadBarriers.insert(Index);
+    assignLQSlot(Index);
+  }
+  if (MayStore) {
+    if (IsMemBarrier)
+      StoreBarriers.insert(Index);
+    assignSQSlot(Index);
+  }
+  return true;
+}
+
 bool LSUnit::isReady(unsigned Index) const {
   bool IsALoad = LoadQueue.count(Index) != 0;
   bool IsAStore = StoreQueue.count(Index) != 0;
+  assert((IsALoad || IsAStore) && "Instruction is not in queue!");
+
   unsigned LoadBarrierIndex = LoadBarriers.empty() ? 0 : *LoadBarriers.begin();
   unsigned StoreBarrierIndex = StoreBarriers.empty() ? 0 : *StoreBarriers.begin();
 

diff --git a/llvm/tools/llvm-mca/LSUnit.h b/llvm/tools/llvm-mca/LSUnit.h
index a2583f8..8bf933d 100644 (file)
--- a/llvm/tools/llvm-mca/LSUnit.h
+++ b/llvm/tools/llvm-mca/LSUnit.h
@@ -24,6 +24,8 @@
 
 namespace mca {
 
+struct InstrDesc;
+
 /// \brief A Load/Store Unit implementing a load and store queues.
 ///
 /// This class implements a load queue and a store queue to emulate the
@@ -129,20 +131,8 @@ public:
   bool isSQFull() const { return SQ_Size != 0 && StoreQueue.size() == SQ_Size; }
   bool isLQFull() const { return LQ_Size != 0 && LoadQueue.size() == LQ_Size; }
 
-  void reserve(unsigned Index, bool MayLoad, bool MayStore, bool IsMemBarrier) {
-    if (!MayLoad && !MayStore)
-      return;
-    if (MayLoad) {
-      if (IsMemBarrier)
-        LoadBarriers.insert(Index);
-      assignLQSlot(Index);
-    }
-    if (MayStore) {
-      if (IsMemBarrier)
-        StoreBarriers.insert(Index);
-      assignSQSlot(Index);
-    }
-  }
+  // Returns true if this instruction has been successfully enqueued.
+  bool reserve(unsigned Index, const InstrDesc &Desc);
 
   // The rules are:
   // 1. A store may not pass a previous store.

diff --git a/llvm/tools/llvm-mca/Scheduler.cpp b/llvm/tools/llvm-mca/Scheduler.cpp
index 70b073b..08ddf6e 100644 (file)
--- a/llvm/tools/llvm-mca/Scheduler.cpp
+++ b/llvm/tools/llvm-mca/Scheduler.cpp
@@ -260,16 +260,9 @@ void Scheduler::scheduleInstruction(unsigned Idx, Instruction &MCIS) {
     notifyReservedBuffers(Desc.Buffers);
   }
 
-  bool MayLoad = Desc.MayLoad;
-  bool MayStore = Desc.MayStore;
-  if (MayLoad || MayStore)
-    LSU->reserve(Idx, MayLoad, MayStore, Desc.HasSideEffects);
-
-  bool IsReady = MCIS.isReady();
-  if (IsReady && (MayLoad || MayStore))
-    IsReady &= LSU->isReady(Idx);
-
-  if (!IsReady) {
+  // If necessary, reserve queue entries in the load-store unit (LSU).
+  bool Reserved = LSU->reserve(Idx, Desc);
+  if (!MCIS.isReady() || (Reserved && !LSU->isReady(Idx))) {
     DEBUG(dbgs() << "[SCHEDULER] Adding " << Idx << " to the Wait Queue\n");
     WaitQueue[Idx] = &MCIS;
     return;