clk: renesas: r9a06g032: Fix UART clkgrp bitsel

There are two UART clock groups, each having a mux to select its
upstream clock source. The register/bit definitions for accessing these
two muxes appear to have been reversed since introduction. Correct them
so as to match the hardware manual.

Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver")

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220518182527.1693156-1-ralph.siemsen@linaro.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index 88865bb..1488c9d 100644 (file)
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -288,8 +288,8 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
                .name = "uart_group_012",
                .type = K_BITSEL,
                .source = 1 + R9A06G032_DIV_UART,
-               /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
-               .dual.sel = ((0xec / 4) << 5) | 24,
+               /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
+               .dual.sel = ((0x34 / 4) << 5) | 30,
                .dual.group = 0,
        },
        {
@@ -297,8 +297,8 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
                .name = "uart_group_34567",
                .type = K_BITSEL,
                .source = 1 + R9A06G032_DIV_P2_PG,
-               /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
-               .dual.sel = ((0x34 / 4) << 5) | 30,
+               /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
+               .dual.sel = ((0xec / 4) << 5) | 24,
                .dual.group = 1,
        },
        D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),