if (FalseZero) {
// If we cannot prefix the requested instruction we'll instead emit a
// prefixed_zeroing_mov for DestructiveBinary.
- assert((DOPRegIsUnique || AArch64::DestructiveBinary == DType) &&
+ assert((DOPRegIsUnique || ((DType == AArch64::DestructiveBinary) ||
+ (DType = AArch64::DestructiveBinaryComm))) &&
"The destructive operand should be unique");
assert(ElementSize != AArch64::ElementSizeNone &&
"This instruction is unpredicated");
// Create the additional LSL to zero the lanes when the DstReg is not
// unique. Zeros the lanes in z0 that aren't active in p0 with sequence
// movprfx z0.b, p0/z, z0.b; lsl z0.b, p0/m, z0.b, #0;
- if (DType == AArch64::DestructiveBinary && !DOPRegIsUnique) {
+ if (((DType == AArch64::DestructiveBinary) ||
+ (DType == AArch64::DestructiveBinaryComm)) &&
+ !DOPRegIsUnique) {
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LSLZero))
.addReg(DstReg, RegState::Define)
.add(MI.getOperand(PredIdx))
--- /dev/null
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+use-experimental-zeroing-pseudos -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s
+
+# Should create an additional LSL to zero the lanes as the DstReg is not unique
+
+--- |
+ define <vscale x 4 x float> @fmul_float_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a){
+ %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+ %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a_z, <vscale x 4 x float> %a_z)
+ ret <vscale x 4 x float> %out
+ }
+
+ declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+...
+---
+name: fmul_float_zero
+alignment: 4
+tracksRegLiveness: true
+tracksDebugUserValues: true
+registers: []
+liveins:
+ - { reg: '$p0', virtual-reg: '' }
+ - { reg: '$z0', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $p0, $z0
+
+ ; CHECK-LABEL: name: fmul_float_zero
+ ; CHECK: liveins: $p0, $z0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $z0_hi, implicit $p0, implicit $z0 {
+ ; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_S $p0, $z0
+ ; CHECK-NEXT: $z0 = LSL_ZPmI_S renamable $p0, internal $z0, 0
+ ; CHECK-NEXT: $z0 = FMUL_ZPmZ_S renamable $p0, internal killed $z0, internal killed renamable $z0
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: RET undef $lr, implicit $z0
+ renamable $z0 = nnan ninf nsz arcp contract afn reassoc FMUL_ZPZZ_ZERO_S renamable $p0, killed renamable $z0, renamable $z0
+ RET_ReallyLR implicit $z0
+...