clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150
authorBhupesh Sharma <bhupesh.sharma@linaro.org>
Wed, 2 Mar 2022 20:30:41 +0000 (02:00 +0530)
committerBjorn Andersson <bjorn.andersson@linaro.org>
Wed, 9 Mar 2022 14:53:29 +0000 (08:53 -0600)
Add the PCIe0 and PCIe1 GDSC defines & driver structures for SM8150.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220302203045.184500-4-bhupesh.sharma@linaro.org
drivers/clk/qcom/gcc-sm8150.c
include/dt-bindings/clock/qcom,gcc-sm8150.h

index 2457944..7e478dc 100644 (file)
@@ -3448,6 +3448,24 @@ static struct clk_branch gcc_video_xo_clk = {
        },
 };
 
+static struct gdsc pcie_0_gdsc = {
+       .gdscr = 0x6b004,
+       .pd = {
+               .name = "pcie_0_gdsc",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+       .flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc pcie_1_gdsc = {
+       .gdscr = 0x8d004,
+       .pd = {
+               .name = "pcie_1_gdsc",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+       .flags = POLL_CFG_GDSCR,
+};
+
 static struct gdsc usb30_prim_gdsc = {
                .gdscr = 0xf004,
                .pd = {
@@ -3714,6 +3732,8 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = {
 };
 
 static struct gdsc *gcc_sm8150_gdscs[] = {
+       [PCIE_0_GDSC] = &pcie_0_gdsc,
+       [PCIE_1_GDSC] = &pcie_1_gdsc,
        [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
        [USB30_SEC_GDSC] = &usb30_sec_gdsc,
 };
index 3e1a918..ae9c164 100644 (file)
 #define GCC_USB_PHY_CFG_AHB2PHY_BCR                            28
 
 /* GCC GDSCRs */
+#define PCIE_0_GDSC                                            0
+#define PCIE_1_GDSC                                            1
 #define USB30_PRIM_GDSC                     4
 #define USB30_SEC_GDSC                                         5