arm64: dts: imx8mm-cl-iot-gate-u-boot.dtsi: alphabetically re-order

Alphabetically re-order nodes and properties.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi
index 1206593..67ce70d 100644 (file)
--- a/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi
@@ -8,18 +8,18 @@
                multiple-images;
        };
 
-       wdt-reboot {
-               compatible = "wdt-reboot";
-               wdt = <&wdog1>;
-               u-boot,dm-spl;
-       };
-
        firmware {
                optee {
                        compatible = "linaro,optee-tz";
                        method = "smc";
                };
        };
+
+       wdt-reboot {
+               compatible = "wdt-reboot";
+               u-boot,dm-spl;
+               wdt = <&wdog1>;
+       };
 };
 
 &{/soc@0} {
@@ -27,17 +27,12 @@
        u-boot,dm-spl;
 };
 
-&clk {
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
        u-boot,dm-spl;
-       u-boot,dm-pre-reloc;
-       /delete-property/ assigned-clocks;
-       /delete-property/ assigned-clock-parents;
-       /delete-property/ assigned-clock-rates;
 };
 
-&osc_24m {
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
        u-boot,dm-spl;
-       u-boot,dm-pre-reloc;
 };
 
 &aips1 {
@@ -53,94 +48,6 @@
        u-boot,dm-spl;
 };
 
-&iomuxc {
-       u-boot,dm-spl;
-};
-
-&pinctrl_uart3 {
-       u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2_gpio {
-       u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2 {
-       u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
-       u-boot,dm-spl;
-};
-
-&gpio1 {
-       u-boot,dm-spl;
-};
-
-&gpio2 {
-       u-boot,dm-spl;
-};
-
-&gpio3 {
-       u-boot,dm-spl;
-};
-
-&gpio4 {
-       u-boot,dm-spl;
-};
-
-&gpio5 {
-       u-boot,dm-spl;
-};
-
-&uart3 {
-       u-boot,dm-spl;
-};
-
-&usdhc1 {
-       u-boot,dm-spl;
-};
-
-&usdhc2 {
-       u-boot,dm-spl;
-};
-
-&usdhc3 {
-       u-boot,dm-spl;
-};
-
-&i2c1 {
-       u-boot,dm-spl;
-};
-
-&i2c2 {
-       u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
-       u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
-       u-boot,dm-spl;
-};
-
-&pinctrl_i2c2 {
-       u-boot,dm-spl;
-};
-
-&pinctrl_pmic {
-       u-boot,dm-spl;
-};
-
-&fec1 {
-       phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
-};
-
-&wdog1 {
-       u-boot,dm-spl;
-};
-
 &binman {
        u-boot-spl-ddr {
                filename = "u-boot-spl-ddr.bin";
@@ -253,3 +160,96 @@
                };
        };
 };
+
+&clk {
+       u-boot,dm-spl;
+       u-boot,dm-pre-reloc;
+       /delete-property/ assigned-clocks;
+       /delete-property/ assigned-clock-parents;
+       /delete-property/ assigned-clock-rates;
+};
+
+&fec1 {
+       phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+};
+
+&gpio1 {
+       u-boot,dm-spl;
+};
+
+&gpio2 {
+       u-boot,dm-spl;
+};
+
+&gpio3 {
+       u-boot,dm-spl;
+};
+
+&gpio4 {
+       u-boot,dm-spl;
+};
+
+&gpio5 {
+       u-boot,dm-spl;
+};
+
+&i2c1 {
+       u-boot,dm-spl;
+};
+
+&i2c2 {
+       u-boot,dm-spl;
+};
+
+&iomuxc {
+       u-boot,dm-spl;
+};
+
+&osc_24m {
+       u-boot,dm-spl;
+       u-boot,dm-pre-reloc;
+};
+
+&pinctrl_i2c2 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+       u-boot,dm-spl;
+};
+
+&pinctrl_uart3 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+       u-boot,dm-spl;
+};
+
+&uart3 {
+       u-boot,dm-spl;
+};
+
+&usdhc1 {
+       u-boot,dm-spl;
+};
+
+&usdhc2 {
+       u-boot,dm-spl;
+};
+
+&usdhc3 {
+       u-boot,dm-spl;
+};
+
+&wdog1 {
+       u-boot,dm-spl;
+};

diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
index 00927c1..fe45a35 100644 (file)
--- a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
@@ -8,18 +8,18 @@
                multiple-images;
        };
 
-       wdt-reboot {
-               compatible = "wdt-reboot";
-               wdt = <&wdog1>;
-               u-boot,dm-spl;
-       };
-
        firmware {
                optee {
                        compatible = "linaro,optee-tz";
                        method = "smc";
                };
        };
+
+       wdt-reboot {
+               compatible = "wdt-reboot";
+               u-boot,dm-spl;
+               wdt = <&wdog1>;
+       };
 };
 
 &{/soc@0} {
@@ -27,17 +27,12 @@
        u-boot,dm-spl;
 };
 
-&clk {
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
        u-boot,dm-spl;
-       u-boot,dm-pre-reloc;
-       /delete-property/ assigned-clocks;
-       /delete-property/ assigned-clock-parents;
-       /delete-property/ assigned-clock-rates;
 };
 
-&osc_24m {
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
        u-boot,dm-spl;
-       u-boot,dm-pre-reloc;
 };
 
 &aips1 {
@@ -53,94 +48,6 @@
        u-boot,dm-spl;
 };
 
-&iomuxc {
-       u-boot,dm-spl;
-};
-
-&pinctrl_uart3 {
-       u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2_gpio {
-       u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2 {
-       u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
-       u-boot,dm-spl;
-};
-
-&gpio1 {
-       u-boot,dm-spl;
-};
-
-&gpio2 {
-       u-boot,dm-spl;
-};
-
-&gpio3 {
-       u-boot,dm-spl;
-};
-
-&gpio4 {
-       u-boot,dm-spl;
-};
-
-&gpio5 {
-       u-boot,dm-spl;
-};
-
-&uart3 {
-       u-boot,dm-spl;
-};
-
-&usdhc1 {
-       u-boot,dm-spl;
-};
-
-&usdhc2 {
-       u-boot,dm-spl;
-};
-
-&usdhc3 {
-       u-boot,dm-spl;
-};
-
-&i2c1 {
-       u-boot,dm-spl;
-};
-
-&i2c2 {
-       u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
-       u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
-       u-boot,dm-spl;
-};
-
-&pinctrl_i2c2 {
-       u-boot,dm-spl;
-};
-
-&pinctrl_pmic {
-       u-boot,dm-spl;
-};
-
-&fec1 {
-       phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
-};
-
-&wdog1 {
-       u-boot,dm-spl;
-};
-
 &binman {
        u-boot-spl-ddr {
                filename = "u-boot-spl-ddr.bin";
@@ -241,3 +148,96 @@
                };
        };
 };
+
+&clk {
+       u-boot,dm-spl;
+       u-boot,dm-pre-reloc;
+       /delete-property/ assigned-clocks;
+       /delete-property/ assigned-clock-parents;
+       /delete-property/ assigned-clock-rates;
+};
+
+&fec1 {
+       phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+};
+
+&gpio1 {
+       u-boot,dm-spl;
+};
+
+&gpio2 {
+       u-boot,dm-spl;
+};
+
+&gpio3 {
+       u-boot,dm-spl;
+};
+
+&gpio4 {
+       u-boot,dm-spl;
+};
+
+&gpio5 {
+       u-boot,dm-spl;
+};
+
+&i2c1 {
+       u-boot,dm-spl;
+};
+
+&i2c2 {
+       u-boot,dm-spl;
+};
+
+&iomuxc {
+       u-boot,dm-spl;
+};
+
+&osc_24m {
+       u-boot,dm-spl;
+       u-boot,dm-pre-reloc;
+};
+
+&pinctrl_i2c2 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+       u-boot,dm-spl;
+};
+
+&pinctrl_uart3 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+       u-boot,dm-spl;
+};
+
+&uart3 {
+       u-boot,dm-spl;
+};
+
+&usdhc1 {
+       u-boot,dm-spl;
+};
+
+&usdhc2 {
+       u-boot,dm-spl;
+};
+
+&usdhc3 {
+       u-boot,dm-spl;
+};
+
+&wdog1 {
+       u-boot,dm-spl;
+};