amd: fix tile_swizzle on gfx11 - should be shifted by 10 bits, not 8

This reverts the radv_adjust_tile_swizzle change to unify the code.

Fixes: 529eb739fc4 - radeonsi/gfx11: add CB deltas

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
(cherry picked from commit 47f598a183e849dfee4a587b51074664ee778312)

diff --git a/.pick_status.json b/.pick_status.json
index 635eec3..2a0588f 100644 (file)
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -2920,7 +2920,7 @@
         "description": "amd: fix tile_swizzle on gfx11 - should be shifted by 10 bits, not 8",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "529eb739fc40a5fe2d0d4d4704d29a6f90c97516"
     },

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 966e0e6..0b03de9 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1878,6 +1878,12 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
 
          assert(xout.pipeBankXor <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
          surf->tile_swizzle = xout.pipeBankXor;
+
+         /* Gfx11 should shift it by 10 bits instead of 8, and drivers already shift it by 8 bits,
+          * so shift it by 2 bits here.
+          */
+         if (info->gfx_level >= GFX11)
+            surf->tile_swizzle <<= 2;
       }
 
       bool use_dcc = false;

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 48a8c4c..d7f6c91 100644 (file)
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -345,7 +345,7 @@ struct radeon_surf {
     * - CMASK if it's TC-compatible or if the gen is GFX9
     * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
     */
-   uint8_t tile_swizzle;
+   uint16_t tile_swizzle; /* it has 16 bits because gfx11 shifts it by 2 bits */
    uint8_t fmask_tile_swizzle;
 
    /* Use (1 << log2) to compute the alignment. */

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 658b795..eec7833 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -6563,8 +6563,6 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
       tile_swizzle = iview->nbc_view.tile_swizzle;
    }
 
-   tile_swizzle = radv_adjust_tile_swizzle(device->physical_device, tile_swizzle);
-
    cb->cb_color_base = va >> 8;
 
    if (device->physical_device->rad_info.gfx_level >= GFX9) {

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 27f8304..86215b8 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -789,8 +789,6 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im
    } else
       va += (uint64_t)base_level_info->offset_256B * 256;
 
-   swizzle = radv_adjust_tile_swizzle(device->physical_device, swizzle);
-
    state[0] = va >> 8;
    if (gfx_level >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D)
       state[0] |= swizzle;

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 8f6371c..f3728ab 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -3196,12 +3196,6 @@ radv_has_shader_buffer_float_minmax(const struct radv_physical_device *pdevice,
           (pdevice->rad_info.gfx_level == GFX11 && bitsize == 32);
 }
 
-static inline unsigned
-radv_adjust_tile_swizzle(const struct radv_physical_device *dev, unsigned pipe_bank_xor)
-{
-   return pipe_bank_xor << (dev->rad_info.gfx_level >= GFX11 ? 2 : 0);
-}
-
 /* radv_perfcounter.c */
 void radv_perfcounter_emit_shaders(struct radeon_cmdbuf *cs, unsigned shaders);
 void radv_perfcounter_emit_spm_reset(struct radeon_cmdbuf *cs);

diff --git a/src/amd/vulkan/radv_sdma_copy_image.c b/src/amd/vulkan/radv_sdma_copy_image.c
index 7c8c8ae..523ac08 100644 (file)
--- a/src/amd/vulkan/radv_sdma_copy_image.c
+++ b/src/amd/vulkan/radv_sdma_copy_image.c
@@ -141,9 +141,7 @@ radv_sdma_v4_v5_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct
                      1u << 31);
       radeon_emit(
          cmd_buffer->cs,
-         (uint32_t)tiled_address |
-            (radv_adjust_tile_swizzle(device->physical_device, image->planes[0].surface.tile_swizzle)
-             << 8));
+         (uint32_t)tiled_address | (image->planes[0].surface.tile_swizzle << 8));
       radeon_emit(cmd_buffer->cs, (uint32_t)(tiled_address >> 32));
       radeon_emit(cmd_buffer->cs, 0);
       radeon_emit(cmd_buffer->cs, ((tiled_width - 1) << 16));