nouveau_drm.h \
r128_drm.h \
radeon_drm.h \
+ radeon_ms_drm.h \
savage_drm.h \
sis_drm.h \
via_drm.h \
void radeon_ms_cp_stop(struct drm_device *dev);
int radeon_ms_cp_wait(struct drm_device *dev, int n);
int radeon_ms_ring_emit(struct drm_device *dev, uint32_t *cmd, uint32_t count);
+int radeon_ms_resetcp(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
/* radeon_ms_crtc.c */
int radeon_ms_crtc_create(struct drm_device *dev, int crtc);
dev_priv->ring_buffer_object->mem.num_pages,
&dev_priv->ring_buffer_map);
if (ret) {
- DRM_ERROR("[radeon_ms] error mapping ring buffer: %d\n", ret);
+ DRM_INFO("[radeon_ms] error mapping ring buffer: %d\n", ret);
return ret;
}
dev_priv->ring_buffer = dev_priv->ring_buffer_map.virtual;
void radeon_ms_cp_stop(struct drm_device *dev)
{
struct drm_radeon_private *dev_priv = dev->dev_private;
+ uint32_t rbbm_status, rbbm_status_cp_mask;
- MMIO_W(CP_CSQ_CNTL, REG_S(CP_CSQ_CNTL, CSQ_MODE,
- CSQ_MODE__CSQ_PRIDIS_INDDIS));
+ dev_priv->cp_ready = 0;
+ MMIO_W(CP_CSQ_CNTL, 0);
+ MMIO_R(CP_CSQ_CNTL);
+ MMIO_W(CP_CSQ_MODE, 0);
+ MMIO_R(CP_CSQ_MODE);
+ MMIO_W(RBBM_SOFT_RESET, RBBM_SOFT_RESET__SOFT_RESET_CP);
+ MMIO_R(RBBM_SOFT_RESET);
+ MMIO_W(RBBM_SOFT_RESET, 0);
+ MMIO_R(RBBM_SOFT_RESET);
+ rbbm_status = MMIO_R(RBBM_STATUS);
+ rbbm_status_cp_mask = (RBBM_STATUS__CPRQ_ON_RBB |
+ RBBM_STATUS__CPRQ_IN_RTBUF |
+ RBBM_STATUS__CP_CMDSTRM_BUSY);
+ if (rbbm_status & rbbm_status_cp_mask) {
+ DRM_INFO("[radeon_ms] cp busy (RBBM_STATUS: 0x%08X "
+ "RBBM_STATUS(cp_mask): 0x%08X)\n", rbbm_status,
+ rbbm_status_cp_mask);
+ }
MMIO_W(CP_RB_CNTL, CP_RB_CNTL__RB_RPTR_WR_ENA);
MMIO_W(CP_RB_RPTR_WR, 0);
MMIO_W(CP_RB_WPTR, 0);
DRM_UDELAY(5);
dev_priv->ring_wptr = dev_priv->ring_rptr = MMIO_R(CP_RB_RPTR);
- MMIO_W(CP_RB_WPTR, dev_priv->ring_wptr);
+ MMIO_W(CP_RB_CNTL, 0);
}
int radeon_ms_cp_wait(struct drm_device *dev, int n)
dev_priv->ring_free -= count;
for (i = 0; i < count; i++) {
dev_priv->ring_buffer[dev_priv->ring_wptr] = cmd[i];
+ DRM_INFO("ring[%d] = 0x%08X\n", dev_priv->ring_wptr, cmd[i]);
dev_priv->ring_wptr++;
dev_priv->ring_wptr &= dev_priv->ring_mask;
}
spin_unlock(&ring_lock);
return 0;
}
+
+int radeon_ms_resetcp(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ int i;
+
+ DRM_INFO("[radeon_ms]--------------------------------------------\n");
+
+ /* reset VAP */
+ DRM_INFO("[radeon_ms] status before VAP : RBBM_STATUS: 0x%08X\n",
+ MMIO_R(RBBM_STATUS));
+ MMIO_W(RBBM_SOFT_RESET, RBBM_SOFT_RESET__SOFT_RESET_VAP);
+ MMIO_R(RBBM_SOFT_RESET);
+ MMIO_W(RBBM_SOFT_RESET, 0);
+ MMIO_R(RBBM_SOFT_RESET);
+ for (i = 0; i < 100; i++) {
+ DRM_UDELAY(100);
+ }
+ DRM_INFO("[radeon_ms] status after VAP : RBBM_STATUS: 0x%08X\n",
+ MMIO_R(RBBM_STATUS));
+
+ DRM_INFO("[radeon_ms]--------------------------------------------\n");
+ return 0;
+}
struct drm_ioctl_desc radeon_ms_ioctls[] = {
DRM_IOCTL_DEF(DRM_RADEON_EXECBUFFER, radeon_ms_execbuffer, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_RADEON_RESETCP, radeon_ms_resetcp, DRM_AUTH),
};
int radeon_ms_num_ioctls = DRM_ARRAY_SIZE(radeon_ms_ioctls);
/* radeon ms ioctl */
#define DRM_RADEON_EXECBUFFER 0x00
+#define DRM_RADEON_RESETCP 0x01
struct drm_radeon_execbuffer_arg {
uint64_t next;
}
/* fence */
- ret = drm_fence_buffer_objects(dev, NULL, 0, NULL, &fence);
- if (ret) {
- drm_putback_buffer_objects(dev);
- DRM_ERROR("[radeon_ms] fence buffer objects failed\n");
- goto out_free_release;
- }
- if (!(fence_arg->flags & DRM_FENCE_FLAG_NO_USER)) {
- ret = drm_fence_add_user_object(file_priv, fence,
- fence_arg->flags & DRM_FENCE_FLAG_SHAREABLE);
- if (!ret) {
- fence_arg->handle = fence->base.hash.key;
- fence_arg->fence_class = fence->fence_class;
- fence_arg->type = fence->type;
- fence_arg->signaled = fence->signaled_types;
- fence_arg->sequence = fence->sequence;
+ if (execbuffer->args_count > 1) {
+ ret = drm_fence_buffer_objects(dev, NULL, 0, NULL, &fence);
+ if (ret) {
+ drm_putback_buffer_objects(dev);
+ DRM_ERROR("[radeon_ms] fence buffer objects failed\n");
+ goto out_free_release;
+ }
+ if (!(fence_arg->flags & DRM_FENCE_FLAG_NO_USER)) {
+ ret = drm_fence_add_user_object(file_priv, fence,
+ fence_arg->flags & DRM_FENCE_FLAG_SHAREABLE);
+ if (!ret) {
+ fence_arg->handle = fence->base.hash.key;
+ fence_arg->fence_class = fence->fence_class;
+ fence_arg->type = fence->type;
+ fence_arg->signaled = fence->signaled_types;
+ fence_arg->sequence = fence->sequence;
+ }
}
+ drm_fence_usage_deref_unlocked(&fence);
}
- drm_fence_usage_deref_unlocked(&fence);
out_free_release:
drm_bo_kunmap(&cmd_kmap);
radeon_ms_execbuffer_args_clean(dev, buffers, execbuffer->args_count);
MMIO_W(RBBM_SOFT_RESET, 0);
MMIO_R(RBBM_SOFT_RESET);
+#if 0
cache_mode = MMIO_R(RB2D_DSTCACHE_MODE);
MMIO_W(RB2D_DSTCACHE_MODE,
cache_mode | RB2D_DSTCACHE_MODE__DC_DISABLE_IGNORE_PE);
+#else
+ reset_mask = RBBM_SOFT_RESET__SOFT_RESET_CP |
+ RBBM_SOFT_RESET__SOFT_RESET_HI |
+ RBBM_SOFT_RESET__SOFT_RESET_E2;
+ MMIO_W(RBBM_SOFT_RESET, rbbm_soft_reset | reset_mask);
+ MMIO_R(RBBM_SOFT_RESET);
+ MMIO_W(RBBM_SOFT_RESET, 0);
+ cache_mode = MMIO_R(RB3D_DSTCACHE_CTLSTAT);
+ MMIO_W(RB3D_DSTCACHE_CTLSTAT, cache_mode | (0xf));
+#endif
MMIO_W(HOST_PATH_CNTL, host_path_cntl | HOST_PATH_CNTL__HDP_SOFT_RESET);
MMIO_R(HOST_PATH_CNTL);
DRM_UDELAY(1);
}
if (i >= dev_priv->usec_timeout) {
- DRM_ERROR("[radeon_ms] timeout waiting for crtc...\n");
+ DRM_INFO("[radeon_ms] timeout waiting for crtc...\n");
}
for (i = 0; i < dev_priv->usec_timeout; i++) {
if (!(CRTC2_OFFSET__CRTC2_GUI_TRIG_OFFSET &
DRM_UDELAY(1);
}
if (i >= dev_priv->usec_timeout) {
- DRM_ERROR("[radeon_ms] timeout waiting for crtc...\n");
+ DRM_INFO("[radeon_ms] timeout waiting for crtc...\n");
}
DRM_UDELAY(10000);
}
uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl;
uint32_t crtc2_gen_cntl, i;
- radeon_ms_wait_for_idle(dev);
/* Capture MC_STATUS in case things go wrong ... */
ov0_scale_cntl = dev_priv->ov0_scale_cntl = MMIO_R(OV0_SCALE_CNTL);
crtc_ext_cntl = dev_priv->crtc_ext_cntl = MMIO_R(CRTC_EXT_CNTL);
}
break;
default:
- DRM_ERROR("Unknown radeon family, aborting\n");
+ DRM_INFO("Unknown radeon family, aborting\n");
return;
}
- DRM_ERROR("[radeon_ms] failed to stop gpu...will proceed anyway\n");
+ DRM_INFO("[radeon_ms] failed to stop gpu...will proceed anyway\n");
DRM_UDELAY(20000);
}
return 0;
DRM_UDELAY(1);
}
- DRM_ERROR("[radeon_ms] failed to wait for fifo\n");
+ DRM_INFO("[radeon_ms] failed to wait for fifo\n");
return -EBUSY;
}
MMIO_W(RB3D_DSTCACHE_CTLSTAT_R3, purge3d);
break;
default:
- DRM_ERROR("Unknown radeon family, aborting\n");
+ DRM_INFO("Unknown radeon family, aborting\n");
return;
}
for (i = 0; i < dev_priv->usec_timeout; i++) {
}
DRM_UDELAY(1);
}
- DRM_ERROR("[radeon_ms] gpu flush timeout\n");
+ DRM_INFO("[radeon_ms] gpu flush timeout\n");
}
void radeon_ms_gpu_restore(struct drm_device *dev, struct radeon_state *state)
ret = radeon_ms_wait_for_fifo(dev, 2);
if (ret) {
ok = 0;
- DRM_ERROR("[radeon_ms] no fifo for setting up dst & src gui\n");
- DRM_ERROR("[radeon_ms] proceed anyway\n");
+ DRM_INFO("[radeon_ms] no fifo for setting up dst & src gui\n");
+ DRM_INFO("[radeon_ms] proceed anyway\n");
}
fbstart = (MC_FB_LOCATION__MC_FB_START__MASK &
MMIO_R(MC_FB_LOCATION)) << 16;
ret = radeon_ms_wait_for_fifo(dev, 1);
if (ret) {
ok = 0;
- DRM_ERROR("[radeon_ms] no fifo for setting up dp data type\n");
- DRM_ERROR("[radeon_ms] proceed anyway\n");
+ DRM_INFO("[radeon_ms] no fifo for setting up dp data type\n");
+ DRM_INFO("[radeon_ms] proceed anyway\n");
}
#ifdef __BIG_ENDIAN
MMIO_W(DP_DATATYPE, DP_DATATYPE__DP_BYTE_PIX_ORDER);
ret = radeon_ms_wait_for_fifo(dev, 1);
if (ret) {
ok = 0;
- DRM_ERROR("[radeon_ms] no fifo for setting up surface cntl\n");
- DRM_ERROR("[radeon_ms] proceed anyway\n");
+ DRM_INFO("[radeon_ms] no fifo for setting up surface cntl\n");
+ DRM_INFO("[radeon_ms] proceed anyway\n");
}
MMIO_W(SURFACE_CNTL, SURFACE_CNTL__SURF_TRANSLATION_DIS);
ret = radeon_ms_wait_for_fifo(dev, 2);
if (ret) {
ok = 0;
- DRM_ERROR("[radeon_ms] no fifo for setting scissor\n");
- DRM_ERROR("[radeon_ms] proceed anyway\n");
+ DRM_INFO("[radeon_ms] no fifo for setting scissor\n");
+ DRM_INFO("[radeon_ms] proceed anyway\n");
}
MMIO_W(DEFAULT_SC_BOTTOM_RIGHT, 0x1fff1fff);
MMIO_W(DEFAULT2_SC_BOTTOM_RIGHT, 0x1fff1fff);
ret = radeon_ms_wait_for_fifo(dev, 1);
if (ret) {
ok = 0;
- DRM_ERROR("[radeon_ms] no fifo for setting up gui cntl\n");
- DRM_ERROR("[radeon_ms] proceed anyway\n");
+ DRM_INFO("[radeon_ms] no fifo for setting up gui cntl\n");
+ DRM_INFO("[radeon_ms] proceed anyway\n");
}
MMIO_W(DP_GUI_MASTER_CNTL, 0);
ret = radeon_ms_wait_for_fifo(dev, 5);
if (ret) {
ok = 0;
- DRM_ERROR("[radeon_ms] no fifo for setting up clear color\n");
- DRM_ERROR("[radeon_ms] proceed anyway\n");
+ DRM_INFO("[radeon_ms] no fifo for setting up clear color\n");
+ DRM_INFO("[radeon_ms] proceed anyway\n");
}
MMIO_W(DP_BRUSH_BKGD_CLR, 0x00000000);
MMIO_W(DP_BRUSH_FRGD_CLR, 0xffffffff);
MMIO_W(DP_WRITE_MSK, 0xffffffff);
if (!ok) {
- DRM_ERROR("[radeon_ms] engine restore not enough fifo\n");
+ DRM_INFO("[radeon_ms] engine restore not enough fifo\n");
}
}
int radeon_ms_wait_for_idle(struct drm_device *dev)
{
struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct radeon_state *state = &dev_priv->driver_state;
int i, j, ret;
for (i = 0; i < 2; i++) {
ret = radeon_ms_wait_for_fifo(dev, 64);
if (ret) {
- DRM_ERROR("[radeon_ms] fifo not empty\n");
+ DRM_INFO("[radeon_ms] fifo not empty\n");
}
for (j = 0; j < dev_priv->usec_timeout; j++) {
if (!(RBBM_STATUS__GUI_ACTIVE & MMIO_R(RBBM_STATUS))) {
}
DRM_UDELAY(1);
}
- DRM_ERROR("[radeon_ms] idle timed out: status=0x%08x\n",
+ DRM_INFO("[radeon_ms] idle timed out: status=0x%08x\n",
MMIO_R(RBBM_STATUS));
- radeon_ms_gpu_stop(dev);
radeon_ms_gpu_reset(dev);
+ radeon_ms_gpu_resume(dev);
}
return -EBUSY;
}
#define SCRATCH_REG7 0x000015FC
#define SCRATCH_REG7__SCRATCH_REG7__MASK 0xFFFFFFFF
#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0
+#define SC_SCISSOR0 0x000043E0
+#define SC_SCISSOR0__XS0__MASK 0x00001FFF
+#define SC_SCISSOR0__XS0__SHIFT 0
+#define SC_SCISSOR0__YS0__MASK 0x03FFE000
+#define SC_SCISSOR0__YS0__SHIFT 13
+#define SC_SCISSOR1 0x000043E4
+#define SC_SCISSOR1__XS1__MASK 0x00001FFF
+#define SC_SCISSOR1__XS1__SHIFT 0
+#define SC_SCISSOR1__YS1__MASK 0x03FFE000
+#define SC_SCISSOR1__YS1__SHIFT 13
#define PCIE_INDEX 0x00000030
#define PCIE_INDEX__PCIE_INDEX__MASK 0x000007FF
#define PCIE_INDEX__PCIE_INDEX__SHIFT 0
#define PCIE_TX_GART_ERROR__GART_INVALID_WRITE 0x00000008
#define PCIE_TX_GART_ERROR__GART_INVALID_ADDR__MASK 0xFFFFFFF0
#define PCIE_TX_GART_ERROR__GART_INVALID_ADDR__SHIFT 4
+#define CP_CSQ_MODE 0x00000744
+#define CP_CSQ_MODE__INDIRECT2_START__MASK 0x0000007F
+#define CP_CSQ_MODE__INDIRECT2_START__SHIFT 0
+#define CP_CSQ_MODE__INDIRECT1_START__MASK 0x00007F00
+#define CP_CSQ_MODE__INDIRECT1_START__SHIFT 8
+#define CP_CSQ_MODE__CSQ_INDIRECT2_MODE 0x04000000
+#define CP_CSQ_MODE__CSQ_INDIRECT2_ENABLE 0x08000000
+#define CP_CSQ_MODE__CSQ_INDIRECT1_MODE 0x10000000
+#define CP_CSQ_MODE__CSQ_INDIRECT1_ENABLE 0x20000000
+#define CP_CSQ_MODE__CSQ_PRIMARY_MODE 0x40000000
+#define CP_CSQ_MODE__CSQ_PRIMARY_ENABLE 0x80000000
#define CP_RB_CNTL 0x00000704
#define CP_RB_CNTL__RB_BUFSZ__MASK 0x0000003F
#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0
#define ISYNC_CNTL__ISYNC_TRIG3D_IDLE2D 0x00000008
#define ISYNC_CNTL__ISYNC_WAIT_IDLEGUI 0x00000010
#define ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI 0x00000020
+#define GA_SOFT_RESET 0x0000429C
+#define GA_SOFT_RESET__SOFT_RESET_COUNT__MASK 0x0000FFFF
+#define GA_SOFT_RESET__SOFT_RESET_COUNT__SHIFT 0
+#define RBBM_CNTL 0x000000EC
+#define RBBM_CNTL__RB_SETTLE__MASK 0x0000000F
+#define RBBM_CNTL__RB_SETTLE__SHIFT 0
+#define RBBM_CNTL__ABORTCLKS_HI__MASK 0x00000070
+#define RBBM_CNTL__ABORTCLKS_HI__SHIFT 4
+#define RBBM_CNTL__ABORTCLKS_CP__MASK 0x00000700
+#define RBBM_CNTL__ABORTCLKS_CP__SHIFT 8
+#define RBBM_CNTL__ABORTCLKS_CFIFO__MASK 0x00007000
+#define RBBM_CNTL__ABORTCLKS_CFIFO__SHIFT 12
+#define RBBM_CNTL__CPQ_DATA_SWAP 0x00020000
+#define RBBM_CNTL__NO_ABORT_IDCT 0x00200000
+#define RBBM_CNTL__NO_ABORT_BIOS 0x00400000
+#define RBBM_CNTL__NO_ABORT_FB 0x00800000
+#define RBBM_CNTL__NO_ABORT_CP 0x01000000
+#define RBBM_CNTL__NO_ABORT_HI 0x02000000
+#define RBBM_CNTL__NO_ABORT_HDP 0x04000000
+#define RBBM_CNTL__NO_ABORT_MC 0x08000000
+#define RBBM_CNTL__NO_ABORT_AIC 0x10000000
+#define RBBM_CNTL__NO_ABORT_VIP 0x20000000
+#define RBBM_CNTL__NO_ABORT_DISP 0x40000000
+#define RBBM_CNTL__NO_ABORT_CG 0x80000000
+#define RBBM_CNTL__NO_ABORT_VAP 0x00080000
+#define RBBM_CNTL__NO_ABORT_GA 0x00100000
+#define RBBM_CNTL__NO_ABORT_TVOUT 0x00800000
#define RBBM_STATUS 0x00000E40
#define RBBM_STATUS__CMDFIFO_AVAIL__MASK 0x0000007F
#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT 0
#define RBBM_SOFT_RESET__SOFT_RESET_VAP 0x00000004
#define RBBM_SOFT_RESET__SOFT_RESET_GA 0x00002000
#define RBBM_SOFT_RESET__SOFT_RESET_IDCT 0x00004000
+#define RBBM_CMDFIFO_ADDR 0x00000E70
+#define RBBM_CMDFIFO_ADDR__CMDFIFO_ADDR__MASK 0x0000003F
+#define RBBM_CMDFIFO_ADDR__CMDFIFO_ADDR__SHIFT 0
+#define RBBM_CMDFIFO_ADDR__CMDFIFO_ADDR_R3__MASK 0x000001FF
+#define RBBM_CMDFIFO_ADDR__CMDFIFO_ADDR_R3__SHIFT 0
+#define RBBM_CMDFIFO_DATA 0x00000E74
+#define RBBM_CMDFIFO_DATA__CMDFIFO_DATA__MASK 0xFFFFFFFF
+#define RBBM_CMDFIFO_DATA__CMDFIFO_DATA__SHIFT 0
+#define RBBM_CMDFIFO_STAT 0x00000E7C
+#define RBBM_CMDFIFO_STAT__CMDFIFO_RPTR__MASK 0x0000003F
+#define RBBM_CMDFIFO_STAT__CMDFIFO_RPTR__SHIFT 0
+#define RBBM_CMDFIFO_STAT__CMDFIFO_WPTR__MASK 0x00003F00
+#define RBBM_CMDFIFO_STAT__CMDFIFO_WPTR__SHIFT 8
#define WAIT_UNTIL 0x00001720
#define WAIT_UNTIL__WAIT_CRTC_PFLIP 0x00000001
#define WAIT_UNTIL__WAIT_RE_CRTC_VLINE 0x00000002
#define DP_WRITE_MSK 0x000016CC
#define DP_WRITE_MSK__DP_WRITE_MSK__MASK 0xFFFFFFFF
#define DP_WRITE_MSK__DP_WRITE_MSK__SHIFT 0
+#define US_CONFIG 0x00004600
+#define US_CONFIG__NLEVEL__MASK 0x00000007
+#define US_CONFIG__NLEVEL__SHIFT 0
+#define US_CONFIG__FIRST_TEX 0x00000008
+#define US_CONFIG__PERF0__MASK 0x000001F0
+#define US_CONFIG__PERF0__SHIFT 4
+#define US_CONFIG__PERF1__MASK 0x00003E00
+#define US_CONFIG__PERF1__SHIFT 9
+#define US_CONFIG__PERF2__MASK 0x0007C000
+#define US_CONFIG__PERF2__SHIFT 14
+#define US_CONFIG__PERF3__MASK 0x00F80000
+#define US_CONFIG__PERF3__SHIFT 19
+#define US_RESET 0x0000460C
+#define VAP_PVS_STATE_FLUSH_REG 0x00002284
+#define VAP_PVS_STATE_FLUSH_REG__DATA_REGISTER__MASK 0xFFFFFFFF
+#define VAP_PVS_STATE_FLUSH_REG__DATA_REGISTER__SHIFT 0
#endif
projects / profile / ivi / libdrm.git / commitdiff