} \
} while (0)
+#define radeon_opt_set_uconfig_reg(sctx, offset, reg, val) do { \
+ unsigned __value = val; \
+ if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \
+ sctx->tracked_regs.reg_value[reg] != __value) { \
+ radeon_set_uconfig_reg(cs, offset, __value); \
+ sctx->tracked_regs.reg_saved |= 0x1ull << (reg); \
+ sctx->tracked_regs.reg_value[reg] = __value; \
+ } \
+} while (0)
+
#define radeon_set_privileged_config_reg(cs, reg, value) do { \
assert((reg) < CIK_UCONFIG_REG_OFFSET); \
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); \
}
}
-static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
-{
- enum si_tracked_reg reg = SI_TRACKED_GE_PC_ALLOC;
-
- if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
- sctx->tracked_regs.reg_value[reg] != value) {
- struct radeon_cmdbuf *cs = &sctx->gfx_cs;
-
- radeon_begin(cs);
- radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value);
- radeon_end();
-
- sctx->tracked_regs.reg_saved |= 0x1ull << reg;
- sctx->tracked_regs.reg_value[reg] = value;
- }
-}
-
bool gfx10_is_ngg_passthrough(struct si_shader *shader)
{
struct si_shader_selector *sel = shader->selector;
SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
radeon_end_update_context_roll(sctx);
- /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
- gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.ngg.ge_pc_alloc);
-
+ /* These don't cause a context roll. */
radeon_begin_again(&sctx->gfx_cs);
+ radeon_opt_set_uconfig_reg(sctx, R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
+ shader->ctx_reg.ngg.ge_pc_alloc);
radeon_opt_set_sh_reg(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
shader->ctx_reg.ngg.spi_shader_pgm_rsrc3_gs);
radeon_end_update_context_roll(sctx);
/* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
- if (sctx->chip_class >= GFX10)
- gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.vs.ge_pc_alloc);
+ if (sctx->chip_class >= GFX10) {
+ radeon_begin_again(&sctx->gfx_cs);
+ radeon_opt_set_uconfig_reg(sctx, R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
+ shader->ctx_reg.vs.ge_pc_alloc);
+ radeon_end();
+ }
}
/**