/* Give the channel a chance to idle, wait 2s (hopefully) */
t_start = engine->timer.read(dev);
- while (NV_READ(chan->get) != NV_READ(chan->put)) {
+ while (NV_READ(chan->get) != NV_READ(chan->put) ||
+ NV_READ(NV03_PFIFO_CACHE1_GET) !=
+ NV_READ(NV03_PFIFO_CACHE1_PUT)) {
if (engine->timer.read(dev) - t_start > 2000000000ULL) {
DRM_ERROR("Failed to idle channel %d before destroy."
"Prepare for strangeness..\n", chan->id);
}
}
+ /*XXX: Maybe should wait for PGRAPH to finish with the stuff it fetched
+ * from CACHE1 too?
+ */
+
/* disable the fifo caches */
NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1));
#define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f
#define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f
#define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f
+#define NV03_PFIFO_CACHE1_PUT 0x00003210
#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220
#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224
# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000