MIPS: Alchemy: fix dbdma2

Various fixes for the Au1200/Au1550/Au1300 DBDMA2 code:

- skip cache invalidation if chip has working coherency circuitry.
- invalidate KSEG0-portion of the (physical) data address.
- force the dma channel doorbell write out to bus immediately with
  a sync.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 5ab0430..6a3c890 100644 (file)
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -30,6 +30,7 @@
  *
  */
 
+#include <linux/dma-map-ops.h> /* for dma_default_coherent */
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/slab.h>
@@ -623,17 +624,18 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
                dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
 
        /*
-        * There is an errata on the Au1200/Au1550 parts that could result
-        * in "stale" data being DMA'ed. It has to do with the snoop logic on
-        * the cache eviction buffer.  DMA_NONCOHERENT is on by default for
-        * these parts. If it is fixed in the future, these dma_cache_inv will
-        * just be nothing more than empty macros. See io.h.
+        * There is an erratum on certain Au1200/Au1550 revisions that could
+        * result in "stale" data being DMA'ed. It has to do with the snoop
+        * logic on the cache eviction buffer.  dma_default_coherent is set
+        * to false on these parts.
         */
-       dma_cache_wback_inv((unsigned long)buf, nbytes);
+       if (!dma_default_coherent)
+               dma_cache_wback_inv(KSEG0ADDR(buf), nbytes);
        dp->dscr_cmd0 |= DSCR_CMD0_V;   /* Let it rip */
        wmb(); /* drain writebuffer */
        dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
        ctp->chan_ptr->ddma_dbell = 0;
+       wmb(); /* force doorbell write out to dma engine */
 
        /* Get next descriptor pointer. */
        ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
@@ -685,17 +687,18 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
                          dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
 #endif
        /*
-        * There is an errata on the Au1200/Au1550 parts that could result in
-        * "stale" data being DMA'ed. It has to do with the snoop logic on the
-        * cache eviction buffer.  DMA_NONCOHERENT is on by default for these
-        * parts. If it is fixed in the future, these dma_cache_inv will just
-        * be nothing more than empty macros. See io.h.
+        * There is an erratum on certain Au1200/Au1550 revisions that could
+        * result in "stale" data being DMA'ed. It has to do with the snoop
+        * logic on the cache eviction buffer.  dma_default_coherent is set
+        * to false on these parts.
         */
-       dma_cache_inv((unsigned long)buf, nbytes);
+       if (!dma_default_coherent)
+               dma_cache_inv(KSEG0ADDR(buf), nbytes);
        dp->dscr_cmd0 |= DSCR_CMD0_V;   /* Let it rip */
        wmb(); /* drain writebuffer */
        dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
        ctp->chan_ptr->ddma_dbell = 0;
+       wmb(); /* force doorbell write out to dma engine */
 
        /* Get next descriptor pointer. */
        ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));