ARM: dts: keystone: Do not capitalize hex digits
authorAndrew Davis <afd@ti.com>
Mon, 15 May 2023 18:35:15 +0000 (13:35 -0500)
committerNishanth Menon <nm@ti.com>
Wed, 7 Jun 2023 14:02:46 +0000 (09:02 -0500)
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515183515.509371-5-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
arch/arm/boot/dts/keystone-k2e-evm.dts
arch/arm/boot/dts/keystone-k2e-netcp.dtsi
arch/arm/boot/dts/keystone-k2g-evm.dts
arch/arm/boot/dts/keystone-k2g-ice.dts
arch/arm/boot/dts/keystone-k2g.dtsi
arch/arm/boot/dts/keystone-k2l-evm.dts
arch/arm/boot/dts/keystone-k2l.dtsi
arch/arm/boot/dts/keystone.dtsi

index 04e0759..6978d6a 100644 (file)
 
                        partition@180000 {
                                label = "ubifs";
-                               reg = <0x180000 0x1FE80000>;
+                               reg = <0x180000 0x1fe80000>;
                        };
                };
        };
index 42cf74d..bff73a0 100644 (file)
@@ -167,7 +167,7 @@ netcp: netcp@24000000 {
                                                 <&tsipclka>, <&tsrefclk>,
                                                 <&tsipclkb>;
                                        ti,mux-tbl = <0x0>, <0x1>, <0x2>,
-                                               <0x3>, <0x4>, <0x8>, <0xC>;
+                                               <0x3>, <0x4>, <0x8>, <0xc>;
                                        assigned-clocks = <&cpts_refclk_mux>;
                                        assigned-clock-parents = <&chipclk12>;
                                };
index 7527dac..7bfc80f 100644 (file)
 
        emac_pins: emac-pins {
                pinctrl-single,pins = <
-                       K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD1.RGMII_RXD1 */
+                       K2G_CORE_IOPAD(0x113c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD1.RGMII_RXD1 */
                        K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD2.RGMII_RXD2 */
                        K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD3.RGMII_RXD3 */
                        K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD0.RGMII_RXD0 */
                        K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD0.RGMII_TXD0 */
                        K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD1.RGMII_TXD1 */
                        K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD2.RGMII_TXD2 */
-                       K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD3.RGMII_TXD3 */
+                       K2G_CORE_IOPAD(0x116c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD3.RGMII_TXD3 */
                        K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXCLK.RGMII_TXC */
-                       K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXEN.RGMII_TXCTL */
+                       K2G_CORE_IOPAD(0x117c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXEN.RGMII_TXCTL */
                        K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXCLK.RGMII_RXC */
                        K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXDV.RGMII_RXCTL */
                >;
 
        mdio_pins: mdio-pins {
                pinctrl-single,pins = <
-                       K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* MDIO_CLK.MDIO_CLK */
+                       K2G_CORE_IOPAD(0x118c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* MDIO_CLK.MDIO_CLK */
                        K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* MDIO_DATA.MDIO_DATA */
                >;
        };
                };
                partition@4 {
                        label = "QSPI.kernel";
-                       reg = <0x001C0000 0x0800000>;
+                       reg = <0x001c0000 0x0800000>;
                };
                partition@5 {
                        label = "QSPI.file-system";
-                       reg = <0x009C0000 0x3640000>;
+                       reg = <0x009c0000 0x3640000>;
                };
        };
 };
index 97be869..6ceb0d5 100644 (file)
 
        mmc1_pins: mmc1-pins {
                pinctrl-single,pins = <
-                       K2G_CORE_IOPAD(0x10FC) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat3.mmc1_dat3 */
+                       K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat3.mmc1_dat3 */
                        K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat2.mmc1_dat2 */
                        K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat1.mmc1_dat1 */
                        K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat0.mmc1_dat0 */
-                       K2G_CORE_IOPAD(0x110C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_clk.mmc1_clk */
+                       K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_clk.mmc1_clk */
                        K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_cmd.mmc1_cmd */
                        K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)        /* mmc1_sdcd.gpio0_69 */
                        K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_sdwp.mmc1_sdwp */
-                       K2G_CORE_IOPAD(0x111C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_pow.mmc1_pow */
+                       K2G_CORE_IOPAD(0x111c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_pow.mmc1_pow */
                >;
        };
 
 
        emac_pins: emac-pins {
                pinctrl-single,pins = <
-                       K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD1.RGMII_RXD1 */
+                       K2G_CORE_IOPAD(0x113c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD1.RGMII_RXD1 */
                        K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD2.RGMII_RXD2 */
                        K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD3.RGMII_RXD3 */
                        K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD0.RGMII_RXD0 */
                        K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD0.RGMII_TXD0 */
                        K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD1.RGMII_TXD1 */
                        K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD2.RGMII_TXD2 */
-                       K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD3.RGMII_TXD3 */
+                       K2G_CORE_IOPAD(0x116c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD3.RGMII_TXD3 */
                        K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXCLK.RGMII_TXC */
-                       K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXEN.RGMII_TXCTL */
+                       K2G_CORE_IOPAD(0x117c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXEN.RGMII_TXCTL */
                        K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXCLK.RGMII_RXC */
                        K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXDV.RGMII_RXCTL */
                >;
 
        mdio_pins: mdio-pins {
                pinctrl-single,pins = <
-                       K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* MDIO_CLK.MDIO_CLK */
+                       K2G_CORE_IOPAD(0x118c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* MDIO_CLK.MDIO_CLK */
                        K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* MDIO_DATA.MDIO_DATA */
                >;
        };
index 380dd9d..102d596 100644 (file)
 
                dcan0: can@260b200 {
                        compatible = "ti,am4372-d_can", "ti,am3352-d_can";
-                       reg = <0x0260B200 0x200>;
+                       reg = <0x0260b200 0x200>;
                        interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
                        status = "disabled";
                        power-domains = <&k2g_pds 0x0008>;
 
                dcan1: can@260b400 {
                        compatible = "ti,am4372-d_can", "ti,am3352-d_can";
-                       reg = <0x0260B400 0x200>;
+                       reg = <0x0260b400 0x200>;
                        interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
                        status = "disabled";
                        power-domains = <&k2g_pds 0x0009>;
 
                spi2: spi@21805c00 {
                        compatible = "ti,keystone-spi";
-                       reg = <0x21805C00 0x200>;
+                       reg = <0x21805c00 0x200>;
                        num-cs = <4>;
                        ti,davinci-spi-intr-line = <0>;
                        interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
index 8e15a26..be619e3 100644 (file)
 
                        partition@180000 {
                                label = "ubifs";
-                               reg = <0x180000 0x7FE80000>;
+                               reg = <0x180000 0x7fe80000>;
                        };
                };
        };
index 87318ca..8949578 100644 (file)
                                 * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20
                                 * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19
                                 */
-                                       0x4 0x0000 0xFFFE0000
+                                       0x4 0x0000 0xfffe0000
                                >;
                        };
 
                                 * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3
                                 * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2
                                 */
-                                       0x4 0x0 0xFFF0
+                                       0x4 0x0 0xfff0
                                >;
                        };
 
                                 * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2
                                 * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1
                                 */
-                                       0x4 0x0 0xF
+                                       0x4 0x0 0xf
                                >;
                        };
 
                                 * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49
                                 * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48
                                 */
-                                       0x8 0x0 0xFFFF0000
+                                       0x8 0x0 0xffff0000
                                >;
                        };
 
                                 * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33
                                 * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32
                                 */
-                                       0x8 0x0 0xFFFF
+                                       0x8 0x0 0xffff
                                >;
                        };
                };
index 552ecd5..1fd04bb 100644 (file)
                        ti,davinci-gpio-unbanked = <32>;
                };
 
-               aemif: aemif@21000A00 {
+               aemif: aemif@21000a00 {
                        compatible = "ti,keystone-aemif", "ti,davinci-aemif";
                        #address-cells = <2>;
                        #size-cells = <1>;
                        clock-names = "aemif";
                        clock-ranges;
 
-                       reg = <0x21000A00 0x00000100>;
+                       reg = <0x21000a00 0x00000100>;
                        ranges = <0 0 0x30000000 0x10000000
-                                 1 0 0x21000A00 0x00000100>;
+                                 1 0 0x21000a00 0x00000100>;
                };
 
                pcie0: pcie@21800000 {