GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
};
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 1,
+ .reg_ofs = 0x34,
+};
+
static const struct of_device_id of_match_clk_mt2701_eth[] = {
{ .compatible = "mediatek,mt2701-ethsys", },
{}
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc);
return r;
}
GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
};
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 1,
+ .reg_ofs = 0xc,
+};
+
static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, 1, 0xc, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc);
return r;
}
GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
};
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 1,
+ .reg_ofs = 0x34,
+};
+
static const struct of_device_id of_match_clk_mt2701_hif[] = {
{ .compatible = "mediatek,mt2701-hifsys", },
{}
return r;
}
- mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc);
return 0;
}
FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
};
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+ /* infrasys */
+ {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 2,
+ .reg_ofs = 0x30,
+ },
+ /* pericfg */
+ {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 2,
+ .reg_ofs = 0x0,
+ },
+};
+
static struct clk_hw_onecell_data *infra_clk_data;
static void __init mtk_infrasys_init_early(struct device_node *node)
if (r)
return r;
- mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc[0]);
return 0;
}
if (r)
return r;
- mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc[1]);
return 0;
}
0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
};
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+ /* infra */
+ {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 2,
+ .reg_ofs = 0x30,
+ },
+ /* peri */
+ {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 2,
+ .reg_ofs = 0x0,
+ },
+};
+
static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
- mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc[0]);
return r;
}
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
- mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc[1]);
return r;
}
"ssusb_cdr_fb", 5),
};
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 1,
+ .reg_ofs = 0x34,
+};
+
static int clk_mt7622_ethsys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc);
return r;
}
GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
};
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 1,
+ .reg_ofs = 0x34,
+};
+
static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc);
return r;
}
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc);
return r;
}
MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
};
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+ /* infrasys */
+ {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 1,
+ .reg_ofs = 0x30,
+ },
+ /* pericfg */
+ {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 2,
+ .reg_ofs = 0x0,
+ },
+};
+
static int mtk_topckgen_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
if (r)
return r;
- mtk_register_reset_controller(node, 1, 0x30, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc[0]);
return 0;
}
clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
- mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc[1]);
return 0;
}
}
};
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 1,
+ .reg_ofs = 0x34,
+};
+
static int clk_mt7629_ethsys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc);
return r;
}
GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
};
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 1,
+ .reg_ofs = 0x34,
+};
+
static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc);
return r;
}
"could not register clock provider: %s: %d\n",
pdev->name, r);
- mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc);
return r;
}
MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
};
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+ /* infrasys */
+ {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 2,
+ .reg_ofs = 0x30,
+ },
+ /* pericfg */
+ {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 2,
+ .reg_ofs = 0x0,
+ }
+};
+
static void __init mtk_topckgen_init(struct device_node *node)
{
struct clk_hw_onecell_data *clk_data;
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
- mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc[0]);
}
CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
- mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc[1]);
}
CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
};
+static const struct mtk_clk_rst_desc clk_rst_desc[] = {
+ /* infrasys */
+ {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 2,
+ .reg_ofs = 0x30,
+ },
+ /* pericfg */
+ {
+ .version = MTK_RST_SIMPLE,
+ .rst_bank_nr = 2,
+ .reg_ofs = 0x0,
+ }
+};
+
static struct clk_hw_onecell_data *mt8173_top_clk_data __initdata;
static struct clk_hw_onecell_data *mt8173_pll_clk_data __initdata;
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
- mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc[0]);
}
CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
- mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);
+ mtk_register_reset_controller(node, &clk_rst_desc[1]);
}
CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
};
+static const struct mtk_clk_rst_desc clk_rst_desc = {
+ .version = MTK_RST_SET_CLR,
+ .rst_bank_nr = 4,
+ .reg_ofs = INFRA_RST0_SET_OFFSET,
+};
+
static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
return r;
}
- mtk_register_reset_controller(node, 4,
- INFRA_RST0_SET_OFFSET, MTK_RST_SET_CLR);
+ mtk_register_reset_controller(node, &clk_rst_desc);
return r;
}
#include "reset.h"
+static inline struct mtk_clk_rst_data *to_mtk_clk_rst_data(struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct mtk_clk_rst_data, rcdev);
+}
+
static int mtk_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool deassert)
{
- struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+ struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
unsigned int val = deassert ? 0 : ~0;
return regmap_update_bits(data->regmap,
- data->regofs + ((id / 32) << 2),
+ data->desc->reg_ofs + ((id / 32) << 2),
BIT(id % 32), val);
}
static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
unsigned long id, bool deassert)
{
- struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
+ struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
unsigned int deassert_ofs = deassert ? 0x4 : 0;
return regmap_write(data->regmap,
- data->regofs + ((id / 32) << 4) + deassert_ofs,
+ data->desc->reg_ofs + ((id / 32) << 4) + deassert_ofs,
BIT(id % 32));
}
};
void mtk_register_reset_controller(struct device_node *np,
- u32 rst_bank_nr, u16 reg_ofs,
- enum mtk_reset_version version)
+ const struct mtk_clk_rst_desc *desc)
{
- struct mtk_reset *data;
- int ret;
struct regmap *regmap;
const struct reset_control_ops *rcops = NULL;
+ struct mtk_clk_rst_data *data;
+ int ret;
+
+ if (!desc) {
+ pr_err("mtk clock reset desc is NULL\n");
+ return;
+ }
- switch (version) {
+ switch (desc->version) {
case MTK_RST_SIMPLE:
rcops = &mtk_reset_ops;
break;
rcops = &mtk_reset_ops_set_clr;
break;
default:
- pr_err("Unknown reset version %d\n", version);
+ pr_err("Unknown reset version %d\n", desc->version);
return;
}
if (!data)
return;
+ data->desc = desc;
data->regmap = regmap;
- data->regofs = reg_ofs;
data->rcdev.owner = THIS_MODULE;
- data->rcdev.nr_resets = rst_bank_nr * 32;
+ data->rcdev.nr_resets = desc->rst_bank_nr * 32;
data->rcdev.ops = rcops;
data->rcdev.of_node = np;
MTK_RST_MAX,
};
-struct mtk_reset {
+/**
+ * struct mtk_clk_rst_desc - Description of MediaTek clock reset.
+ * @version: Reset version which is defined in enum mtk_reset_version.
+ * @reg_ofs: Base offset of the reset register.
+ * @rst_bank_nr: Quantity of reset bank.
+ */
+struct mtk_clk_rst_desc {
+ enum mtk_reset_version version;
+ u16 reg_ofs;
+ u32 rst_bank_nr;
+};
+
+/**
+ * struct mtk_clk_rst_data - Data of MediaTek clock reset controller.
+ * @regmap: Pointer to base address of reset register address.
+ * @rcdev: Reset controller device.
+ * @desc: Pointer to description of the reset controller.
+ */
+struct mtk_clk_rst_data {
struct regmap *regmap;
- int regofs;
struct reset_controller_dev rcdev;
+ const struct mtk_clk_rst_desc *desc;
};
/**
* mtk_register_reset_controller - Register MediaTek clock reset controller
* @np: Pointer to device node.
- * @rst_bank_nr: Quantity of reset bank.
- * @reg_ofs: Base offset of the reset register.
- * @version: Version of MediaTek clock reset controller.
+ * @desc: Constant pointer to description of clock reset.
*/
void mtk_register_reset_controller(struct device_node *np,
- u32 rst_bank_nr, u16 reg_ofs,
- enum mtk_reset_version version);
+ const struct mtk_clk_rst_desc *desc);
#endif /* __DRV_CLK_MTK_RESET_H */