drm/amd/pm: enable vclk and dclk Pstates for SMU v13.0.4

Add the ability to control the vclk and dclk frequency by
power_dpm_force_performance_level interface.

Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 999b07db862e510fb32c3e5d3556a26753eeca68..315a6d8bde2e30d41601000bdd559defd8a8b483 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -915,6 +915,8 @@ static int smu_v13_0_4_set_performance_level(struct smu_context *smu,
        uint32_t sclk_min = 0, sclk_max = 0;
        uint32_t fclk_min = 0, fclk_max = 0;
        uint32_t socclk_min = 0, socclk_max = 0;
+       uint32_t vclk_min = 0, vclk_max = 0;
+       uint32_t dclk_min = 0, dclk_max = 0;
        int ret = 0;
 
        switch (level) {
@@ -922,22 +924,32 @@ static int smu_v13_0_4_set_performance_level(struct smu_context *smu,
                smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
                smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
                smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
+               smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
+               smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
                sclk_min = sclk_max;
                fclk_min = fclk_max;
                socclk_min = socclk_max;
+               vclk_min = vclk_max;
+               dclk_min = dclk_max;
                break;
        case AMD_DPM_FORCED_LEVEL_LOW:
                smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
                smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
                smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
+               smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
+               smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
                sclk_max = sclk_min;
                fclk_max = fclk_min;
                socclk_max = socclk_min;
+               vclk_max = vclk_min;
+               dclk_max = dclk_min;
                break;
        case AMD_DPM_FORCED_LEVEL_AUTO:
                smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
                smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
                smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
+               smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
+               smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
                break;
        case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
        case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
@@ -983,6 +995,23 @@ static int smu_v13_0_4_set_performance_level(struct smu_context *smu,
                        return ret;
        }
 
+       if (vclk_min && vclk_max) {
+               ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
+                                                             SMU_VCLK,
+                                                             vclk_min,
+                                                             vclk_max);
+               if (ret)
+                       return ret;
+       }
+
+       if (dclk_min && dclk_max) {
+               ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
+                                                             SMU_DCLK,
+                                                             dclk_min,
+                                                             dclk_max);
+               if (ret)
+                       return ret;
+       }
        return ret;
 }