[DAG] optimize away an arithmetic-right-shift of a 0 or -1 value

This came up as part of:
https://reviews.llvm.org/D25485

Note that the vector case is missed because ComputeNumSignBits() is deficient for vectors.

llvm-svn: 284395

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 44a49e848aa9c2df9e7972412bc4088ca3ae63ac..f460d529d051c8c1df1b59114fdfbe30897ddbc3 100644 (file)
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4740,6 +4740,10 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
   EVT VT = N0.getValueType();
   unsigned OpSizeInBits = VT.getScalarSizeInBits();
 
+  // Arithmetic shifting an all-sign-bit value is a no-op.
+  if (DAG.ComputeNumSignBits(N0) == OpSizeInBits)
+    return N0;
+
   // fold vector ops
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
   if (VT.isVector()) {

diff --git a/llvm/test/CodeGen/X86/sar_fold64.ll b/llvm/test/CodeGen/X86/sar_fold64.ll
index b8bd04dbb22af1fcfe767413210f69a70044b6a9..80c632b1f6af41b4939f58545a995327446fa3d5 100644 (file)
--- a/llvm/test/CodeGen/X86/sar_fold64.ll
+++ b/llvm/test/CodeGen/X86/sar_fold64.ll
@@ -57,14 +57,11 @@ define i32 @shl56sar57(i64 %a) #0 {
   ret i32 %3
 }
 
-; FIXME
-
 define i8 @all_sign_bit_ashr(i8 %x) {
 ; CHECK-LABEL: all_sign_bit_ashr:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    andb $1, %dil
 ; CHECK-NEXT:    negb %dil
-; CHECK-NEXT:    sarb $6, %dil
 ; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
 ;