void dcn31_timing_generator_init(struct optc *optc1);
+bool optc31_immediate_disable_crtc(struct timing_generator *optc);
+
void optc31_set_drr(struct timing_generator *optc, const struct drr_params *params);
void optc3_init_odm(struct timing_generator *optc);
.program_global_sync = optc1_program_global_sync,
.enable_crtc = optc314_enable_crtc,
.disable_crtc = optc314_disable_crtc,
+ .immediate_disable_crtc = optc31_immediate_disable_crtc,
.phantom_crtc_post_enable = optc314_phantom_crtc_post_enable,
/* used by enable_timing_synchronization. Not need for FPGA */
.is_counter_moving = optc1_is_counter_moving,
.clear_optc_underflow = optc1_clear_optc_underflow,
.setup_global_swap_lock = NULL,
.get_crc = optc1_get_crc,
- .configure_crc = optc1_configure_crc,
+ .configure_crc = optc2_configure_crc,
.set_dsc_config = optc3_set_dsc_config,
.get_dsc_status = optc2_get_dsc_status,
.set_dwb_source = NULL,