{
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
int i;
+ u32 clk;
u32 fsync;
+ if (!cs42l42->sclk)
+ clk = cs42l42->bclk;
+ else
+ clk = cs42l42->sclk;
+
for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
- if (pll_ratio_table[i].sclk == cs42l42->sclk) {
+ if (pll_ratio_table[i].sclk == clk) {
/* Configure the internal sample rate */
snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
CS42L42_INTERNAL_FS_MASK,
(pll_ratio_table[i].mclk_div <<
CS42L42_MCLKDIV_SHIFT));
/* Set up the LRCLK */
- fsync = cs42l42->sclk / cs42l42->srate;
- if (((fsync * cs42l42->srate) != cs42l42->sclk)
+ fsync = clk / cs42l42->srate;
+ if (((fsync * cs42l42->srate) != clk)
|| ((fsync % 2) != 0)) {
dev_err(component->dev,
"Unsupported sclk %d/sample rate %d\n",
- cs42l42->sclk,
+ clk,
cs42l42->srate);
return -EINVAL;
}
unsigned int val = 0;
cs42l42->srate = params_rate(params);
+ cs42l42->bclk = snd_soc_params_to_bclk(params);
switch(substream->stream) {
case SNDRV_PCM_STREAM_CAPTURE:
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = CS42L42_FORMATS,
},
+ .symmetric_rate = 1,
+ .symmetric_sample_bits = 1,
.ops = &cs42l42_ops,
};