* config/ia64/ia64.md (cmpxchg_acq_si): Mark operand 3 as DImode.

	* config/ia64/ia64.c (ia64_expand_fetch_and_op,
	ia64_expand_op_and_fetch): Make sure the REG for ar.ccv is
	DImode.   Use convert_move to load ar.ccv.
	(ia64_expand_compare_and_swap): Likewise.
	If expand_expr doesn't put 'old' and 'new' in the proper
	modes, run them through convert_to_mode.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@72770 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e260e04..36c3936 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2003-10-21  Zack Weinberg  <zack@codesourcery.com>
+
+       * config/ia64/ia64.md (cmpxchg_acq_si): Mark operand 3 as DImode.
+       * config/ia64/ia64.c (ia64_expand_fetch_and_op,
+       ia64_expand_op_and_fetch): Make sure the REG for ar.ccv is
+       DImode.   Use convert_move to load ar.ccv.
+       (ia64_expand_compare_and_swap): Likewise.
+       If expand_expr doesn't put 'old' and 'new' in the proper
+       modes, run them through convert_to_mode.
+
 2003-10-21  Eric Christopher  <echristo@redhat.com>
 
        * config/frv/frv.c (frv_adjust_field_align): Check DECL_ARTIFICIAL

diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 1c94533..72b8e86 100644 (file)
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -7885,13 +7885,14 @@ ia64_expand_fetch_and_op (optab binoptab, enum machine_mode mode,
     }
 
   tmp = gen_reg_rtx (mode);
-  ccv = gen_rtx_REG (mode, AR_CCV_REGNUM);
+  /* ar.ccv must always be loaded with a zero-extended DImode value.  */
+  ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
   emit_move_insn (tmp, mem);
 
   label = gen_label_rtx ();
   emit_label (label);
   emit_move_insn (ret, tmp);
-  emit_move_insn (ccv, tmp);
+  convert_move (ccv, tmp, /*unsignedp=*/1);
 
   /* Perform the specific operation.  Special case NAND by noticing
      one_cmpl_optab instead.  */
@@ -7951,14 +7952,15 @@ ia64_expand_op_and_fetch (optab binoptab, enum machine_mode mode,
   emit_insn (gen_mf ());
   tmp = gen_reg_rtx (mode);
   old = gen_reg_rtx (mode);
-  ccv = gen_rtx_REG (mode, AR_CCV_REGNUM);
+  /* ar.ccv must always be loaded with a zero-extended DImode value.  */
+  ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
 
   emit_move_insn (tmp, mem);
 
   label = gen_label_rtx ();
   emit_label (label);
   emit_move_insn (old, tmp);
-  emit_move_insn (ccv, tmp);
+  convert_move (ccv, tmp, /*unsignedp=*/1);
 
   /* Perform the specific operation.  Special case NAND by noticing
      one_cmpl_optab instead.  */
@@ -8007,6 +8009,11 @@ ia64_expand_compare_and_swap (enum machine_mode rmode, enum machine_mode mode,
   mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
   MEM_VOLATILE_P (mem) = 1;
 
+  if (GET_MODE (old) != mode)
+    old = convert_to_mode (mode, old, /*unsignedp=*/1);
+  if (GET_MODE (new) != mode)
+    new = convert_to_mode (mode, new, /*unsignedp=*/1);
+
   if (! register_operand (old, mode))
     old = copy_to_mode_reg (mode, old);
   if (! register_operand (new, mode))
@@ -8018,14 +8025,7 @@ ia64_expand_compare_and_swap (enum machine_mode rmode, enum machine_mode mode,
     tmp = gen_reg_rtx (mode);
 
   ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
-  if (mode == DImode)
-    emit_move_insn (ccv, old);
-  else
-    {
-      rtx ccvtmp = gen_reg_rtx (DImode);
-      emit_insn (gen_zero_extendsidi2 (ccvtmp, old));
-      emit_move_insn (ccv, ccvtmp);
-    }
+  convert_move (ccv, old, /*unsignedp=*/1);
   emit_insn (gen_mf ());
   if (mode == SImode)
     insn = gen_cmpxchg_acq_si (tmp, mem, new, ccv);

diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index da7bff4..e6bf9fe 100644 (file)
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -5388,7 +5388,7 @@
    (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
         (unspec:SI [(match_dup 1)
                     (match_operand:SI 2 "gr_register_operand" "r")
-                   (match_operand 3 "ar_ccv_reg_operand" "")]
+                   (match_operand:DI 3 "ar_ccv_reg_operand" "")]
                   UNSPEC_CMPXCHG_ACQ))]
   ""
   "cmpxchg4.acq %0 = %1, %2, %3"