arm64: dts: qcom: qcs404: fix default pinctrl settings for blsp1_spi1

The current settings refer to "blsp_spi1" function which isn't defined.
For this reason an attempt to enable blsp1_spi1 interface results in
the probe failure below:

[    3.492900] qcs404-pinctrl 1000000.pinctrl: invalid function blsp_spi1 in map table
[    3.502460] qcs404-pinctrl 1000000.pinctrl: invalid function blsp_spi1 in map table
[    3.517725] qcs404-pinctrl 1000000.pinctrl: invalid function blsp_spi1 in map table
[    3.532998] qcs404-pinctrl 1000000.pinctrl: invalid function blsp_spi1 in map table
[    3.548277] spi_qup: probe of 78b6000.spi failed with error -22

Fix this by making the functions used in qcs404.dtsi to match the contents
of drivers/pinctrl/qcom/pinctrl-qcs404.c.

Signed-off-by: Andrey Konovalov <andrey.konovalov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220611195713.131597-1-andrey.konovalov@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 1cdbe66..e4e4061 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -669,8 +669,25 @@
                        };
 
                        blsp1_spi1_default: blsp1-spi1-default {
-                               pins = "gpio22", "gpio23", "gpio24", "gpio25";
-                               function = "blsp_spi1";
+                               mosi {
+                                       pins = "gpio22";
+                                       function = "blsp_spi_mosi_a1";
+                               };
+
+                               miso {
+                                       pins = "gpio23";
+                                       function = "blsp_spi_miso_a1";
+                               };
+
+                               cs_n {
+                                       pins = "gpio24";
+                                       function = "blsp_spi_cs_n_a1";
+                               };
+
+                               clk {
+                                       pins = "gpio25";
+                                       function = "blsp_spi_clk_a1";
+                               };
                        };
 
                        blsp1_spi2_default: blsp1-spi2-default {