IBM Z: Fix *vec_tf_to_v1tf constraints

Certain alternatives of *vec_tf_to_v1tf use "v" constraint for its
TFmode source operand.  Therefore it is assigned to VEC_REGS class,
and when it is reloaded using *movtf_64, whose relevant alternatives
need FP_REGS, LRA loops and ICE happens.  The reason is that register
class mismatch causes LRA to emit another reload, which triggers this
issue again.

Fix by using "f" constraint, which is more appropriate for FP register
pairs anyway.

gcc/ChangeLog:

2020-09-02  Ilya Leoshkevich  <iii@linux.ibm.com>

	* config/s390/vector.md(*vec_tf_to_v1tf): Use "f" instead of "v"
	  for the source operand.

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 131bbda..2573b7d 100644 (file)
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -567,7 +567,7 @@
 ; single vector register.
 (define_insn "*vec_tf_to_v1tf"
   [(set (match_operand:V1TF                   0 "nonimmediate_operand" "=v,v,R,v,v")
-       (vec_duplicate:V1TF (match_operand:TF 1 "general_operand"       "v,R,v,G,d")))]
+       (vec_duplicate:V1TF (match_operand:TF 1 "general_operand"       "f,R,f,G,d")))]
   "TARGET_VX"
   "@
    vmrhg\t%v0,%1,%N1