Merge remote-tracking branches 'spi/topic/mtk', 'spi/topic/pxa2xx', 'spi/topic/qspi...

diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
new file mode 100644 (file)
index 0000000..dcefc43
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
@@ -0,0 +1,51 @@
+Binding for MTK SPI controller
+
+Required properties:
+- compatible: should be one of the following.
+    - mediatek,mt8173-spi: for mt8173 platforms
+    - mediatek,mt8135-spi: for mt8135 platforms
+    - mediatek,mt6589-spi: for mt6589 platforms
+
+- #address-cells: should be 1.
+
+- #size-cells: should be 0.
+
+- reg: Address and length of the register set for the device
+
+- interrupts: Should contain spi interrupt
+
+- clocks: phandles to input clocks.
+  The first should be <&topckgen CLK_TOP_SPI_SEL>.
+  The second should be one of the following.
+   -  <&clk26m>: specify parent clock 26MHZ.
+   -  <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
+                                     It's the default one.
+   -  <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
+   -  <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
+   -  <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
+
+- clock-names: shall be "spi-clk" for the controller clock, and
+  "parent-clk" for the parent clock.
+
+Optional properties:
+- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi
+  controller used, this value should be 0~3, only required for MT8173.
+    0: specify GPIO69,70,71,72 for spi pins.
+    1: specify GPIO102,103,104,105 for spi pins.
+    2: specify GPIO128,129,130,131 for spi pins.
+    3: specify GPIO5,6,7,8 for spi pins.
+
+Example:
+
+- SoC Specific Portion:
+spi: spi@1100a000 {
+       compatible = "mediatek,mt8173-spi";
+       #address-cells = <1>;
+       #size-cells = <0>;
+       reg = <0 0x1100a000 0 0x1000>;
+       interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
+       clocks = <&topckgen CLK_TOP_SPI_SEL>, <&topckgen CLK_TOP_SYSPLL3_D2>;
+       clock-names = "spi-clk", "parent-clk";
+       mediatek,pad-select = <0>;
+       status = "disabled";
+};

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b0f30fb..43f6d3d 100644 (file)
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -326,6 +326,15 @@ config SPI_MESON_SPIFC
          This enables master mode support for the SPIFC (SPI flash
          controller) available in Amlogic Meson SoCs.
 
+config SPI_MT65XX
+       tristate "MediaTek SPI controller"
+       depends on ARCH_MEDIATEK || COMPILE_TEST
+       help
+         This selects the MediaTek(R) SPI bus driver.
+         If you want to use MediaTek(R) SPI interface,
+         say Y or M here.If you are not sure, say N.
+         SPI drivers for Mediatek MT65XX and MT81XX series ARM SoCs.
+
 config SPI_OC_TINY
        tristate "OpenCores tiny SPI"
        depends on GPIOLIB || COMPILE_TEST

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 1154dba..9746beb 100644 (file)
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_SPI_MESON_SPIFC)         += spi-meson-spifc.o
 obj-$(CONFIG_SPI_MPC512x_PSC)          += spi-mpc512x-psc.o
 obj-$(CONFIG_SPI_MPC52xx_PSC)          += spi-mpc52xx-psc.o
 obj-$(CONFIG_SPI_MPC52xx)              += spi-mpc52xx.o
+obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o
 obj-$(CONFIG_SPI_MXS)                  += spi-mxs.o
 obj-$(CONFIG_SPI_NUC900)               += spi-nuc900.o
 obj-$(CONFIG_SPI_OC_TINY)              += spi-oc-tiny.o

diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
new file mode 100644 (file)
index 0000000..5f6315c
--- /dev/null
+++ b/drivers/spi/spi-mt65xx.c
@@ -0,0 +1,726 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Leilk Liu <leilk.liu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/spi-mt65xx.h>
+#include <linux/pm_runtime.h>
+#include <linux/spi/spi.h>
+
+#define SPI_CFG0_REG                      0x0000
+#define SPI_CFG1_REG                      0x0004
+#define SPI_TX_SRC_REG                    0x0008
+#define SPI_RX_DST_REG                    0x000c
+#define SPI_TX_DATA_REG                   0x0010
+#define SPI_RX_DATA_REG                   0x0014
+#define SPI_CMD_REG                       0x0018
+#define SPI_STATUS0_REG                   0x001c
+#define SPI_PAD_SEL_REG                   0x0024
+
+#define SPI_CFG0_SCK_HIGH_OFFSET          0
+#define SPI_CFG0_SCK_LOW_OFFSET           8
+#define SPI_CFG0_CS_HOLD_OFFSET           16
+#define SPI_CFG0_CS_SETUP_OFFSET          24
+
+#define SPI_CFG1_CS_IDLE_OFFSET           0
+#define SPI_CFG1_PACKET_LOOP_OFFSET       8
+#define SPI_CFG1_PACKET_LENGTH_OFFSET     16
+#define SPI_CFG1_GET_TICK_DLY_OFFSET      30
+
+#define SPI_CFG1_CS_IDLE_MASK             0xff
+#define SPI_CFG1_PACKET_LOOP_MASK         0xff00
+#define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000
+
+#define SPI_CMD_ACT                  BIT(0)
+#define SPI_CMD_RESUME               BIT(1)
+#define SPI_CMD_RST                  BIT(2)
+#define SPI_CMD_PAUSE_EN             BIT(4)
+#define SPI_CMD_DEASSERT             BIT(5)
+#define SPI_CMD_CPHA                 BIT(8)
+#define SPI_CMD_CPOL                 BIT(9)
+#define SPI_CMD_RX_DMA               BIT(10)
+#define SPI_CMD_TX_DMA               BIT(11)
+#define SPI_CMD_TXMSBF               BIT(12)
+#define SPI_CMD_RXMSBF               BIT(13)
+#define SPI_CMD_RX_ENDIAN            BIT(14)
+#define SPI_CMD_TX_ENDIAN            BIT(15)
+#define SPI_CMD_FINISH_IE            BIT(16)
+#define SPI_CMD_PAUSE_IE             BIT(17)
+
+#define MT8173_SPI_MAX_PAD_SEL 3
+
+#define MTK_SPI_PAUSE_INT_STATUS 0x2
+
+#define MTK_SPI_IDLE 0
+#define MTK_SPI_PAUSED 1
+
+#define MTK_SPI_MAX_FIFO_SIZE 32
+#define MTK_SPI_PACKET_SIZE 1024
+
+struct mtk_spi_compatible {
+       bool need_pad_sel;
+       /* Must explicitly send dummy Tx bytes to do Rx only transfer */
+       bool must_tx;
+};
+
+struct mtk_spi {
+       void __iomem *base;
+       u32 state;
+       u32 pad_sel;
+       struct clk *spi_clk, *parent_clk;
+       struct spi_transfer *cur_transfer;
+       u32 xfer_len;
+       struct scatterlist *tx_sgl, *rx_sgl;
+       u32 tx_sgl_len, rx_sgl_len;
+       const struct mtk_spi_compatible *dev_comp;
+};
+
+static const struct mtk_spi_compatible mt6589_compat;
+static const struct mtk_spi_compatible mt8135_compat;
+static const struct mtk_spi_compatible mt8173_compat = {
+       .need_pad_sel = true,
+       .must_tx = true,
+};
+
+/*
+ * A piece of default chip info unless the platform
+ * supplies it.
+ */
+static const struct mtk_chip_config mtk_default_chip_info = {
+       .rx_mlsb = 1,
+       .tx_mlsb = 1,
+};
+
+static const struct of_device_id mtk_spi_of_match[] = {
+       { .compatible = "mediatek,mt6589-spi", .data = (void *)&mt6589_compat },
+       { .compatible = "mediatek,mt8135-spi", .data = (void *)&mt8135_compat },
+       { .compatible = "mediatek,mt8173-spi", .data = (void *)&mt8173_compat },
+       {}
+};
+MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
+
+static void mtk_spi_reset(struct mtk_spi *mdata)
+{
+       u32 reg_val;
+
+       /* set the software reset bit in SPI_CMD_REG. */
+       reg_val = readl(mdata->base + SPI_CMD_REG);
+       reg_val |= SPI_CMD_RST;
+       writel(reg_val, mdata->base + SPI_CMD_REG);
+
+       reg_val = readl(mdata->base + SPI_CMD_REG);
+       reg_val &= ~SPI_CMD_RST;
+       writel(reg_val, mdata->base + SPI_CMD_REG);
+}
+
+static void mtk_spi_config(struct mtk_spi *mdata,
+                          struct mtk_chip_config *chip_config)
+{
+       u32 reg_val;
+
+       reg_val = readl(mdata->base + SPI_CMD_REG);
+
+       /* set the mlsbx and mlsbtx */
+       if (chip_config->tx_mlsb)
+               reg_val |= SPI_CMD_TXMSBF;
+       else
+               reg_val &= ~SPI_CMD_TXMSBF;
+       if (chip_config->rx_mlsb)
+               reg_val |= SPI_CMD_RXMSBF;
+       else
+               reg_val &= ~SPI_CMD_RXMSBF;
+
+       /* set the tx/rx endian */
+#ifdef __LITTLE_ENDIAN
+       reg_val &= ~SPI_CMD_TX_ENDIAN;
+       reg_val &= ~SPI_CMD_RX_ENDIAN;
+#else
+       reg_val |= SPI_CMD_TX_ENDIAN;
+       reg_val |= SPI_CMD_RX_ENDIAN;
+#endif
+
+       /* set finish and pause interrupt always enable */
+       reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
+
+       /* disable dma mode */
+       reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
+
+       /* disable deassert mode */
+       reg_val &= ~SPI_CMD_DEASSERT;
+
+       writel(reg_val, mdata->base + SPI_CMD_REG);
+
+       /* pad select */
+       if (mdata->dev_comp->need_pad_sel)
+               writel(mdata->pad_sel, mdata->base + SPI_PAD_SEL_REG);
+}
+
+static int mtk_spi_prepare_hardware(struct spi_master *master)
+{
+       struct spi_transfer *trans;
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+       struct spi_message *msg = master->cur_msg;
+
+       trans = list_first_entry(&msg->transfers, struct spi_transfer,
+                                transfer_list);
+       if (!trans->cs_change) {
+               mdata->state = MTK_SPI_IDLE;
+               mtk_spi_reset(mdata);
+       }
+
+       return 0;
+}
+
+static int mtk_spi_prepare_message(struct spi_master *master,
+                                  struct spi_message *msg)
+{
+       u32 reg_val;
+       u8 cpha, cpol;
+       struct mtk_chip_config *chip_config;
+       struct spi_device *spi = msg->spi;
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+
+       cpha = spi->mode & SPI_CPHA ? 1 : 0;
+       cpol = spi->mode & SPI_CPOL ? 1 : 0;
+
+       reg_val = readl(mdata->base + SPI_CMD_REG);
+       if (cpha)
+               reg_val |= SPI_CMD_CPHA;
+       else
+               reg_val &= ~SPI_CMD_CPHA;
+       if (cpol)
+               reg_val |= SPI_CMD_CPOL;
+       else
+               reg_val &= ~SPI_CMD_CPOL;
+       writel(reg_val, mdata->base + SPI_CMD_REG);
+
+       chip_config = spi->controller_data;
+       if (!chip_config) {
+               chip_config = (void *)&mtk_default_chip_info;
+               spi->controller_data = chip_config;
+       }
+       mtk_spi_config(mdata, chip_config);
+
+       return 0;
+}
+
+static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
+{
+       u32 reg_val;
+       struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
+
+       reg_val = readl(mdata->base + SPI_CMD_REG);
+       if (!enable)
+               reg_val |= SPI_CMD_PAUSE_EN;
+       else
+               reg_val &= ~SPI_CMD_PAUSE_EN;
+       writel(reg_val, mdata->base + SPI_CMD_REG);
+}
+
+static void mtk_spi_prepare_transfer(struct spi_master *master,
+                                    struct spi_transfer *xfer)
+{
+       u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+
+       spi_clk_hz = clk_get_rate(mdata->spi_clk);
+       if (xfer->speed_hz < spi_clk_hz / 2)
+               div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
+       else
+               div = 1;
+
+       sck_time = (div + 1) / 2;
+       cs_time = sck_time * 2;
+
+       reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET);
+       reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
+       reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
+       reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
+       writel(reg_val, mdata->base + SPI_CFG0_REG);
+
+       reg_val = readl(mdata->base + SPI_CFG1_REG);
+       reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
+       reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
+       writel(reg_val, mdata->base + SPI_CFG1_REG);
+}
+
+static void mtk_spi_setup_packet(struct spi_master *master)
+{
+       u32 packet_size, packet_loop, reg_val;
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+
+       packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
+       packet_loop = mdata->xfer_len / packet_size;
+
+       reg_val = readl(mdata->base + SPI_CFG1_REG);
+       reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
+       reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
+       reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
+       writel(reg_val, mdata->base + SPI_CFG1_REG);
+}
+
+static void mtk_spi_enable_transfer(struct spi_master *master)
+{
+       u32 cmd;
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+
+       cmd = readl(mdata->base + SPI_CMD_REG);
+       if (mdata->state == MTK_SPI_IDLE)
+               cmd |= SPI_CMD_ACT;
+       else
+               cmd |= SPI_CMD_RESUME;
+       writel(cmd, mdata->base + SPI_CMD_REG);
+}
+
+static int mtk_spi_get_mult_delta(u32 xfer_len)
+{
+       u32 mult_delta;
+
+       if (xfer_len > MTK_SPI_PACKET_SIZE)
+               mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
+       else
+               mult_delta = 0;
+
+       return mult_delta;
+}
+
+static void mtk_spi_update_mdata_len(struct spi_master *master)
+{
+       int mult_delta;
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+
+       if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
+               if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
+                       mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
+                       mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
+                       mdata->rx_sgl_len = mult_delta;
+                       mdata->tx_sgl_len -= mdata->xfer_len;
+               } else {
+                       mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
+                       mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
+                       mdata->tx_sgl_len = mult_delta;
+                       mdata->rx_sgl_len -= mdata->xfer_len;
+               }
+       } else if (mdata->tx_sgl_len) {
+               mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
+               mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
+               mdata->tx_sgl_len = mult_delta;
+       } else if (mdata->rx_sgl_len) {
+               mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
+               mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
+               mdata->rx_sgl_len = mult_delta;
+       }
+}
+
+static void mtk_spi_setup_dma_addr(struct spi_master *master,
+                                  struct spi_transfer *xfer)
+{
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+
+       if (mdata->tx_sgl)
+               writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG);
+       if (mdata->rx_sgl)
+               writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG);
+}
+
+static int mtk_spi_fifo_transfer(struct spi_master *master,
+                                struct spi_device *spi,
+                                struct spi_transfer *xfer)
+{
+       int cnt;
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+
+       mdata->cur_transfer = xfer;
+       mdata->xfer_len = xfer->len;
+       mtk_spi_prepare_transfer(master, xfer);
+       mtk_spi_setup_packet(master);
+
+       if (xfer->len % 4)
+               cnt = xfer->len / 4 + 1;
+       else
+               cnt = xfer->len / 4;
+       iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
+
+       mtk_spi_enable_transfer(master);
+
+       return 1;
+}
+
+static int mtk_spi_dma_transfer(struct spi_master *master,
+                               struct spi_device *spi,
+                               struct spi_transfer *xfer)
+{
+       int cmd;
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+
+       mdata->tx_sgl = NULL;
+       mdata->rx_sgl = NULL;
+       mdata->tx_sgl_len = 0;
+       mdata->rx_sgl_len = 0;
+       mdata->cur_transfer = xfer;
+
+       mtk_spi_prepare_transfer(master, xfer);
+
+       cmd = readl(mdata->base + SPI_CMD_REG);
+       if (xfer->tx_buf)
+               cmd |= SPI_CMD_TX_DMA;
+       if (xfer->rx_buf)
+               cmd |= SPI_CMD_RX_DMA;
+       writel(cmd, mdata->base + SPI_CMD_REG);
+
+       if (xfer->tx_buf)
+               mdata->tx_sgl = xfer->tx_sg.sgl;
+       if (xfer->rx_buf)
+               mdata->rx_sgl = xfer->rx_sg.sgl;
+
+       if (mdata->tx_sgl) {
+               xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
+               mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
+       }
+       if (mdata->rx_sgl) {
+               xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
+               mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
+       }
+
+       mtk_spi_update_mdata_len(master);
+       mtk_spi_setup_packet(master);
+       mtk_spi_setup_dma_addr(master, xfer);
+       mtk_spi_enable_transfer(master);
+
+       return 1;
+}
+
+static int mtk_spi_transfer_one(struct spi_master *master,
+                               struct spi_device *spi,
+                               struct spi_transfer *xfer)
+{
+       if (master->can_dma(master, spi, xfer))
+               return mtk_spi_dma_transfer(master, spi, xfer);
+       else
+               return mtk_spi_fifo_transfer(master, spi, xfer);
+}
+
+static bool mtk_spi_can_dma(struct spi_master *master,
+                           struct spi_device *spi,
+                           struct spi_transfer *xfer)
+{
+       return xfer->len > MTK_SPI_MAX_FIFO_SIZE;
+}
+
+static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
+{
+       u32 cmd, reg_val, cnt;
+       struct spi_master *master = dev_id;
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+       struct spi_transfer *trans = mdata->cur_transfer;
+
+       reg_val = readl(mdata->base + SPI_STATUS0_REG);
+       if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
+               mdata->state = MTK_SPI_PAUSED;
+       else
+               mdata->state = MTK_SPI_IDLE;
+
+       if (!master->can_dma(master, master->cur_msg->spi, trans)) {
+               if (trans->rx_buf) {
+                       if (mdata->xfer_len % 4)
+                               cnt = mdata->xfer_len / 4 + 1;
+                       else
+                               cnt = mdata->xfer_len / 4;
+                       ioread32_rep(mdata->base + SPI_RX_DATA_REG,
+                                    trans->rx_buf, cnt);
+               }
+               spi_finalize_current_transfer(master);
+               return IRQ_HANDLED;
+       }
+
+       if (mdata->tx_sgl)
+               trans->tx_dma += mdata->xfer_len;
+       if (mdata->rx_sgl)
+               trans->rx_dma += mdata->xfer_len;
+
+       if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
+               mdata->tx_sgl = sg_next(mdata->tx_sgl);
+               if (mdata->tx_sgl) {
+                       trans->tx_dma = sg_dma_address(mdata->tx_sgl);
+                       mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
+               }
+       }
+       if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
+               mdata->rx_sgl = sg_next(mdata->rx_sgl);
+               if (mdata->rx_sgl) {
+                       trans->rx_dma = sg_dma_address(mdata->rx_sgl);
+                       mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
+               }
+       }
+
+       if (!mdata->tx_sgl && !mdata->rx_sgl) {
+               /* spi disable dma */
+               cmd = readl(mdata->base + SPI_CMD_REG);
+               cmd &= ~SPI_CMD_TX_DMA;
+               cmd &= ~SPI_CMD_RX_DMA;
+               writel(cmd, mdata->base + SPI_CMD_REG);
+
+               spi_finalize_current_transfer(master);
+               return IRQ_HANDLED;
+       }
+
+       mtk_spi_update_mdata_len(master);
+       mtk_spi_setup_packet(master);
+       mtk_spi_setup_dma_addr(master, trans);
+       mtk_spi_enable_transfer(master);
+
+       return IRQ_HANDLED;
+}
+
+static int mtk_spi_probe(struct platform_device *pdev)
+{
+       struct spi_master *master;
+       struct mtk_spi *mdata;
+       const struct of_device_id *of_id;
+       struct resource *res;
+       int irq, ret;
+
+       master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
+       if (!master) {
+               dev_err(&pdev->dev, "failed to alloc spi master\n");
+               return -ENOMEM;
+       }
+
+       master->auto_runtime_pm = true;
+       master->dev.of_node = pdev->dev.of_node;
+       master->mode_bits = SPI_CPOL | SPI_CPHA;
+
+       master->set_cs = mtk_spi_set_cs;
+       master->prepare_transfer_hardware = mtk_spi_prepare_hardware;
+       master->prepare_message = mtk_spi_prepare_message;
+       master->transfer_one = mtk_spi_transfer_one;
+       master->can_dma = mtk_spi_can_dma;
+
+       of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
+       if (!of_id) {
+               dev_err(&pdev->dev, "failed to probe of_node\n");
+               ret = -EINVAL;
+               goto err_put_master;
+       }
+
+       mdata = spi_master_get_devdata(master);
+       mdata->dev_comp = of_id->data;
+       if (mdata->dev_comp->must_tx)
+               master->flags = SPI_MASTER_MUST_TX;
+
+       if (mdata->dev_comp->need_pad_sel) {
+               ret = of_property_read_u32(pdev->dev.of_node,
+                                          "mediatek,pad-select",
+                                          &mdata->pad_sel);
+               if (ret) {
+                       dev_err(&pdev->dev, "failed to read pad select: %d\n",
+                               ret);
+                       goto err_put_master;
+               }
+
+               if (mdata->pad_sel > MT8173_SPI_MAX_PAD_SEL) {
+                       dev_err(&pdev->dev, "wrong pad-select: %u\n",
+                               mdata->pad_sel);
+                       ret = -EINVAL;
+                       goto err_put_master;
+               }
+       }
+
+       platform_set_drvdata(pdev, master);
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       if (!res) {
+               ret = -ENODEV;
+               dev_err(&pdev->dev, "failed to determine base address\n");
+               goto err_put_master;
+       }
+
+       mdata->base = devm_ioremap_resource(&pdev->dev, res);
+       if (IS_ERR(mdata->base)) {
+               ret = PTR_ERR(mdata->base);
+               goto err_put_master;
+       }
+
+       irq = platform_get_irq(pdev, 0);
+       if (irq < 0) {
+               dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
+               ret = irq;
+               goto err_put_master;
+       }
+
+       if (!pdev->dev.dma_mask)
+               pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+
+       ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
+                              IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
+       if (ret) {
+               dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
+               goto err_put_master;
+       }
+
+       mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
+       if (IS_ERR(mdata->spi_clk)) {
+               ret = PTR_ERR(mdata->spi_clk);
+               dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
+               goto err_put_master;
+       }
+
+       mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
+       if (IS_ERR(mdata->parent_clk)) {
+               ret = PTR_ERR(mdata->parent_clk);
+               dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
+               goto err_put_master;
+       }
+
+       ret = clk_prepare_enable(mdata->spi_clk);
+       if (ret < 0) {
+               dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
+               goto err_put_master;
+       }
+
+       ret = clk_set_parent(mdata->spi_clk, mdata->parent_clk);
+       if (ret < 0) {
+               dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
+               goto err_disable_clk;
+       }
+
+       clk_disable_unprepare(mdata->spi_clk);
+
+       pm_runtime_enable(&pdev->dev);
+
+       ret = devm_spi_register_master(&pdev->dev, master);
+       if (ret) {
+               dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
+               goto err_put_master;
+       }
+
+       return 0;
+
+err_disable_clk:
+       clk_disable_unprepare(mdata->spi_clk);
+err_put_master:
+       spi_master_put(master);
+
+       return ret;
+}
+
+static int mtk_spi_remove(struct platform_device *pdev)
+{
+       struct spi_master *master = platform_get_drvdata(pdev);
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+
+       pm_runtime_disable(&pdev->dev);
+
+       mtk_spi_reset(mdata);
+       clk_disable_unprepare(mdata->spi_clk);
+       spi_master_put(master);
+
+       return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int mtk_spi_suspend(struct device *dev)
+{
+       int ret;
+       struct spi_master *master = dev_get_drvdata(dev);
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+
+       ret = spi_master_suspend(master);
+       if (ret)
+               return ret;
+
+       if (!pm_runtime_suspended(dev))
+               clk_disable_unprepare(mdata->spi_clk);
+
+       return ret;
+}
+
+static int mtk_spi_resume(struct device *dev)
+{
+       int ret;
+       struct spi_master *master = dev_get_drvdata(dev);
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+
+       if (!pm_runtime_suspended(dev)) {
+               ret = clk_prepare_enable(mdata->spi_clk);
+               if (ret < 0) {
+                       dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
+                       return ret;
+               }
+       }
+
+       ret = spi_master_resume(master);
+       if (ret < 0)
+               clk_disable_unprepare(mdata->spi_clk);
+
+       return ret;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+#ifdef CONFIG_PM
+static int mtk_spi_runtime_suspend(struct device *dev)
+{
+       struct spi_master *master = dev_get_drvdata(dev);
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+
+       clk_disable_unprepare(mdata->spi_clk);
+
+       return 0;
+}
+
+static int mtk_spi_runtime_resume(struct device *dev)
+{
+       struct spi_master *master = dev_get_drvdata(dev);
+       struct mtk_spi *mdata = spi_master_get_devdata(master);
+       int ret;
+
+       ret = clk_prepare_enable(mdata->spi_clk);
+       if (ret < 0) {
+               dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
+               return ret;
+       }
+
+       return 0;
+}
+#endif /* CONFIG_PM */
+
+static const struct dev_pm_ops mtk_spi_pm = {
+       SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
+       SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
+                          mtk_spi_runtime_resume, NULL)
+};
+
+static struct platform_driver mtk_spi_driver = {
+       .driver = {
+               .name = "mtk-spi",
+               .pm     = &mtk_spi_pm,
+               .of_match_table = mtk_spi_of_match,
+       },
+       .probe = mtk_spi_probe,
+       .remove = mtk_spi_remove,
+};
+
+module_platform_driver(mtk_spi_driver);
+
+MODULE_DESCRIPTION("MTK SPI Controller driver");
+MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:mtk-spi");

diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c
index 3cfd435..d19d7f2 100644 (file)
--- a/drivers/spi/spi-pxa2xx-pci.c
+++ b/drivers/spi/spi-pxa2xx-pci.c
@@ -7,7 +7,6 @@
 #include <linux/of_device.h>
 #include <linux/module.h>
 #include <linux/spi/pxa2xx_spi.h>
-#include <linux/clk.h>
 #include <linux/clk-provider.h>
 
 #include <linux/dmaengine.h>

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 7293d6d..fdd7919 100644 (file)
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -21,6 +21,7 @@
 #include <linux/err.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
+#include <linux/pci.h>
 #include <linux/platform_device.h>
 #include <linux/spi/pxa2xx_spi.h>
 #include <linux/spi/spi.h>
@@ -97,6 +98,15 @@ static const struct lpss_config lpss_platforms[] = {
                .tx_threshold_lo = 160,
                .tx_threshold_hi = 224,
        },
+       {       /* LPSS_SPT_SSP */
+               .offset = 0x200,
+               .reg_general = -1,
+               .reg_ssp = 0x20,
+               .reg_cs_ctrl = 0x24,
+               .rx_threshold = 1,
+               .tx_threshold_lo = 32,
+               .tx_threshold_hi = 56,
+       },
 };
 
 static inline const struct lpss_config
@@ -110,6 +120,7 @@ static bool is_lpss_ssp(const struct driver_data *drv_data)
        switch (drv_data->ssp_type) {
        case LPSS_LPT_SSP:
        case LPSS_BYT_SSP:
+       case LPSS_SPT_SSP:
                return true;
        default:
                return false;
@@ -1107,6 +1118,7 @@ static int setup(struct spi_device *spi)
                break;
        case LPSS_LPT_SSP:
        case LPSS_BYT_SSP:
+       case LPSS_SPT_SSP:
                config = lpss_get_config(drv_data);
                tx_thres = config->tx_threshold_lo;
                tx_hi_thres = config->tx_threshold_hi;
@@ -1276,6 +1288,31 @@ static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
 };
 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
 
+/*
+ * PCI IDs of compound devices that integrate both host controller and private
+ * integrated DMA engine. Please note these are not used in module
+ * autoloading and probing in this module but matching the LPSS SSP type.
+ */
+static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
+       /* SPT-LP */
+       { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
+       { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
+       /* SPT-H */
+       { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
+       { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
+       { },
+};
+
+static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
+{
+       struct device *dev = param;
+
+       if (dev != chan->device->dev->parent)
+               return false;
+
+       return true;
+}
+
 static struct pxa2xx_spi_master *
 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
 {
@@ -1283,16 +1320,25 @@ pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
        struct acpi_device *adev;
        struct ssp_device *ssp;
        struct resource *res;
-       const struct acpi_device_id *id;
+       const struct acpi_device_id *adev_id = NULL;
+       const struct pci_device_id *pcidev_id = NULL;
        int devid, type;
 
        if (!ACPI_HANDLE(&pdev->dev) ||
            acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
                return NULL;
 
-       id = acpi_match_device(pdev->dev.driver->acpi_match_table, &pdev->dev);
-       if (id)
-               type = (int)id->driver_data;
+       if (dev_is_pci(pdev->dev.parent))
+               pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
+                                        to_pci_dev(pdev->dev.parent));
+       else
+               adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
+                                           &pdev->dev);
+
+       if (adev_id)
+               type = (int)adev_id->driver_data;
+       else if (pcidev_id)
+               type = (int)pcidev_id->driver_data;
        else
                return NULL;
 
@@ -1311,6 +1357,12 @@ pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
        if (IS_ERR(ssp->mmio_base))
                return NULL;
 
+       if (pcidev_id) {
+               pdata->tx_param = pdev->dev.parent;
+               pdata->rx_param = pdev->dev.parent;
+               pdata->dma_filter = pxa2xx_spi_idma_filter;
+       }
+
        ssp->clk = devm_clk_get(&pdev->dev, NULL);
        ssp->irq = platform_get_irq(pdev, 0);
        ssp->type = type;
@@ -1362,8 +1414,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
                return -ENODEV;
        }
 
-       /* Allocate master with space for drv_data and null dma buffer */
-       master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
+       master = spi_alloc_master(dev, sizeof(struct driver_data));
        if (!master) {
                dev_err(&pdev->dev, "cannot alloc spi_master\n");
                pxa_ssp_free(ssp);
@@ -1390,7 +1441,6 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
        master->auto_runtime_pm = true;
 
        drv_data->ssp_type = ssp->type;
-       drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
 
        drv_data->ioaddr = ssp->mmio_base;
        drv_data->ssdr_physical = ssp->phys_base + SSDR;
@@ -1424,8 +1474,6 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
        }
 
        /* Setup DMA if requested */
-       drv_data->tx_channel = -1;
-       drv_data->rx_channel = -1;
        if (platform_info->enable_dma) {
                status = pxa2xx_spi_dma_setup(drv_data);
                if (status) {

diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h
index 9f01e9c..0a9b639 100644 (file)
--- a/drivers/spi/spi-pxa2xx.h
+++ b/drivers/spi/spi-pxa2xx.h
@@ -36,11 +36,6 @@ struct driver_data {
        /* PXA hookup */
        struct pxa2xx_spi_master *master_info;
 
-       /* PXA private DMA setup stuff */
-       int rx_channel;
-       int tx_channel;
-       u32 *null_dma_buf;
-
        /* SSP register addresses */
        void __iomem *ioaddr;
        u32 ssdr_physical;

diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 68e7efe..79a8bc4 100644 (file)
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -645,7 +645,6 @@ static int rockchip_spi_probe(struct platform_device *pdev)
        platform_set_drvdata(pdev, master);
 
        rs = spi_master_get_devdata(master);
-       memset(rs, 0, sizeof(struct rockchip_spi));
 
        /* Get basic io resource and map it */
        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);

diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index f9189a0..8188433 100644 (file)
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -383,7 +383,8 @@ static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
        rspi_write8(rspi, data, reg);
 }
 
-static int qspi_set_send_trigger(struct rspi_data *rspi, unsigned int len)
+static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
+                                         unsigned int len)
 {
        unsigned int n;
 
@@ -724,25 +725,25 @@ static int rspi_rz_transfer_one(struct spi_master *master,
 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
                                        u8 *rx, unsigned int len)
 {
-       int i, n, ret;
-       int error;
+       unsigned int i, n;
+       int ret;
 
        while (len > 0) {
                n = qspi_set_send_trigger(rspi, len);
                qspi_set_receive_trigger(rspi, len);
                if (n == QSPI_BUFFER_SIZE) {
-                       error = rspi_wait_for_tx_empty(rspi);
-                       if (error < 0) {
+                       ret = rspi_wait_for_tx_empty(rspi);
+                       if (ret < 0) {
                                dev_err(&rspi->master->dev, "transmit timeout\n");
-                               return error;
+                               return ret;
                        }
                        for (i = 0; i < n; i++)
                                rspi_write_data(rspi, *tx++);
 
-                       error = rspi_wait_for_rx_full(rspi);
-                       if (error < 0) {
+                       ret = rspi_wait_for_rx_full(rspi);
+                       if (ret < 0) {
                                dev_err(&rspi->master->dev, "receive timeout\n");
-                               return error;
+                               return ret;
                        }
                        for (i = 0; i < n; i++)
                                *rx++ = rspi_read_data(rspi);

diff --git a/drivers/spi/spi-s3c24xx.c b/drivers/spi/spi-s3c24xx.c
index f747ca2..f36bc32 100644 (file)
--- a/drivers/spi/spi-s3c24xx.c
+++ b/drivers/spi/spi-s3c24xx.c
@@ -501,7 +501,6 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
        }
 
        hw = spi_master_get_devdata(master);
-       memset(hw, 0, sizeof(struct s3c24xx_spi));
 
        hw->master = master;
        hw->pdata = pdata = dev_get_platdata(&pdev->dev);

diff --git a/include/linux/platform_data/spi-mt65xx.h b/include/linux/platform_data/spi-mt65xx.h
new file mode 100644 (file)
index 0000000..54b0448
--- /dev/null
+++ b/include/linux/platform_data/spi-mt65xx.h
@@ -0,0 +1,20 @@
+/*
+ *  MTK SPI bus driver definitions
+ *
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Leilk Liu <leilk.liu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H
+#define ____LINUX_PLATFORM_DATA_SPI_MTK_H
+
+/* Board specific platform_data */
+struct mtk_chip_config {
+       u32 tx_mlsb;
+       u32 rx_mlsb;
+};
+#endif

diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h
index 0485bab..9227377 100644 (file)
--- a/include/linux/pxa2xx_ssp.h
+++ b/include/linux/pxa2xx_ssp.h
@@ -197,6 +197,7 @@ enum pxa_ssp_type {
        QUARK_X1000_SSP,
        LPSS_LPT_SSP, /* Keep LPSS types sorted with lpss_platforms[] */
        LPSS_BYT_SSP,
+       LPSS_SPT_SSP,
 };
 
 struct ssp_device {