i965: Rename ISP_DIS to INDIRECT_STATE_POINTERS_DISABLE.

Clearer name.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index a3f521b..704f651 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -362,7 +362,7 @@ gen10_emit_isp_disable(struct brw_context *brw)
                          PIPE_CONTROL_CS_STALL,
                          NULL, 0, 0);
    brw_emit_pipe_control(brw,
-                         PIPE_CONTROL_ISP_DIS |
+                         PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE |
                          PIPE_CONTROL_CS_STALL,
                          NULL, 0, 0);
 

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.h b/src/mesa/drivers/dri/i965/brw_pipe_control.h
index 4c58e16..69b1c7c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.h
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.h
@@ -48,7 +48,7 @@ struct brw_bo;
 #define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12)
 #define PIPE_CONTROL_INSTRUCTION_INVALIDATE (1 << 11)
 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE  (1 << 10) /* GM45+ only */
-#define PIPE_CONTROL_ISP_DIS           (1 << 9)
+#define PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE (1 << 9)
 #define PIPE_CONTROL_INTERRUPT_ENABLE  (1 << 8)
 #define PIPE_CONTROL_FLUSH_ENABLE      (1 << 7) /* Gen7+ only */
 /* GT */