IPP_CMD_MAX,
};
+/* define of color range */
+enum drm_exynos_color_range {
+ COLOR_RANGE_LIMITED, /* Narrow: Y(16 to 235), Cb/Cr(16 to 240) */
+ COLOR_RANGE_FULL, /* Wide: Y/Cb/Cr(0 to 255), Wide default */
+};
+
/**
* A structure for ipp property.
*
* @ipp_id: id of ipp driver.
* @prop_id: id of property.
* @refresh_rate: refresh rate.
+ * @range: dynamic range for csc.
+ * @pad: just padding to be 64-bit aligned.
*/
struct drm_exynos_ipp_property {
struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
__u32 ipp_id;
__u32 prop_id;
__u32 refresh_rate;
+ __u32 range;
+ __u32 pad;
};
/* definition of buffer */
}
property->config[EXYNOS_DRM_OPS_DST].pos = scale_pos;
property->config[EXYNOS_DRM_OPS_DST].sz = dst_sz;
+ property->range = COLOR_RANGE_FULL; /* Wide default */
break;
case IPP_CMD_WB:
property->config[EXYNOS_DRM_OPS_SRC].ops_id = EXYNOS_DRM_OPS_SRC;
}
property->config[EXYNOS_DRM_OPS_DST].pos = scale_pos;
property->config[EXYNOS_DRM_OPS_DST].sz = dst_sz;
+ property->range = COLOR_RANGE_FULL; /* Wide default */
break;
case IPP_CMD_OUTPUT:
default: