[X86] Lower zext i1 arguments

i1 is now a legal type for X86 with AVX512.
There were some paths in X86FastISel which were not quite ready to see
an i1 value: they were not quite sure how to deal with sign/zero extends
for call arguments.
DTRT by extending to i8 for zeroext and bailing out of FastISel for
signext.

This fixes PR27591.

llvm-svn: 268470

diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index 6eab3f1..d389452 100644 (file)
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -3019,6 +3019,10 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
     case CCValAssign::SExt: {
       assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
              "Unexpected extend");
+
+      if (ArgVT.SimpleTy == MVT::i1)
+        return false;
+
       bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg,
                                        ArgVT, ArgReg);
       assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
@@ -3028,6 +3032,17 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
     case CCValAssign::ZExt: {
       assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
              "Unexpected extend");
+
+      // Handle zero-extension from i1 to i8, which is common.
+      if (ArgVT.SimpleTy == MVT::i1) {
+        // Set the high bits to zero.
+        ArgReg = fastEmitZExtFromI1(MVT::i8, ArgReg, /*TODO: Kill=*/false);
+        ArgVT = MVT::i8;
+
+        if (ArgReg == 0)
+          return false;
+      }
+
       bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg,
                                        ArgVT, ArgReg);
       assert(Emitted && "Failed to emit a zext!"); (void)Emitted;

diff --git a/llvm/test/CodeGen/X86/pr27591.ll b/llvm/test/CodeGen/X86/pr27591.ll
new file mode 100644 (file)
index 0000000..bbafe59
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr27591.ll
@@ -0,0 +1,42 @@
+; RUN: llc -o - -O0 < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @test1(i32 %x) #0 {
+entry:
+  %tobool = icmp ne i32 %x, 0
+  call void @callee1(i1 zeroext %tobool)
+  ret void
+}
+
+; CHECK-LABEL: test1:
+; CHECK:      cmpl   $0, %edi
+; CHECK-NEXT: setne  %al
+; CHECK-NEXT: andb   $1, %al
+; CHECK-NEXT: movzbl %al, %edi
+; CHECK-NEXT: callq  callee1
+
+define void @test2(i32 %x) #0 {
+entry:
+  %tobool = icmp ne i32 %x, 0
+  call void @callee2(i1 signext %tobool)
+  ret void
+}
+
+; CHECK-LABEL: test2:
+; CHECK:      cmpl   $0, %edi
+; CHECK-NEXT: setne  %al
+; CHECK-NEXT: kmovb  %eax, %k0
+; CHECK-NEXT: kmovw  %k0, %edi
+; CHECK-NEXT: andl  $1, %edi
+; CHECK-NEXT: movb  %dil, %al
+; CHECK-NEXT: xorl  %edi, %edi
+; CHECK-NEXT: testb  %al, %al
+; CHECK-NEXT: movl  $-1, %ecx
+; CHECK-NEXT: cmovnel  %ecx, %edi
+; CHECK-NEXT: callq  callee2
+
+declare void @callee1(i1 zeroext)
+declare void @callee2(i1 signext)
+
+attributes #0 = { nounwind "target-cpu"="skylake-avx512" }