drm/i915: use lower aux clock divider on non-ULT HSW

Workaround to avoid intermittent aux channel failures, per spec change.

v2: Don't mess with cpu dp aux divider (Paulo Zanoni)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Kill spurious tab spotted by Paulo.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 482b5e5..173add1 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -353,10 +353,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
                        aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
                else
                        aux_clock_divider = 225; /* eDP input clock at 450Mhz */
-       } else if (HAS_PCH_SPLIT(dev))
+       } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
+               /* Workaround for non-ULT HSW */
+               aux_clock_divider = 74;
+       } else if (HAS_PCH_SPLIT(dev)) {
                aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
-       else
+       } else {
                aux_clock_divider = intel_hrawclk(dev) / 2;
+       }
 
        if (IS_GEN6(dev))
                precharge = 3;