bool "Select defaults suitable for booting general purpose Linux distributions"
default y if ARCH_SUNXI || TEGRA
default y if ARCH_LS2080A
+ default y if ARCH_ROCKCHIP
default n
select CMD_BOOTZ if ARM && !ARM64
select CMD_BOOTI if ARM64
it is possible to set breakpoints on particular lines, single-step
debug through the source code, etc.
-endif
+endif # EXPERT
config PHYS_64BIT
bool "64bit physical address support"
config FIT
bool "Support Flattened Image Tree"
help
- This option allows to boot the new uImage structrure,
+ This option allows you to boot the new uImage structure,
Flattened Image Tree. FIT is formally a FDT, which can include
images of various types (kernel, FDT blob, ramdisk, etc.)
in a single blob. To boot this new uImage structure,
pass the address of the blob to the "bootm" command.
FIT is very flexible, supporting compression, multiple images,
multiple configurations, verification through hashing and also
- verified boot (secure boot using RSA). This option enables that
- feature.
+ verified boot (secure boot using RSA).
-config SPL_FIT
- bool "Support Flattened Image Tree within SPL"
- depends on FIT
- depends on SPL
-
-config FIT_VERBOSE
- bool "Display verbose messages on FIT boot"
- depends on FIT
+if FIT
config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"
- depends on FIT
depends on DM
select RSA
help
This option enables signature verification of FIT uImages,
using a hash signed and verified using RSA. If
CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
- hashing is available using hardware, then then RSA library will use
+ hashing is available using hardware, then the RSA library will use
it. See doc/uImage.FIT/signature.txt for more details.
WARNING: When relying on signed FIT images with a required signature
format support in this case, enable it using
CONFIG_IMAGE_FORMAT_LEGACY.
-config SPL_FIT_SIGNATURE
- bool "Enable signature verification of FIT firmware within SPL"
- depends on SPL_FIT
- depends on SPL_DM
- select SPL_RSA
+config FIT_VERBOSE
+ bool "Show verbose messages when FIT images fail"
+ help
+ Generally a system will have valid FIT images so debug messages
+ are a waste of code space. If you are debugging your images then
+ you can enable this option to get more verbose information about
+ failures.
config FIT_BEST_MATCH
bool "Select the best match for the kernel device tree"
- depends on FIT
help
When no configuration is explicitly selected, default to the
one whose fdt's compatibility field best matches that of
most specific compatibility entry of U-Boot's fdt's root node.
The order of entries in the configuration's fdt is ignored.
-config FIT_VERBOSE
- bool "Show verbose messages when FIT images fails"
- depends on FIT
+config FIT_IMAGE_POST_PROCESS
+ bool "Enable post-processing of FIT artifacts after loading by U-Boot"
+ depends on TI_SECURE_DEVICE
help
- Generally a system will have valid FIT images so debug messages
- are a waste of code space. If you are debugging your images then
- you can enable this option to get more verbose information about
- failures.
+ Allows doing any sort of manipulation to blobs after they got extracted
+ from FIT images like stripping off headers or modifying the size of the
+ blob, verification, authentication, decryption etc. in a platform or
+ board specific way. In order to use this feature a platform or board-
+ specific implementation of board_fit_image_post_process() must be
+ provided. Also, anything done during this post-processing step would
+ need to be comprehended in how the images were prepared before being
+ injected into the FIT creation (i.e. the blobs would have been pre-
+ processed before being added to the FIT image).
+
+config SPL_FIT
+ bool "Support Flattened Image Tree within SPL"
+ depends on SPL
+
+config SPL_FIT_SIGNATURE
+ bool "Enable signature verification of FIT firmware within SPL"
+ depends on SPL_FIT
+ depends on SPL_DM
+ select SPL_RSA
+
+config SPL_LOAD_FIT
+ bool "Enable SPL loading U-Boot as a FIT"
+ help
+ Normally with the SPL framework a legacy image is generated as part
+ of the build. This contains U-Boot along with information as to
+ where it should be loaded. This option instead enables generation
+ of a FIT (Flat Image Tree) which provides more flexibility. In
+ particular it can handle selecting from multiple device tree
+ and passing the correct one to U-Boot.
+
+config SPL_FIT_IMAGE_POST_PROCESS
+ bool "Enable post-processing of FIT artifacts after loading by the SPL"
+ depends on SPL_LOAD_FIT && TI_SECURE_DEVICE
+ help
+ Allows doing any sort of manipulation to blobs after they got extracted
+ from the U-Boot FIT image like stripping off headers or modifying the
+ size of the blob, verification, authentication, decryption etc. in a
+ platform or board specific way. In order to use this feature a platform
+ or board-specific implementation of board_fit_image_post_process() must
+ be provided. Also, anything done during this post-processing step would
+ need to be comprehended in how the images were prepared before being
+ injected into the FIT creation (i.e. the blobs would have been pre-
+ processed before being added to the FIT image).
+
+endif # FIT
config OF_BOARD_SETUP
bool "Set up board-specific details in device tree before boot"
config SYS_TEXT_BASE
depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
- (M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS
+ (M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS || \
+ ARCH_ZYNQ
depends on !EFI_APP
hex "Text Base"
help
TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
-config SPL_LOAD_FIT
- bool "Enable SPL loading U-Boot as a FIT"
- depends on FIT
- help
- Normally with the SPL framework a legacy image is generated as part
- of the build. This contains U-Boot along with information as to
- where it should be loaded. This option instead enables generation
- of a FIT (Flat Image Tree) which provides more flexibility. In
- particular it can handle selecting from multiple device tree
- and passing the correct one to U-Boot.
-
-config SPL_FIT_IMAGE_POST_PROCESS
- bool "Enable post-processing of FIT artifacts after loading by the SPL"
- depends on SPL_LOAD_FIT && TI_SECURE_DEVICE
- help
- Allows doing any sort of manipulation to blobs after they got extracted
- from the U-Boot FIT image like stripping off headers or modifying the
- size of the blob, verification, authentication, decryption etc. in a
- platform or board specific way. In order to use this feature a platform
- or board-specific implementation of board_fit_image_post_process() must
- be provided. Also, anything done during this post-processing step would
- need to be comprehended in how the images were prepared before being
- injected into the FIT creation (i.e. the blobs would have been pre-
- processed before being added to the FIT image).
-
-config FIT_IMAGE_POST_PROCESS
- bool "Enable post-processing of FIT artifacts after loading by U-Boot"
- depends on FIT && TI_SECURE_DEVICE
- help
- Allows doing any sort of manipulation to blobs after they got extracted
- from FIT images like stripping off headers or modifying the size of the
- blob, verification, authentication, decryption etc. in a platform or
- board specific way. In order to use this feature a platform or board-
- specific implementation of board_fit_image_post_process() must be
- provided. Also, anything done during this post-processing step would
- need to be comprehended in how the images were prepared before being
- injected into the FIT creation (i.e. the blobs would have been pre-
- processed before being added to the FIT image).
config SYS_CLK_FREQ
depends on ARC || ARCH_SUNXI
F: drivers/spmi/
F: include/spmi/
+TI SYSTEM SECURITY
+M: Andrew F. Davis <afd@ti.com>
+S: Supported
+F: arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
+F: arch/arm/mach-omap2/omap5/sec-fxns.c
+F: arch/arm/mach-omap2/sec-common.c
+F: arch/arm/mach-omap2/config_secure.mk
+F: configs/am43xx_hs_evm_defconfig
+F: configs/am57xx_hs_evm_defconfig
+F: configs/dra7xx_hs_evm_defconfig
+
TQ GROUP
#M: Martin Krause <martin.krause@tq-systems.de>
S: Orphaned (Since 2016-02)
VERSION = 2017
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
NAME =
# *DOCUMENTATION*
Defines the string to utilize when trying to match PCIe device
tree nodes for the given platform.
- CONFIG_SYS_PPC_E500_DEBUG_TLB
-
- Enables a temporary TLB entry to be used during boot to work
- around limitations in e500v1 and e500v2 external debugger
- support. This reduces the portions of the boot code where
- breakpoints and single stepping do not work. The value of this
- symbol should be set to the TLB1 entry to be used for this
- purpose.
-
CONFIG_SYS_FSL_ERRATUM_A004510
Enables a workaround for erratum A004510. If set,
config ARCH_MX7
bool "Freescale MX7"
select CPU_V7
+ select SYS_FSL_HAS_SEC if SECURE_BOOT
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SEC_LE
config ARCH_MX6
bool "Freescale MX6"
select CPU_V7
+ select SYS_FSL_HAS_SEC if SECURE_BOOT
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SEC_LE
config ARCH_MX5
bool "Freescale MX5"
config TARGET_S32V234EVB
bool "Support s32v234evb"
select ARM64
+ select SYS_FSL_ERRATUM_ESDHC111
config ARCH_SNAPDRAGON
bool "Qualcomm Snapdragon SoCs"
config TARGET_TS4800
bool "Support TS4800"
select CPU_V7
+ select SYS_FSL_ERRATUM_ESDHC_A001
config TARGET_VF610TWR
bool "Support vf610twr"
select CPU_V7
+ select SYS_FSL_ERRATUM_ESDHC111
config TARGET_COLIBRI_VF
bool "Support Colibri VF50/61"
select CPU_V7
+ select SYS_FSL_ERRATUM_ESDHC111
config TARGET_PCM052
bool "Support pcm-052"
select CPU_V7
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_ESDHC135
+ select SYS_FSL_ERRATUM_ESDHC_A001
config TARGET_BK4R1
bool "Support BK4r1"
select CPU_V7
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_ESDHC135
+ select SYS_FSL_ERRATUM_ESDHC_A001
config ARCH_ZYNQ
bool "Xilinx Zynq Platform"
select ARCH_LS1021A
select ARCH_SUPPORT_PSCI
select LS1_DEEP_SLEEP
+ select SYS_FSL_DDR
config TARGET_LS1021ATWR
bool "Support ls1021atwr"
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/imx-common/sys_proto.h>
-#ifdef CONFIG_MXC_MMC
+#ifdef CONFIG_MMC_MXC
#include <asm/arch/mxcmmc.h>
#endif
*/
int cpu_mmc_init(bd_t *bis)
{
-#ifdef CONFIG_MXC_MMC
+#ifdef CONFIG_MMC_MXC
return mxc_mmc_init(bis);
#else
return 0;
}
#endif /* CONFIG_FEC_MXC */
-#ifdef CONFIG_MXC_MMC
+#ifdef CONFIG_MMC_MXC
void mx27_sd1_init_pins(void)
{
int i;
imx_gpio_mode(mode[i]);
}
-#endif /* CONFIG_MXC_MMC */
+#endif /* CONFIG_MMC_MXC */
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
config ARCH_LS1021A
bool
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A008407
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
- select SYS_FSL_DDR_BE
- select SYS_FSL_DDR_VER_50
+ select SYS_FSL_DDR_BE if SYS_FSL_DDR
+ select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
+ select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
+ select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_LE
menu "LS102xA architecture"
depends on ARCH_LS1021A
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
-config NUM_DDR_CONTROLLERS
- int "Maximum DDR controllers"
- default 1
-
config SECURE_BOOT
bool "Secure Boot"
help
config SYS_HAS_SERDES
bool
-config SYS_FSL_DDR
- bool "Freescale DDR driver"
- help
- Select Freescale General DDR driver, shared between most Freescale
- PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
- based Layerscape SoCs (such as ls2080a).
-
-config SYS_FSL_DDR_BE
- bool
- default y
- help
- Access DDR registers in big-endian.
-
-config SYS_FSL_DDR_VER
- int
- default 50 if SYS_FSL_DDR_VER_50
-
-config SYS_FSL_DDR_VER_50
- bool
-
-config SYS_FSL_DDRC_ARM_GEN3
- bool
-
-config SYS_FSL_DDRC_GEN4
- bool
-
-config SYS_FSL_DDR3
- bool "Freescale DDR3 controller"
- depends on !SYS_FSL_DDR4
- select SYS_FSL_DDR
- select SYS_FSL_DDRC_ARM_GEN3
- help
- Enable Freescale DDR3 controller on ARM-based SoCs.
-
-config SYS_FSL_DDR4
- bool "Freescale DDR4 controller"
- select SYS_FSL_DDR
- select SYS_FSL_DDRC_GEN4
- help
- Enable Freescale DDR4 controller.
-
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1021A
default 8
+config SYS_FSL_ERRATUM_A008407
+ bool
+
endmenu
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
obj-$(CONFIG_ARMV8_PSCI) += psci.o
+obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
#include <asm/secure.h>
#include <linux/compiler.h>
+/*
+ * sdelay() - simple spin loop.
+ *
+ * Will delay execution by roughly (@loops * 2) cycles.
+ * This is necessary to be used before timers are accessible.
+ *
+ * A value of "0" will results in 2^64 loops.
+ */
+void sdelay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %0, #1\n"
+ "b.ne 1b" : "=r" (loops) : "0"(loops) : "cc");
+}
+
int cleanup_before_linux(void)
{
/*
config ARCH_LS1043A
bool
select FSL_LSCH2
+ select SYS_FSL_DDR
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008850
+ select SYS_FSL_ERRATUM_A009660
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009929
+ select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
config ARCH_LS1046A
bool
select FSL_LSCH2
+ select SYS_FSL_DDR
select SYS_FSL_DDR_BE
- select SYS_FSL_DDR4
select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008511
+ select SYS_FSL_ERRATUM_A009801
+ select SYS_FSL_ERRATUM_A009803
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
+ select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
config ARCH_LS2080A
bool
select FSL_LSCH3
- select SYS_FSL_DDR4
+ select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_DP_DDR
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_LE
select SYS_FSL_SRDS_2
+ select SYS_FSL_ERRATUM_A008336
+ select SYS_FSL_ERRATUM_A008511
+ select SYS_FSL_ERRATUM_A008514
+ select SYS_FSL_ERRATUM_A008585
+ select SYS_FSL_ERRATUM_A009635
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009801
+ select SYS_FSL_ERRATUM_A009803
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_A010165
config FSL_LSCH2
bool
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_BE
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
implemented under the common ARMv8 PSCI framework.
endmenu
-config SYS_FSL_MMDC
- bool
-
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
-config NUM_DDR_CONTROLLERS
- int "Maximum DDR controllers"
- default 3 if ARCH_LS2080A
- default 1
-
config SECURE_BOOT
bool
help
config SYS_HAS_SERDES
bool
-config SYS_FSL_DDR
- bool "Freescale DDR driver"
- help
- Select Freescale General DDR driver, shared between most Freescale
- PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
- based Layerscape SoCs (such as ls2080a).
+endmenu
-config SYS_FSL_DDR_BE
+config SYS_FSL_ERRATUM_A008336
bool
- help
- Access DDR registers in big-endian.
-config SYS_FSL_DDR_LE
+config SYS_FSL_ERRATUM_A008514
bool
- help
- Access DDR registers in little-endian.
-
-config SYS_FSL_DDR_VER
- int
- default 50 if SYS_FSL_DDR_VER_50
-config SYS_FSL_DDR_VER_50
+config SYS_FSL_ERRATUM_A008585
bool
-config SYS_FSL_DDRC_ARM_GEN3
+config SYS_FSL_ERRATUM_A008850
bool
-config SYS_FSL_DDRC_GEN4
+config SYS_FSL_ERRATUM_A009635
bool
-config SYS_FSL_DDR3
- bool "Freescale DDR3 controller"
- depends on !SYS_FSL_DDR4
- select SYS_FSL_DDR
- select SYS_FSL_DDRC_ARM_GEN3
- help
- Enable Freescale DDR3 controller on ARM-based SoCs.
-
-config SYS_FSL_DDR4
- bool "Freescale DDR4 controller"
- select SYS_FSL_DDR
- select SYS_FSL_DDRC_GEN4
- help
- Enable Freescale DDR4 controller.
+config SYS_FSL_ERRATUM_A009660
+ bool
-endmenu
+config SYS_FSL_ERRATUM_A009929
+ bool
--- /dev/null
+/*
+ * A lowlevel_init function that sets up the stack to call a C function to
+ * perform further init.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+ /*
+ * Setup a temporary stack. Global data is not available yet.
+ */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+ ldr w0, =CONFIG_SPL_STACK
+#else
+ ldr w0, =CONFIG_SYS_INIT_SP_ADDR
+#endif
+ bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
+
+ /*
+ * Save the old LR(passed in x29) and the current LR to stack
+ */
+ stp x29, x30, [sp, #-16]!
+
+ /*
+ * Call the very early init function. This should do only the
+ * absolute bare minimum to get started. It should not:
+ *
+ * - set up DRAM
+ * - use global_data
+ * - clear BSS
+ * - try to start a console
+ *
+ * For boards with SPL this should be empty since SPL can do all of
+ * this init in the SPL board_init_f() function which is called
+ * immediately after this.
+ */
+ bl s_init
+ ldp x29, x30, [sp]
+ ret
+ENDPROC(lowlevel_init)
.globl _start
_start:
- b reset
-
#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
/*
* Various SoCs need something special and SoC-specific up front in
* use it here.
*/
#include <asm/arch/boot0.h>
-ARM_SOC_BOOT0_HOOK
+#else
+ b reset
#endif
.align 3
/* Processor specific initialization */
bl lowlevel_init
-#if CONFIG_IS_ENABLED(ARMV8_SPIN_TABLE)
+#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
branch_if_master x0, x1, master_cpu
b spin_table_secondary_jump
/* never return */
default "zynqmp"
config SYS_VENDOR
+ string "Vendor name"
default "xilinx"
config SYS_SOC
obj-y += cpu.o
obj-$(CONFIG_MP) += mp.o
obj-y += slcr.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
--- /dev/null
+/*
+ * Copyright 2016 - 2017 Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * atfhandoffparams
+ * Parameter bitfield encoding
+ * -----------------------------------------------------------------------------
+ * Exec State 0 0 -> Aarch64, 1-> Aarch32
+ * endianness 1 0 -> LE, 1 -> BE
+ * secure (TZ) 2 0 -> Non secure, 1 -> secure
+ * EL 3:4 00 -> EL0, 01 -> EL1, 10 -> EL2, 11 -> EL3
+ * CPU# 5:6 00 -> A53_0, 01 -> A53_1, 10 -> A53_2, 11 -> A53_3
+ */
+
+#define FSBL_FLAGS_ESTATE_SHIFT 0
+#define FSBL_FLAGS_ESTATE_MASK (1 << FSBL_FLAGS_ESTATE_SHIFT)
+#define FSBL_FLAGS_ESTATE_A64 0
+#define FSBL_FLAGS_ESTATE_A32 1
+
+#define FSBL_FLAGS_ENDIAN_SHIFT 1
+#define FSBL_FLAGS_ENDIAN_MASK (1 << FSBL_FLAGS_ENDIAN_SHIFT)
+#define FSBL_FLAGS_ENDIAN_LE 0
+#define FSBL_FLAGS_ENDIAN_BE 1
+
+#define FSBL_FLAGS_TZ_SHIFT 2
+#define FSBL_FLAGS_TZ_MASK (1 << FSBL_FLAGS_TZ_SHIFT)
+#define FSBL_FLAGS_NON_SECURE 0
+#define FSBL_FLAGS_SECURE 1
+
+#define FSBL_FLAGS_EL_SHIFT 3
+#define FSBL_FLAGS_EL_MASK (3 << FSBL_FLAGS_EL_SHIFT)
+#define FSBL_FLAGS_EL0 0
+#define FSBL_FLAGS_EL1 1
+#define FSBL_FLAGS_EL2 2
+#define FSBL_FLAGS_EL3 3
+
+#define FSBL_FLAGS_CPU_SHIFT 5
+#define FSBL_FLAGS_CPU_MASK (3 << FSBL_FLAGS_CPU_SHIFT)
+#define FSBL_FLAGS_A53_0 0
+#define FSBL_FLAGS_A53_1 1
+#define FSBL_FLAGS_A53_2 2
+#define FSBL_FLAGS_A53_3 3
+
+#define FSBL_MAX_PARTITIONS 8
+
+/* Structure corresponding to each partition entry */
+struct xfsbl_partition {
+ uint64_t entry_point;
+ uint64_t flags;
+};
+
+/* Structure for handoff parameters to ARM Trusted Firmware (ATF) */
+struct xfsbl_atf_handoff_params {
+ uint8_t magic[4];
+ uint32_t num_entries;
+ struct xfsbl_partition partition[FSBL_MAX_PARTITIONS];
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+void handoff_setup(void)
+{
+ struct xfsbl_atf_handoff_params *atfhandoffparams;
+
+ atfhandoffparams = (void *)CONFIG_SPL_TEXT_BASE;
+ atfhandoffparams->magic[0] = 'X';
+ atfhandoffparams->magic[1] = 'L';
+ atfhandoffparams->magic[2] = 'N';
+ atfhandoffparams->magic[3] = 'X';
+
+ atfhandoffparams->num_entries = 1;
+ atfhandoffparams->partition[0].entry_point = CONFIG_SYS_TEXT_BASE;
+ atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 <<
+ FSBL_FLAGS_EL_SHIFT;
+
+ writel(CONFIG_SPL_TEXT_BASE, &pmu_base->gen_storage6);
+}
+#endif
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
+ handoff_setup();
+
return 0;
}
#endif
sun8i-a83t-cubietruck-plus.dtb \
sun8i-a83t-sinovoip-bpi-m3.dtb
dtb-$(CONFIG_MACH_SUN8I_H3) += \
+ sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-lite.dtb \
regulator-always-on;
vin-supply = <&vcc_io>;
};
+
+ vcc5v0_host: usb-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_vbus_drv>;
+ regulator-name = "vcc5v0_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
};
&cpu0 {
rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ usb_host {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&tsadc {
status = "okay";
};
+&usb_host1 {
+ vbus-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
&usbphy {
status = "okay";
};
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&cru SCLK_EMMC>;
assigned-clock-rates = <200000000>;
+ max-frequency = <200000000>;
clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
clock-names = "clk_xin", "clk_ahb";
phys = <&emmc_phy>;
--- /dev/null
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on sun8i-h3-orangepi-one.dts, which is:
+ * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Xunlong Orange Pi Zero";
+ compatible = "xunlong,orangepi-zero", "allwinner,sun8i-h2-plus";
+
+ aliases {
+ serial0 = &uart0;
+ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet1 = &xr819;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr_led {
+ label = "orangepi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status_led {
+ label = "orangepi:red:status";
+ gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_vcc_wifi: reg_vcc_wifi {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+ enable-active-high;
+ gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ phy = <&phy1>;
+ phy-mode = "mii";
+ allwinner,use-internal-phy;
+ allwinner,leds-active-low;
+ status = "okay";
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ vmmc-supply = <®_vcc_wifi>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ /*
+ * Explicitly define the sdio device, so that we can add an ethernet
+ * alias for it (which e.g. makes u-boot set a mac-address).
+ */
+ xr819: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ /* USB VBUS is always on */
+ status = "okay";
+};
/* USB VBUS is always on */
status = "okay";
};
+
+&emac {
+ phy = <&phy1>;
+ phy-mode = "mii";
+ allwinner,use-internal-phy;
+ allwinner,leds-active-low;
+ status = "okay";
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
i2c2 = "/i2c@7000c400";
mmc0 = "/sdhci@c8000600";
usb0 = "/usb@c5000000";
- usb1 = "/usb@c5004000"; /* on-module only, for ASIX */
+ usb1 = "/usb@c5004000"; /* On-module only, for ASIX */
usb2 = "/usb@c5008000";
};
/* EHCI instance 1: ULPI -> USB3340 -> AX88772B */
usb@c5004000 {
status = "okay";
+ /* ULPI_RESET */
+ nvidia,phy-reset-gpio =
+ <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
/* VBUS_LAN */
- nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
};
/dts-v1/;
+#include <dt-bindings/input/input.h>
#include "tegra20.dtsi"
/ {
};
aliases {
- usb0 = "/usb@c5008000";
+ rtc0 = "/i2c@7000d000/tps6586x@34";
+ rtc1 = "/rtc@7000e000";
+ serial0 = &uarta;
+ serial1 = &uartc;
+ usb0 = "/usb@c5000000";
+ usb1 = "/usb@c5004000";
+ usb2 = "/usb@c5008000";
mmc0 = "/sdhci@c8000600";
mmc1 = "/sdhci@c8000000";
};
status = "okay";
rgb {
status = "okay";
- nvidia,panel = <&lcd_panel>;
+
+ nvidia,panel = <&panel>;
+
+ display-timings {
+ timing@0 {
+ /* PAZ00 has 1024x600 */
+ clock-frequency = <54030000>;
+ hactive = <1024>;
+ vactive = <600>;
+ hback-porch = <160>;
+ hfront-porch = <24>;
+ hsync-len = <136>;
+ vback-porch = <3>;
+ vfront-porch = <61>;
+ vsync-len = <6>;
+ hsync-active = <1>;
+ };
+ };
+ };
+ };
+
+ hdmi@54280000 {
+ status = "okay";
+
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ pinmux@70000014 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ ata {
+ nvidia,pins = "ata", "atc", "atd", "ate",
+ "dap2", "gmb", "gmc", "gmd", "spia",
+ "spib", "spic", "spid", "spie";
+ nvidia,function = "gmi";
+ };
+ atb {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ };
+ cdev1 {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+ cdev2 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ };
+ crtp {
+ nvidia,pins = "crtp";
+ nvidia,function = "crt";
+ };
+ csus {
+ nvidia,pins = "csus";
+ nvidia,function = "pllc_out1";
+ };
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+ dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+ nvidia,function = "rsvd1";
+ };
+ dtf {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+ gpu {
+ nvidia,pins = "gpu", "sdb", "sdd";
+ nvidia,function = "pwm";
+ };
+ gpu7 {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+ gpv {
+ nvidia,pins = "gpv", "slxa", "slxk";
+ nvidia,function = "pcie";
+ };
+ hdint {
+ nvidia,pins = "hdint", "pta";
+ nvidia,function = "hdmi";
+ };
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ };
+ irrx {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uarta";
+ };
+ kbca {
+ nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+ kbcb {
+ nvidia,pins = "kbcb", "kbcd";
+ nvidia,function = "sdio2";
+ };
+ lcsn {
+ nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+ "ld3", "ld4", "ld5", "ld6", "ld7",
+ "ld8", "ld9", "ld10", "ld11", "ld12",
+ "ld13", "ld14", "ld15", "ld16", "ld17",
+ "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+ "lhs", "lm0", "lm1", "lpp", "lpw0",
+ "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+ "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+ "lvs";
+ nvidia,function = "displaya";
+ };
+ owc {
+ nvidia,pins = "owc";
+ nvidia,function = "owr";
+ };
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+ rm {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ };
+ sdc {
+ nvidia,pins = "sdc";
+ nvidia,function = "twc";
+ };
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+ slxc {
+ nvidia,pins = "slxc", "slxd";
+ nvidia,function = "spi4";
+ };
+ spdi {
+ nvidia,pins = "spdi", "spdo";
+ nvidia,function = "rsvd2";
+ };
+ spif {
+ nvidia,pins = "spif", "uac";
+ nvidia,function = "rsvd4";
+ };
+ spig {
+ nvidia,pins = "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+ uaa {
+ nvidia,pins = "uaa", "uab", "uda";
+ nvidia,function = "ulpi";
+ };
+ uad {
+ nvidia,pins = "uad";
+ nvidia,function = "spdif";
+ };
+ uca {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+ conf_ata {
+ nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+ "cdev1", "cdev2", "dap1", "dap2", "dtf",
+ "gma", "gmb", "gmc", "gmd", "gme",
+ "gpu", "gpu7", "gpv", "i2cp", "pta",
+ "rm", "sdio1", "slxk", "spdo", "uac",
+ "uda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_ck32 {
+ nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+ "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ };
+ conf_crtp {
+ nvidia,pins = "crtp", "dap3", "dap4", "dtb",
+ "dtc", "dte", "slxa", "slxc", "slxd",
+ "spdi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_csus {
+ nvidia,pins = "csus", "spia", "spib", "spid",
+ "spif";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_ddc {
+ nvidia,pins = "ddc", "irrx", "irtx", "kbca",
+ "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+ "spic", "spig", "uaa", "uab";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_dta {
+ nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
+ "spie", "spih", "uad", "uca", "ucb";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_hdint {
+ nvidia,pins = "hdint", "ld0", "ld1", "ld2",
+ "ld3", "ld4", "ld5", "ld6", "ld7",
+ "ld8", "ld9", "ld10", "ld11", "ld12",
+ "ld13", "ld14", "ld15", "ld16", "ld17",
+ "ldc", "ldi", "lhs", "lsc0", "lspi",
+ "lvs", "pmc";
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_lc {
+ nvidia,pins = "lc", "ls";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ };
+ conf_lcsn {
+ nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
+ "lm0", "lm1", "lpp", "lpw0", "lpw1",
+ "lpw2", "lsc1", "lsck", "lsda", "lsdi",
+ "lvp0", "lvp1", "sdb";
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_ld17_0 {
+ nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+ "ld23_22";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
};
};
};
+ i2s@70002800 {
+ status = "okay";
+ };
+
serial@70006000 {
- clock-frequency = < 216000000 >;
+ status = "okay";
+ };
+
+ serial@70006200 {
+ status = "okay";
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ lvds_ddc: i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ alc5632: alc5632@1e {
+ compatible = "realtek,alc5632";
+ reg = <0x1e>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ hdmi_ddc: i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ nvec@7000c500 {
+ compatible = "nvidia,nvec";
+ reg = <0x7000c500 0x100>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <80000>;
+ request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+ slave-addr = <138>;
+ clocks = <&tegra_car TEGRA20_CLK_I2C3>,
+ <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
+ clock-names = "div-clk", "fast-clk";
+ resets = <&tegra_car 67>;
+ reset-names = "i2c";
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&p5valw_reg>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ sys_reg: sys {
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ sm0 {
+ regulator-name = "+1.2vs_sm0,vdd_core";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ sm1 {
+ regulator-name = "+1.0vs_sm1,vdd_cpu";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ sm2_reg: sm2 {
+ regulator-name = "+3.7vs_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ /* LDO0 is not connected to anything */
+
+ ldo1 {
+ regulator-name = "+1.1vs_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ ldo2 {
+ regulator-name = "+1.2vs_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo3 {
+ regulator-name = "+3.3vs_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo4 {
+ regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo5 {
+ regulator-name = "+2.85vs_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo6 {
+ /*
+ * Research indicates this should be
+ * 1.8v; other boards that use this
+ * rail for the same purpose need it
+ * set to 1.8v. The schematic signal
+ * name is incorrect; perhaps copied
+ * from an incorrect NVIDIA reference.
+ */
+ regulator-name = "+2.85vs_ldo6,avdd_vdac";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ hdmi_vdd_reg: ldo7 {
+ regulator-name = "+3.3vs_ldo7,avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ hdmi_pll_reg: ldo8 {
+ regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo9 {
+ regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ ldo_rtc {
+ regulator-name = "+3.3vs_rtc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ adt7461@4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+ };
+
+ pmc@7000e400 {
+ nvidia,invert-interrupt;
+ nvidia,suspend-mode = <1>;
+ nvidia,cpu-pwr-good-time = <2000>;
+ nvidia,cpu-pwr-off-time = <0>;
+ nvidia,core-pwr-good-time = <3845 3845>;
+ nvidia,core-pwr-off-time = <0>;
+ nvidia,sys-clock-req-active-high;
+ };
+
+ usb@c5000000 {
+ status = "okay";
+ };
+
+ usb-phy@c5000000 {
+ status = "okay";
+ };
+
+ usb@c5004000 {
+ status = "okay";
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+ GPIO_ACTIVE_LOW>;
+ };
+
+ usb-phy@c5004000 {
+ status = "okay";
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+ GPIO_ACTIVE_LOW>;
};
usb@c5008000 {
status = "okay";
};
+ usb-phy@c5008000 {
+ status = "okay";
+ };
+
sdhci@c8000000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
non-removable;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_bl_reg>;
+ pwms = <&pwm 0 5000000>;
+
+ brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
+ default-brightness-level = <10>;
+
+ backlight-boot-off;
+ };
+
clocks {
compatible = "simple-bus";
#address-cells = <1>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
- reg=<0>;
+ reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
- pwm: pwm@7000a000 {
- status = "okay";
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
};
- lcd_panel: panel {
- /* PAZ00 has 1024x600 */
- clock = <54030000>;
- xres = <1024>;
- yres = <600>;
- right-margin = <160>;
- left-margin = <24>;
- hsync-len = <136>;
- upper-margin = <3>;
- lower-margin = <61>;
- vsync-len = <6>;
- hsync-active-high;
- nvidia,bits-per-pixel = <16>;
- nvidia,pwm = <&pwm 0 0>;
- nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(U, 4)
- GPIO_ACTIVE_HIGH>;
- nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(M, 6)
- GPIO_ACTIVE_HIGH>;
- nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
- GPIO_ACTIVE_HIGH>;
- nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(A, 4)
- GPIO_ACTIVE_HIGH>;
- nvidia,panel-timings = <400 4 203 17 15>;
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ wifi {
+ label = "wifi-led";
+ gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "rfkill0";
+ };
+ };
+
+ panel: panel {
+ compatible = "samsung,ltn101nt05", "simple-panel";
+
+ ddc-i2c-bus = <&lvds_ddc>;
+ power-supply = <&vdd_pnl_reg>;
+ enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
+
+ backlight = <&backlight>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ p5valw_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "+5valw";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vdd_pnl_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "+3VS,vdd_pnl";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_bl_reg: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-alc5632-paz00",
+ "nvidia,tegra-audio-alc5632";
+
+ nvidia,model = "Compal PAZ00";
+
+ nvidia,audio-routing =
+ "Int Spk", "SPKOUT",
+ "Int Spk", "SPKOUTN",
+ "Headset Mic", "MICBIAS1",
+ "MIC1", "Headset Mic",
+ "Headset Stereophone", "HPR",
+ "Headset Stereophone", "HPL",
+ "DMICDAT", "Digital Mic";
+
+ nvidia,audio-codec = <&alc5632>;
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+ GPIO_ACTIVE_HIGH>;
+
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
hvdd-pex-supply = <&sys_3v3_reg>;
pci@1,0 {
+ /* TS_DIFF1/2/3/4 left disabled */
nvidia,num-lanes = <4>;
};
pci@2,0 {
+ /* PCIE1_RX/TX left disabled */
nvidia,num-lanes = <1>;
};
};
emmc: sdhc@5a000000 {
- compatible = "cdns,sd4hc";
+ compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
pinctrl-names = "default";
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
- /* mmc-hs400-1_8v; support depends on board design */
};
usb0: usb@5a800100 {
};
emmc: sdhc@5a000000 {
- compatible = "cdns,sd4hc";
+ compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
pinctrl-names = "default";
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
- /* mmc-hs400-1_8v; support depends on board design */
};
sd: sdhc@5a400000 {
interrupts = <0 26 4>;
clocks = <&clkc 25>, <&clkc 34>;
clock-names = "ref_clk", "pclk";
- spi-max-frequency = <166666700>;
#address-cells = <1>;
#size-cells = <0>;
};
interrupts = <0 49 4>;
clocks = <&clkc 26>, <&clkc 35>;
clock-names = "ref_clk", "pclk";
- spi-max-frequency = <166666700>;
#address-cells = <1>;
#size-cells = <0>;
};
label = "sw14";
gpios = <&gpio0 12 0>;
linux,code = <108>; /* down */
- gpio-key,wakeup;
+ wakeup-source;
autorepeat;
};
sw13 {
label = "sw13";
gpios = <&gpio0 14 0>;
linux,code = <103>; /* up */
- gpio-key,wakeup;
+ wakeup-source;
autorepeat;
};
};
clocks = <&clk250>, <&clk250>;
};
+&watchdog0 {
+ clocks = <&clk250>;
+};
+
&xilinx_drm {
clocks = <&drm_clock>;
};
};
chosen {
+ bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+};
+
+&dwc3_0 {
+ status = "okay";
dr_mode = "host";
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
+};
+
+&dwc3_1 {
+ status = "okay";
dr_mode = "host";
};
device_type = "cpu";
enable-method = "psci";
reg = <0x0>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu@1 {
device_type = "cpu";
enable-method = "psci";
reg = <0x1>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu@2 {
device_type = "cpu";
enable-method = "psci";
reg = <0x2>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu@3 {
device_type = "cpu";
enable-method = "psci";
reg = <0x3>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ idle-states {
+ entry-mehod = "arm,psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x40000000>;
+ local-timer-stop;
+ entry-latency-us = <300>;
+ exit-latency-us = <600>;
+ min-residency-us = <800000>;
+ };
};
};
};
i2c0: i2c@ff020000 {
- compatible = "cdns,i2c-r1p10";
+ compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 17 4>;
};
i2c1: i2c@ff030000 {
- compatible = "cdns,i2c-r1p10";
+ compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 18 4>;
image_entry_noargs_t image_entry =
(image_entry_noargs_t)(unsigned long)spl_image->entry_point;
- debug("image entry point: 0x%X\n", spl_image->entry_point);
+ debug("image entry point: 0x%lX\n", spl_image->entry_point);
/* HAB looks for the CSF at the end of the authenticated data therefore,
* we need to subtract the size of the CSF from the actual filesize */
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __BOOT0_H
-#define __BOOT0_H
-
/* BOOT0 header information */
-#define ARM_SOC_BOOT0_HOOK \
- .word 0xbabeface; \
+ .word 0xbabeface
.word _end - _start
-
-#endif /* __BOOT0_H */
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __BOOT0_H
-#define __BOOT0_H
-
/* BOOT0 header information */
-#define ARM_SOC_BOOT0_HOOK \
- .word 0xbabeface; \
+ .word 0xbabeface
.word _end - _start
-
-#endif /* __BOOT0_H */
#define CONFIG_SYS_FSL_SFP_LE
#define CONFIG_SYS_FSL_SRK_LE
-/* SEC */
-#define CONFIG_SYS_FSL_SEC_LE
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
-
/* Security Monitor */
#define CONFIG_SYS_FSL_SEC_MON_LE
#define EPU_EPCTR5 0x700060a14ULL
#define EPU_EPGCR 0x700060000ULL
-#define CONFIG_SYS_FSL_ERRATUM_A008336
-#define CONFIG_SYS_FSL_ERRATUM_A008511
-#define CONFIG_SYS_FSL_ERRATUM_A008514
-#define CONFIG_SYS_FSL_ERRATUM_A008585
#define CONFIG_SYS_FSL_ERRATUM_A008751
-#define CONFIG_SYS_FSL_ERRATUM_A009635
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009801
-#define CONFIG_SYS_FSL_ERRATUM_A009803
-#define CONFIG_SYS_FSL_ERRATUM_A009942
-#define CONFIG_SYS_FSL_ERRATUM_A010165
/* ARM A57 CORE ERRATA */
#define CONFIG_ARM_ERRATA_826974
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_CCSR_GUR_BE
#define CONFIG_SYS_FSL_PEX_LUT_BE
-#define CONFIG_SYS_FSL_SEC_BE
/* SoC related */
#ifdef CONFIG_LS1043A
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
-#define CONFIG_SYS_FSL_ERRATUM_A008850
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009929
-#define CONFIG_SYS_FSL_ERRATUM_A009942
-#define CONFIG_SYS_FSL_ERRATUM_A009660
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
-#elif defined(CONFIG_ARCH_LS1012A)
-#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
+#elif defined(CONFIG_ARCH_LS1012A)
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
+
#elif defined(CONFIG_ARCH_LS1046A)
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
-#define CONFIG_SYS_FSL_ERRATUM_A008511
-#define CONFIG_SYS_FSL_ERRATUM_A009801
-#define CONFIG_SYS_FSL_ERRATUM_A009803
-#define CONFIG_SYS_FSL_ERRATUM_A009942
-#define CONFIG_SYS_FSL_ERRATUM_A010165
#else
#error SoC not defined
#endif
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_FSL_ERRATUM_A008407
#ifdef CONFIG_DDR_SPD
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_DCU_BE
#define CONFIG_SYS_FSL_SEC_MON_LE
-#define CONFIG_SYS_FSL_SEC_LE
#define CONFIG_SYS_FSL_SFP_VER_3_2
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SRK_LE
#define DCU_LAYER_MAX_NUM 16
#ifdef CONFIG_LS102XA
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_FSL_ERRATUM_A008378
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
extern void mx27_fec_init_pins(void);
#endif /* CONFIG_FEC_MXC */
-#ifdef CONFIG_MXC_MMC
+#ifdef CONFIG_MMC_MXC
extern void mx27_sd1_init_pins(void);
extern void mx27_sd2_init_pins(void);
-#endif /* CONFIG_MXC_MMC */
+#endif /* CONFIG_MMC_MXC */
/* AIPI */
struct aipi_regs {
--- /dev/null
+/*
+ * Copyright 2016 Rockchip Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_QOS_RK3288_H
+#define _ASM_ARCH_QOS_RK3288_H
+
+#define PRIORITY_HIGH_SHIFT 2
+#define PRIORITY_LOW_SHIFT 0
+
+#define CPU_AXI_QOS_PRIORITY 0x08
+
+#define VIO0_VOP_QOS 0xffad0400
+#define VIO1_VOP_QOS 0xffad0000
+#define VIO1_ISP_R_QOS 0xffad0900
+#define VIO1_ISP_W0_QOS 0xffad0100
+#define VIO1_ISP_W1_QOS 0xffad0180
+
+#endif
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __BOOT0_H
-#define __BOOT0_H
-
+#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD)
/* reserve space for BOOT0 header information */
-#define ARM_SOC_BOOT0_HOOK \
+ b reset
.space 1532
-
-#endif /* __BOOT0_H */
+#elif defined(CONFIG_ARM_BOOT_HOOK_RMR)
+/*
+ * Switch into AArch64 if needed.
+ * Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source.
+ */
+ tst x0, x0 // this is "b #0x84" in ARM
+ b reset
+ .space 0x7c
+ .word 0xe59f1024 // ldr r1, [pc, #36] ; 0x170000a0
+ .word 0xe59f0024 // ldr r0, [pc, #36] ; CONFIG_*_TEXT_BASE
+ .word 0xe5810000 // str r0, [r1]
+ .word 0xf57ff04f // dsb sy
+ .word 0xf57ff06f // isb sy
+ .word 0xee1c0f50 // mrc 15, 0, r0, cr12, cr0, {2} ; RMR
+ .word 0xe3800003 // orr r0, r0, #3
+ .word 0xee0c0f50 // mcr 15, 0, r0, cr12, cr0, {2} ; RMR
+ .word 0xf57ff06f // isb sy
+ .word 0xe320f003 // wfi
+ .word 0xeafffffd // b @wfi
+ .word 0x017000a0 // writeable RVBAR mapping address
+#ifdef CONFIG_SPL_BUILD
+ .word CONFIG_SPL_TEXT_BASE
+#else
+ .word CONFIG_SYS_TEXT_BASE
+#endif
+#else
+/* normal execution */
+ b reset
+#endif
#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8)
#define CCM_DRAMCLK_CFG_SRC_PLL5 (0x0 << 20)
#define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20)
+#define CCM_DRAMCLK_CFG_SRC_PLL11 (0x1 << 20) /* A64 only */
#define CCM_DRAMCLK_CFG_SRC_MASK (0x3 << 20)
#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
#include <asm/arch/cpu_sun4i.h>
#endif
+#define SOCID_A64 0x1689
+#define SOCID_H3 0x1680
+
#endif /* _SUNXI_CPU_H */
#include <asm/arch/dram_sun8i_a33.h>
#elif defined(CONFIG_MACH_SUN8I_A83T)
#include <asm/arch/dram_sun8i_a83t.h>
-#elif defined(CONFIG_MACH_SUN8I_H3)
+#elif defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
#include <asm/arch/dram_sun8i_h3.h>
#elif defined(CONFIG_MACH_SUN9I)
#include <asm/arch/dram_sun9i.h>
struct sunxi_mctl_com_reg {
u32 cr; /* 0x00 control register */
- u8 res0[0xc]; /* 0x04 */
+ u8 res0[0x8]; /* 0x04 */
+ u32 tmr; /* 0x0c (unused on H3) */
u32 mcr[16][2]; /* 0x10 */
u32 bwcr; /* 0x90 bandwidth control register */
u32 maer; /* 0x94 master enable register */
u32 swoffr; /* 0xc4 */
u8 res2[0x8]; /* 0xc8 */
u32 cccr; /* 0xd0 */
- u8 res3[0x72c]; /* 0xd4 */
+ u8 res3[0x54]; /* 0xd4 */
+ u32 mdfs_bwlr[3]; /* 0x128 (unused on H3) */
+ u8 res4[0x6cc]; /* 0x134 */
u32 protect; /* 0x800 */
};
u32 rfshtmg; /* 0x90 refresh timing */
u32 rfshctl1; /* 0x94 */
u32 pwrtmg; /* 0x98 */
- u8 res3[0x20]; /* 0x9c */
+ u8 res3[0x1c]; /* 0x9c */
+ u32 vtfcr; /* 0xb8 (unused on H3) */
u32 dqsgmr; /* 0xbc */
u32 dtcr; /* 0xc0 */
u32 dtar[4]; /* 0xc4 */
u32 perfhpr[2]; /* 0x1c4 */
u32 perflpr[2]; /* 0x1cc */
u32 perfwr[2]; /* 0x1d4 */
- u8 res8[0x2c]; /* 0x1dc */
- u32 aciocr; /* 0x208 */
- u8 res9[0xf4]; /* 0x20c */
+ u8 res8[0x24]; /* 0x1dc */
+ u32 acmdlr; /* 0x200 AC master delay line register */
+ u32 aclcdlr; /* 0x204 AC local calibrated delay line register */
+ u32 aciocr; /* 0x208 AC I/O configuration register */
+ u8 res9[0x4]; /* 0x20c */
+ u32 acbdlr[31]; /* 0x210 AC bit delay line registers */
+ u8 res10[0x74]; /* 0x28c */
struct { /* 0x300 DATX8 modules*/
- u32 mdlr; /* 0x00 */
- u32 lcdlr[3]; /* 0x04 */
- u32 iocr[11]; /* 0x10 IO configuration register */
- u32 bdlr6; /* 0x3c */
- u32 gtr; /* 0x40 */
- u32 gcr; /* 0x44 */
- u32 gsr[3]; /* 0x48 */
+ u32 mdlr; /* 0x00 master delay line register */
+ u32 lcdlr[3]; /* 0x04 local calibrated delay line registers */
+ u32 bdlr[12]; /* 0x10 bit delay line registers */
+ u32 gtr; /* 0x40 general timing register */
+ u32 gcr; /* 0x44 general configuration register */
+ u32 gsr[3]; /* 0x48 general status registers */
u8 res0[0x2c]; /* 0x54 */
- } datx[4];
- u8 res10[0x388]; /* 0x500 */
+ } dx[4];
+ u8 res11[0x388]; /* 0x500 */
u32 upd2; /* 0x888 */
};
#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */
-#define ZQCR_PWRDOWN (0x1 << 31) /* ZQ power down */
+#define ZQCR_PWRDOWN (1U << 31) /* ZQ power down */
-#define DATX_IOCR_DQ(x) (x) /* DQ0-7 IOCR index */
-#define DATX_IOCR_DM (8) /* DM IOCR index */
-#define DATX_IOCR_DQS (9) /* DQS IOCR index */
-#define DATX_IOCR_DQSN (10) /* DQSN IOCR index */
+#define ACBDLR_WRITE_DELAY(x) ((x) << 8)
-#define DATX_IOCR_WRITE_DELAY(x) ((x) << 8)
-#define DATX_IOCR_READ_DELAY(x) ((x) << 0)
+#define DXBDLR_DQ(x) (x) /* DQ0-7 BDLR index */
+#define DXBDLR_DM 8 /* DM BDLR index */
+#define DXBDLR_DQS 9 /* DQS BDLR index */
+#define DXBDLR_DQSN 10 /* DQSN BDLR index */
+
+#define DXBDLR_WRITE_DELAY(x) ((x) << 8)
+#define DXBDLR_READ_DELAY(x) ((x) << 0)
#endif /* _SUNXI_DRAM_SUN8I_H3_H */
#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
+#define ZYNQMP_PMU_BASEADDR 0xFFD80000
+
+struct pmu_regs {
+ u32 reserved[18];
+ u32 gen_storage6; /* 0x48 */
+};
+
+#define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
+
#endif /* _ASM_ARCH_HARDWARE_H */
#ifndef _ASM_ARCH_SYS_PROTO_H
#define _ASM_ARCH_SYS_PROTO_H
+#ifndef CONFIG_CLK_ZYNQMP
/* Setup clk for network */
static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
{
}
+#endif
int zynq_slcr_get_mio_pin_status(const char *periph);
void psu_init(void);
+void handoff_setup(void);
+
#endif /* _ASM_ARCH_SYS_PROTO_H */
#ifndef _ASM_ARMV8_MMU_H_
#define _ASM_ARMV8_MMU_H_
-#ifdef __ASSEMBLY__
-#define _AC(X, Y) X
-#else
-#define _AC(X, Y) (X##Y)
-#endif
-
-#define UL(x) _AC(x, UL)
-
/***************************************************************/
/*
* The following definitions are related each other, shoud be
#ifndef __ASM_ARM_MACH_TYPE_H
#define __ASM_ARM_MACH_TYPE_H
-#ifndef __ASSEMBLY__
-/* The type of machine we're running on */
-extern unsigned int __machine_arch_type;
-#endif
-
/* see arch/arm/kernel/arch.c for a description of these */
#define MACH_TYPE_EBSA110 0
#define MACH_TYPE_RISCPC 1
#define MACH_TYPE_LPD7A404 390
#define MACH_TYPE_CSB337 399
#define MACH_TYPE_MAINSTONE 406
+#define MACH_TYPE_LITE300 408
#define MACH_TYPE_XCEP 413
#define MACH_TYPE_ARCOM_VULCAN 414
#define MACH_TYPE_NOMADIK 420
#define MACH_TYPE_SX1 613
#define MACH_TYPE_IXDP465 618
#define MACH_TYPE_IXDP2351 619
+#define MACH_TYPE_CM4008 624
#define MACH_TYPE_IQ80332 629
#define MACH_TYPE_GTWX5715 641
#define MACH_TYPE_CSB637 648
#define MACH_TYPE_N30 656
#define MACH_TYPE_NEC_MP900 659
#define MACH_TYPE_KAFA 662
+#define MACH_TYPE_CM41XX 672
#define MACH_TYPE_TS72XX 673
#define MACH_TYPE_OTOM 680
#define MACH_TYPE_NEXCODER_2440 681
#define MACH_TYPE_GATEWAY7001 731
#define MACH_TYPE_PCM027 732
#define MACH_TYPE_ANUBIS 734
+#define MACH_TYPE_XBOARDGP8 742
#define MACH_TYPE_AKITA 744
#define MACH_TYPE_E330 753
#define MACH_TYPE_NOKIA770 755
#define MACH_TYPE_INTELMOTE2 775
#define MACH_TYPE_TRIZEPS4 776
#define MACH_TYPE_PNX4008 782
+#define MACH_TYPE_CPUAT91 787
#define MACH_TYPE_IQ81340SC 799
#define MACH_TYPE_IQ81340MC 801
+#define MACH_TYPE_SE4200 809
#define MACH_TYPE_MICRO9 811
#define MACH_TYPE_MICRO9L 812
#define MACH_TYPE_OMAP_PALMTE 817
#define MACH_TYPE_AMS_DELTA 862
#define MACH_TYPE_NAS100D 865
#define MACH_TYPE_MAGICIAN 875
+#define MACH_TYPE_CM4002 876
#define MACH_TYPE_NXDKN 880
#define MACH_TYPE_PALMTX 885
#define MACH_TYPE_S3C2413 887
#define MACH_TYPE_DAVINCI_EVM 901
#define MACH_TYPE_PALMZ72 904
#define MACH_TYPE_NXDB500 905
+#define MACH_TYPE_APF9328 906
#define MACH_TYPE_PALMT5 917
#define MACH_TYPE_PALMTC 918
#define MACH_TYPE_OMAP_APOLLON 919
#define MACH_TYPE_SMDK2412 1009
#define MACH_TYPE_SMDK2413 1022
#define MACH_TYPE_AML_M5900 1024
+#define MACH_TYPE_BALLOON3 1029
#define MACH_TYPE_ECBAT91 1072
#define MACH_TYPE_ONEARM 1075
#define MACH_TYPE_SMDK2443 1084
#define MACH_TYPE_AT91SAM9260EK 1099
#define MACH_TYPE_GLANTANK 1100
#define MACH_TYPE_N2100 1101
+#define MACH_TYPE_IM42XX 1105
#define MACH_TYPE_QT2410 1108
#define MACH_TYPE_KIXRP435 1109
#define MACH_TYPE_CC9P9360DEV 1114
#define MACH_TYPE_MIOA701 1257
#define MACH_TYPE_ARMADILLO5X0 1260
#define MACH_TYPE_CC9P9360JS 1264
+#define MACH_TYPE_SMDK6400 1270
#define MACH_TYPE_NOKIA_N800 1271
#define MACH_TYPE_EP80219 1281
#define MACH_TYPE_GORAMO_MLR 1292
#define MACH_TYPE_DAVINCI_DM6467_EVM 1380
#define MACH_TYPE_DAVINCI_DM355_EVM 1381
#define MACH_TYPE_LITTLETON 1388
+#define MACH_TYPE_IM4004 1400
#define MACH_TYPE_REALVIEW_PB11MP 1407
#define MACH_TYPE_MX27_3DS 1430
#define MACH_TYPE_HALIBUT 1439
#define MACH_TYPE_OMAP3_BEAGLE 1546
#define MACH_TYPE_NOKIA_N810 1548
#define MACH_TYPE_PCM038 1551
+#define MACH_TYPE_SG310 1564
#define MACH_TYPE_TS209 1565
#define MACH_TYPE_AT91CAP9ADK 1566
#define MACH_TYPE_MX31MOBOARD 1574
+#define MACH_TYPE_VISION_EP9307 1578
#define MACH_TYPE_TERASTATION_PRO2 1584
#define MACH_TYPE_LINKSTATION_PRO 1585
#define MACH_TYPE_E350 1596
#define MACH_TYPE_TS409 1601
+#define MACH_TYPE_RSI_EWS 1609
#define MACH_TYPE_CM_X300 1616
#define MACH_TYPE_AT91SAM9G20EK 1624
#define MACH_TYPE_SMDK6410 1626
#define MACH_TYPE_TRIZEPS4WL 1649
#define MACH_TYPE_TS78XX 1652
#define MACH_TYPE_SFFSDR 1657
-#define MACH_TYPE_SMARTWEB 1668
#define MACH_TYPE_PCM037 1673
#define MACH_TYPE_DB88F6281_BP 1680
#define MACH_TYPE_RD88F6192_NAS 1681
#define MACH_TYPE_MX25_3DS 1771
#define MACH_TYPE_OMAP3530_LV_SOM 1773
#define MACH_TYPE_DAVINCI_DA830_EVM 1781
-#define MACH_TYPE_AT572D940HFEB 1783
#define MACH_TYPE_DOVE_DB 1788
#define MACH_TYPE_OVERO 1798
#define MACH_TYPE_AT2440EVB 1799
#define MACH_TYPE_TAVOREVB 1827
#define MACH_TYPE_SAAR 1828
#define MACH_TYPE_AT91SAM9M10G45EK 1830
+#define MACH_TYPE_USB_A9G20 1841
#define MACH_TYPE_MXLADS 1851
#define MACH_TYPE_LINKSTATION_MINI 1858
#define MACH_TYPE_AFEB9260 1859
#define MACH_TYPE_AT91SAM9G10EK 2159
#define MACH_TYPE_OMAP_4430SDP 2160
#define MACH_TYPE_MAGX_ZN5 2162
-#define MACH_TYPE_BTMAVB101 2172
-#define MACH_TYPE_BTMAWB101 2173
#define MACH_TYPE_OMAP3_TORPEDO 2178
#define MACH_TYPE_ANW6410 2183
#define MACH_TYPE_IMX27_VISSTRIM_M10 2187
#define MACH_TYPE_PORTUXG20 2191
#define MACH_TYPE_SMDKC110 2193
+#define MACH_TYPE_CABESPRESSO 2194
#define MACH_TYPE_OMAP3517EVM 2200
#define MACH_TYPE_NETSPACE_V2 2201
#define MACH_TYPE_NETSPACE_MAX_V2 2202
#define MACH_TYPE_NET5BIG_V2 2206
#define MACH_TYPE_INETSPACE_V2 2208
#define MACH_TYPE_AT91SAM9G45EKES 2212
-#define MACH_TYPE_PC7302 2220
#define MACH_TYPE_SPEAR600 2236
#define MACH_TYPE_SPEAR300 2237
#define MACH_TYPE_LILLY1131 2239
#define MACH_TYPE_BIGDISK 2283
#define MACH_TYPE_AT91SAM9G20EK_2MMC 2288
#define MACH_TYPE_BCMRING 2289
-#define MACH_TYPE_DP6XX 2302
#define MACH_TYPE_MAHIMAHI 2304
+#define MACH_TYPE_CEREBRIC 2311
#define MACH_TYPE_SMDK6442 2324
#define MACH_TYPE_OPENRD_BASE 2325
#define MACH_TYPE_DEVKIT8000 2330
#define MACH_TYPE_IGEP0020 2344
#define MACH_TYPE_NUC932EVB 2356
#define MACH_TYPE_OPENRD_CLIENT 2361
+#define MACH_TYPE_U8500 2368
#define MACH_TYPE_MX51_EFIKASB 2370
#define MACH_TYPE_MARVELL_JASPER 2382
#define MACH_TYPE_FLINT 2383
#define MACH_TYPE_SMDKV210 2456
#define MACH_TYPE_OMAP_ZOOM3 2464
#define MACH_TYPE_OMAP_3630SDP 2465
+#define MACH_TYPE_CYBOOK2440 2466
#define MACH_TYPE_SMARTQ7 2479
#define MACH_TYPE_WATSON_EFM_PLUGIN 2491
#define MACH_TYPE_G4EVM 2493
#define MACH_TYPE_SMARTQ5 2534
#define MACH_TYPE_DAVINCI_DM6467TEVM 2548
#define MACH_TYPE_MXT_TD60 2550
-#define MACH_TYPE_RIOT_BEI2 2576
-#define MACH_TYPE_RIOT_X37 2578
#define MACH_TYPE_CAPC7117 2612
#define MACH_TYPE_ICONTROL 2624
+#define MACH_TYPE_GPLUGD 2625
#define MACH_TYPE_QSD8X50A_ST1_5 2627
#define MACH_TYPE_MX23EVK 2629
#define MACH_TYPE_AP4EVB 2630
#define MACH_TYPE_AQUILA 2676
#define MACH_TYPE_ESATA_SHEEVAPLUG 2678
#define MACH_TYPE_MSM7X30_SURF 2679
-#define MACH_TYPE_EA2478DEVKIT 2683
#define MACH_TYPE_TERASTATION_WXL 2697
#define MACH_TYPE_MSM7X25_SURF 2703
#define MACH_TYPE_MSM7X25_FFA 2704
#define MACH_TYPE_SBC3530 2722
#define MACH_TYPE_SAARB 2727
#define MACH_TYPE_HARMONY 2731
+#define MACH_TYPE_CYBOOK_ORIZON 2733
#define MACH_TYPE_MSM7X30_FLUID 2741
#define MACH_TYPE_CM_T3517 2750
#define MACH_TYPE_WBD222 2753
#define MACH_TYPE_MSM8X60_SURF 2755
#define MACH_TYPE_MSM8X60_SIM 2756
#define MACH_TYPE_TCC8000_SDK 2758
-#define MACH_TYPE_NANOS 2759
-#define MACH_TYPE_STAMP9G45 2761
#define MACH_TYPE_CNS3420VB 2776
#define MACH_TYPE_OMAP4_PANDA 2791
#define MACH_TYPE_TI8168EVM 2800
#define MACH_TYPE_EUKREA_CPUIMX51SD 2822
#define MACH_TYPE_EUKREA_CPUIMX51 2823
#define MACH_TYPE_SMDKC210 2838
-#define MACH_TYPE_OMAP3_BRAILLO 2839
-#define MACH_TYPE_SPYPLUG 2840
-#define MACH_TYPE_GINGER 2841
-#define MACH_TYPE_TNY_T3530 2842
-#define MACH_TYPE_PCA102 2843
-#define MACH_TYPE_SPADE 2844
-#define MACH_TYPE_MXC25_TOPAZ 2845
#define MACH_TYPE_T5325 2846
-#define MACH_TYPE_GW2361 2847
-#define MACH_TYPE_ELOG 2848
#define MACH_TYPE_INCOME 2849
-#define MACH_TYPE_BCM589X 2850
-#define MACH_TYPE_ETNA 2851
-#define MACH_TYPE_HAWKS 2852
-#define MACH_TYPE_MESON 2853
-#define MACH_TYPE_XSBASE255 2854
-#define MACH_TYPE_PVM2030 2855
-#define MACH_TYPE_MIOA502 2856
-#define MACH_TYPE_VVBOX_SDORIG2 2857
-#define MACH_TYPE_VVBOX_SDLITE2 2858
-#define MACH_TYPE_VVBOX_SDPRO4 2859
-#define MACH_TYPE_HTC_SPV_M700 2860
-#define MACH_TYPE_MX257SX 2861
#define MACH_TYPE_GONI 2862
-#define MACH_TYPE_MSM8X55_SVLTE_FFA 2863
-#define MACH_TYPE_MSM8X55_SVLTE_SURF 2864
-#define MACH_TYPE_QUICKSTEP 2865
-#define MACH_TYPE_DMW96 2866
-#define MACH_TYPE_HAMMERHEAD 2867
-#define MACH_TYPE_TRIDENT 2868
-#define MACH_TYPE_LIGHTNING 2869
-#define MACH_TYPE_ICONNECT 2870
-#define MACH_TYPE_AUTOBOT 2871
-#define MACH_TYPE_COCONUT 2872
-#define MACH_TYPE_DURIAN 2873
-#define MACH_TYPE_CAYENNE 2874
-#define MACH_TYPE_FUJI 2875
-#define MACH_TYPE_SYNOLOGY_6282 2876
-#define MACH_TYPE_EM1SY 2877
-#define MACH_TYPE_M502 2878
-#define MACH_TYPE_MATRIX518 2879
-#define MACH_TYPE_TINY_GURNARD 2880
-#define MACH_TYPE_SPEAR1310 2881
#define MACH_TYPE_BV07 2882
-#define MACH_TYPE_MXT_TD61 2883
#define MACH_TYPE_OPENRD_ULTIMATE 2884
#define MACH_TYPE_DEVIXP 2885
#define MACH_TYPE_MICCPT 2886
#define MACH_TYPE_MIC256 2887
-#define MACH_TYPE_AS1167 2888
-#define MACH_TYPE_OMAP3_IBIZA 2889
#define MACH_TYPE_U5500 2890
-#define MACH_TYPE_DAVINCI_PICTO 2891
-#define MACH_TYPE_MECHA 2892
-#define MACH_TYPE_BUBBA3 2893
-#define MACH_TYPE_PUPITRE 2894
-#define MACH_TYPE_TEGRA_VOGUE 2896
-#define MACH_TYPE_TEGRA_E1165 2897
-#define MACH_TYPE_SIMPLENET 2898
-#define MACH_TYPE_EC4350TBM 2899
-#define MACH_TYPE_PEC_TC 2900
-#define MACH_TYPE_PEC_HC2 2901
-#define MACH_TYPE_ESL_MOBILIS_A 2902
-#define MACH_TYPE_ESL_MOBILIS_B 2903
-#define MACH_TYPE_ESL_WAVE_A 2904
-#define MACH_TYPE_ESL_WAVE_B 2905
-#define MACH_TYPE_UNISENSE_MMM 2906
-#define MACH_TYPE_BLUESHARK 2907
-#define MACH_TYPE_E10 2908
-#define MACH_TYPE_APP3K_ROBIN 2909
-#define MACH_TYPE_POV15HD 2910
-#define MACH_TYPE_STELLA 2911
#define MACH_TYPE_LINKSTATION_LSCHL 2913
-#define MACH_TYPE_NETWALKER 2914
-#define MACH_TYPE_ACSX106 2915
-#define MACH_TYPE_ATLAS5_C1 2916
-#define MACH_TYPE_NSB3AST 2917
-#define MACH_TYPE_GNET_SLC 2918
-#define MACH_TYPE_AF4000 2919
-#define MACH_TYPE_ARK9431 2920
-#define MACH_TYPE_FS_S5PC100 2921
-#define MACH_TYPE_OMAP3505NOVA8 2922
-#define MACH_TYPE_OMAP3621_EDP1 2923
-#define MACH_TYPE_ORATISAES 2924
#define MACH_TYPE_SMDKV310 2925
-#define MACH_TYPE_SIEMENS_L0 2926
-#define MACH_TYPE_VENTANA 2927
#define MACH_TYPE_WM8505_7IN_NETBOOK 2928
-#define MACH_TYPE_EC4350SDB 2929
-#define MACH_TYPE_MIMAS 2930
-#define MACH_TYPE_TITAN 2931
#define MACH_TYPE_CRANEBOARD 2932
-#define MACH_TYPE_ES2440 2933
-#define MACH_TYPE_NAJAY_A9263 2934
-#define MACH_TYPE_HTCTORNADO 2935
-#define MACH_TYPE_DIMM_MX257 2936
-#define MACH_TYPE_JIGEN 2937
#define MACH_TYPE_SMDK6450 2938
-#define MACH_TYPE_MENO_QNG 2939
-#define MACH_TYPE_NS2416 2940
-#define MACH_TYPE_RPC353 2941
-#define MACH_TYPE_TQ6410 2942
-#define MACH_TYPE_SKY6410 2943
-#define MACH_TYPE_DYNASTY 2944
-#define MACH_TYPE_VIVO 2945
-#define MACH_TYPE_BURY_BL7582 2946
-#define MACH_TYPE_BURY_BPS5270 2947
-#define MACH_TYPE_BASI 2948
-#define MACH_TYPE_TN200 2949
-#define MACH_TYPE_C2MMI 2950
-#define MACH_TYPE_MESON_6236M 2951
-#define MACH_TYPE_MESON_8626M 2952
-#define MACH_TYPE_TUBE 2953
-#define MACH_TYPE_MESSINA 2954
-#define MACH_TYPE_MX50_ARM2 2955
-#define MACH_TYPE_CETUS9263 2956
#define MACH_TYPE_BROWNSTONE 2957
-#define MACH_TYPE_VMX25 2958
-#define MACH_TYPE_VMX51 2959
-#define MACH_TYPE_ABACUS 2960
-#define MACH_TYPE_CM4745 2961
-#define MACH_TYPE_ORATISLINK 2962
-#define MACH_TYPE_DAVINCI_DM365_DVR 2963
-#define MACH_TYPE_NETVIZ 2964
#define MACH_TYPE_FLEXIBITY 2965
-#define MACH_TYPE_WLAN_COMPUTER 2966
-#define MACH_TYPE_LPC24XX 2967
-#define MACH_TYPE_SPICA 2968
-#define MACH_TYPE_GPSDISPLAY 2969
-#define MACH_TYPE_BIPNET 2970
-#define MACH_TYPE_OVERO_CTU_INERTIAL 2971
-#define MACH_TYPE_DAVINCI_DM355_MMM 2972
-#define MACH_TYPE_PC9260_V2 2973
-#define MACH_TYPE_PTX7545 2974
-#define MACH_TYPE_TM_EFDC 2975
-#define MACH_TYPE_OMAP3_WALDO1 2977
-#define MACH_TYPE_FLYER 2978
-#define MACH_TYPE_TORNADO3240 2979
-#define MACH_TYPE_SOLI_01 2980
-#define MACH_TYPE_OMAPL138_EUROPALC 2981
-#define MACH_TYPE_HELIOS_V1 2982
-#define MACH_TYPE_NETSPACE_LITE_V2 2983
-#define MACH_TYPE_SSC 2984
-#define MACH_TYPE_PREMIERWAVE_EN 2985
-#define MACH_TYPE_WASABI 2986
#define MACH_TYPE_MX50_RDP 2988
#define MACH_TYPE_UNIVERSAL_C210 2989
#define MACH_TYPE_REAL6410 2990
-#define MACH_TYPE_SPX_SAKURA 2991
-#define MACH_TYPE_IJ3K_2440 2992
-#define MACH_TYPE_OMAP3_BC10 2993
-#define MACH_TYPE_THEBE 2994
-#define MACH_TYPE_RV082 2995
-#define MACH_TYPE_ARMLGUEST 2996
-#define MACH_TYPE_TJINC1000 2997
#define MACH_TYPE_DOCKSTAR 2998
-#define MACH_TYPE_AX8008 2999
-#define MACH_TYPE_GNET_SGCE 3000
-#define MACH_TYPE_PXWNAS_500_1000 3001
-#define MACH_TYPE_EA20 3002
-#define MACH_TYPE_AWM2 3003
#define MACH_TYPE_TI8148EVM 3004
#define MACH_TYPE_SEABOARD 3005
-#define MACH_TYPE_LINKSTATION_CHLV2 3006
-#define MACH_TYPE_TERA_PRO2_RACK 3007
-#define MACH_TYPE_RUBYS 3008
-#define MACH_TYPE_AQUARIUS 3009
#define MACH_TYPE_MX53_ARD 3010
#define MACH_TYPE_MX53_SMD 3011
-#define MACH_TYPE_LSWXL 3012
-#define MACH_TYPE_DOVE_AVNG_V3 3013
-#define MACH_TYPE_SDI_ESS_9263 3014
-#define MACH_TYPE_JOCPU550 3015
#define MACH_TYPE_MSM8X60_RUMI3 3016
#define MACH_TYPE_MSM8X60_FFA 3017
-#define MACH_TYPE_YANOMAMI 3018
-#define MACH_TYPE_GTA04 3019
#define MACH_TYPE_CM_A510 3020
-#define MACH_TYPE_OMAP3_RFS200 3021
-#define MACH_TYPE_KX33XX 3022
-#define MACH_TYPE_PTX7510 3023
-#define MACH_TYPE_TOP9000 3024
-#define MACH_TYPE_TEENOTE 3025
-#define MACH_TYPE_TS3 3026
-#define MACH_TYPE_A0 3027
-#define MACH_TYPE_FSM9XXX_SURF 3028
-#define MACH_TYPE_FSM9XXX_FFA 3029
-#define MACH_TYPE_FRRHWCDMA60W 3030
-#define MACH_TYPE_REMUS 3031
-#define MACH_TYPE_AT91CAP7XDK 3032
-#define MACH_TYPE_AT91CAP7STK 3033
-#define MACH_TYPE_KT_SBC_SAM9_1 3034
-#define MACH_TYPE_ARMADA_XP_DB 3036
-#define MACH_TYPE_SPDM 3037
-#define MACH_TYPE_GTIB 3038
-#define MACH_TYPE_DGM3240 3039
-#define MACH_TYPE_HTCMEGA 3041
-#define MACH_TYPE_TRICORDER 3042
#define MACH_TYPE_TX28 3043
-#define MACH_TYPE_BSTBRD 3044
-#define MACH_TYPE_PWB3090 3045
-#define MACH_TYPE_IDEA6410 3046
-#define MACH_TYPE_QBC9263 3047
-#define MACH_TYPE_BORABORA 3048
-#define MACH_TYPE_VALDEZ 3049
-#define MACH_TYPE_LS9G20 3050
-#define MACH_TYPE_MIOS_V1 3051
-#define MACH_TYPE_S5PC110_CRESPO 3052
-#define MACH_TYPE_CONTROLTEK9G20 3053
-#define MACH_TYPE_TIN307 3054
-#define MACH_TYPE_TIN510 3055
-#define MACH_TYPE_BLUECHEESE 3057
-#define MACH_TYPE_TEM3X30 3058
-#define MACH_TYPE_HARVEST_DESOTO 3059
-#define MACH_TYPE_MSM8X60_QRDC 3060
-#define MACH_TYPE_SPEAR900 3061
#define MACH_TYPE_PCONTROL_G20 3062
-#define MACH_TYPE_RDSTOR 3063
-#define MACH_TYPE_USDLOADER 3064
-#define MACH_TYPE_TSOPLOADER 3065
-#define MACH_TYPE_KRONOS 3066
-#define MACH_TYPE_FFCORE 3067
-#define MACH_TYPE_MONE 3068
-#define MACH_TYPE_UNIT2S 3069
-#define MACH_TYPE_ACER_A5 3070
-#define MACH_TYPE_ETHERPRO_ISP 3071
-#define MACH_TYPE_STRETCHS7000 3072
-#define MACH_TYPE_P87_SMARTSIM 3073
-#define MACH_TYPE_TULIP 3074
-#define MACH_TYPE_SUNFLOWER 3075
-#define MACH_TYPE_RIB 3076
-#define MACH_TYPE_CLOD 3077
-#define MACH_TYPE_RUMP 3078
-#define MACH_TYPE_TENDERLOIN 3079
-#define MACH_TYPE_SHORTLOIN 3080
-#define MACH_TYPE_ANTARES 3082
-#define MACH_TYPE_WB40N 3083
-#define MACH_TYPE_HERRING 3084
-#define MACH_TYPE_NAXY400 3085
-#define MACH_TYPE_NAXY1200 3086
#define MACH_TYPE_VPR200 3087
-#define MACH_TYPE_BUG20 3088
-#define MACH_TYPE_GOFLEXNET 3089
#define MACH_TYPE_TORBRECK 3090
-#define MACH_TYPE_SAARB_MG1 3091
-#define MACH_TYPE_CALLISTO 3092
-#define MACH_TYPE_MULTHSU 3093
-#define MACH_TYPE_SALUDA 3094
-#define MACH_TYPE_PEMP_OMAP3_APOLLO 3095
-#define MACH_TYPE_VC0718 3096
-#define MACH_TYPE_MVBLX 3097
-#define MACH_TYPE_INHAND_APEIRON 3098
-#define MACH_TYPE_INHAND_FURY 3099
-#define MACH_TYPE_INHAND_SIREN 3100
-#define MACH_TYPE_HDNVP 3101
-#define MACH_TYPE_SOFTWINNER 3102
#define MACH_TYPE_PRIMA2_EVB 3103
-#define MACH_TYPE_NAS6210 3104
-#define MACH_TYPE_UNISDEV 3105
-#define MACH_TYPE_SBCA11 3106
-#define MACH_TYPE_SAGA 3107
-#define MACH_TYPE_NS_K330 3108
-#define MACH_TYPE_TANNA 3109
-#define MACH_TYPE_IMATE8502 3110
-#define MACH_TYPE_ASPEN 3111
-#define MACH_TYPE_DAINTREE_CWAC 3112
-#define MACH_TYPE_ZMX25 3113
-#define MACH_TYPE_MAPLE1 3114
-#define MACH_TYPE_QSD8X72_SURF 3115
-#define MACH_TYPE_QSD8X72_FFA 3116
-#define MACH_TYPE_ABILENE 3117
-#define MACH_TYPE_EIGEN_TTR 3118
-#define MACH_TYPE_IOMEGA_IX2_200 3119
-#define MACH_TYPE_CORETEC_VCX7400 3120
-#define MACH_TYPE_SANTIAGO 3121
-#define MACH_TYPE_MX257SOL 3122
-#define MACH_TYPE_STRASBOURG 3123
-#define MACH_TYPE_MSM8X60_FLUID 3124
-#define MACH_TYPE_SMARTQV5 3125
-#define MACH_TYPE_SMARTQV3 3126
-#define MACH_TYPE_SMARTQV7 3127
#define MACH_TYPE_PAZ00 3128
#define MACH_TYPE_ACMENETUSFOXG20 3129
-#define MACH_TYPE_FWBD_0404 3131
-#define MACH_TYPE_HDGU 3132
-#define MACH_TYPE_PYRAMID 3133
-#define MACH_TYPE_EPIPHAN 3134
-#define MACH_TYPE_OMAP_BENDER 3135
-#define MACH_TYPE_GURNARD 3136
-#define MACH_TYPE_GTL_IT5100 3137
-#define MACH_TYPE_BCM2708 3138
-#define MACH_TYPE_MX51_GGC 3139
-#define MACH_TYPE_SHARESPACE 3140
-#define MACH_TYPE_HABA_KNX_EXPLORER 3141
-#define MACH_TYPE_SIMTEC_KIRKMOD 3142
-#define MACH_TYPE_CRUX 3143
-#define MACH_TYPE_MX51_BRAVO 3144
-#define MACH_TYPE_CHARON 3145
-#define MACH_TYPE_PICOCOM3 3146
-#define MACH_TYPE_PICOCOM4 3147
-#define MACH_TYPE_SERRANO 3148
-#define MACH_TYPE_DOUBLESHOT 3149
-#define MACH_TYPE_EVSY 3150
-#define MACH_TYPE_HUASHAN 3151
-#define MACH_TYPE_LAUSANNE 3152
-#define MACH_TYPE_EMERALD 3153
-#define MACH_TYPE_TQMA35 3154
-#define MACH_TYPE_MARVEL 3155
-#define MACH_TYPE_MANUAE 3156
-#define MACH_TYPE_CHACHA 3157
-#define MACH_TYPE_LEMON 3158
-#define MACH_TYPE_CSC 3159
-#define MACH_TYPE_GIRA_KNXIP_ROUTER 3160
-#define MACH_TYPE_T20 3161
-#define MACH_TYPE_HDMINI 3162
-#define MACH_TYPE_SCIPHONE_G2 3163
-#define MACH_TYPE_EXPRESS 3164
-#define MACH_TYPE_EXPRESS_KT 3165
-#define MACH_TYPE_MAXIMASP 3166
-#define MACH_TYPE_NITROGEN_IMX51 3167
-#define MACH_TYPE_NITROGEN_IMX53 3168
-#define MACH_TYPE_SUNFIRE 3169
-#define MACH_TYPE_AROWANA 3170
-#define MACH_TYPE_TEGRA_DAYTONA 3171
-#define MACH_TYPE_TEGRA_SWORDFISH 3172
-#define MACH_TYPE_EDISON 3173
-#define MACH_TYPE_SVP8500V1 3174
-#define MACH_TYPE_SVP8500V2 3175
-#define MACH_TYPE_SVP5500 3176
-#define MACH_TYPE_B5500 3177
-#define MACH_TYPE_S5500 3178
-#define MACH_TYPE_ICON 3179
-#define MACH_TYPE_ELEPHANT 3180
-#define MACH_TYPE_SHOOTER 3182
-#define MACH_TYPE_SPADE_LTE 3183
-#define MACH_TYPE_PHILHWANI 3184
-#define MACH_TYPE_GSNCOMM 3185
-#define MACH_TYPE_STRASBOURG_A2 3186
-#define MACH_TYPE_MMM 3187
-#define MACH_TYPE_DAVINCI_DM365_BV 3188
#define MACH_TYPE_AG5EVM 3189
-#define MACH_TYPE_SC575PLC 3190
-#define MACH_TYPE_SC575IPC 3191
-#define MACH_TYPE_OMAP3_TDM3730 3192
-#define MACH_TYPE_TOP9000_EVAL 3194
-#define MACH_TYPE_TOP9000_SU 3195
-#define MACH_TYPE_UTM300 3196
-#define MACH_TYPE_TSUNAGI 3197
-#define MACH_TYPE_TS75XX 3198
-#define MACH_TYPE_TS47XX 3200
-#define MACH_TYPE_DA850_K5 3201
-#define MACH_TYPE_AX502 3202
-#define MACH_TYPE_IGEP0032 3203
-#define MACH_TYPE_ANTERO 3204
-#define MACH_TYPE_SYNERGY 3205
#define MACH_TYPE_ICS_IF_VOIP 3206
#define MACH_TYPE_WLF_CRAGG_6410 3207
-#define MACH_TYPE_PUNICA 3208
#define MACH_TYPE_TRIMSLICE 3209
-#define MACH_TYPE_MX27_WMULTRA 3210
-#define MACH_TYPE_MACKEREL 3211
-#define MACH_TYPE_FA9X27 3213
-#define MACH_TYPE_NS2816TB 3214
-#define MACH_TYPE_NS2816_NTPAD 3215
-#define MACH_TYPE_NS2816_NTNB 3216
#define MACH_TYPE_KAEN 3217
-#define MACH_TYPE_NV1000 3218
-#define MACH_TYPE_NUC950TS 3219
#define MACH_TYPE_NOKIA_RM680 3220
-#define MACH_TYPE_AST2200 3221
-#define MACH_TYPE_LEAD 3222
-#define MACH_TYPE_UNINO1 3223
-#define MACH_TYPE_GREECO 3224
-#define MACH_TYPE_VERDI 3225
-#define MACH_TYPE_DM6446_ADBOX 3226
-#define MACH_TYPE_QUAD_SALSA 3227
-#define MACH_TYPE_ABB_GMA_1_1 3228
-#define MACH_TYPE_SVCID 3229
#define MACH_TYPE_MSM8960_SIM 3230
#define MACH_TYPE_MSM8960_RUMI3 3231
-#define MACH_TYPE_ICON_G 3232
-#define MACH_TYPE_MB3 3233
#define MACH_TYPE_GSIA18S 3234
-#define MACH_TYPE_PIVICC 3235
-#define MACH_TYPE_PCM048 3236
-#define MACH_TYPE_DDS 3237
-#define MACH_TYPE_CHALTEN_XA1 3238
-#define MACH_TYPE_TS48XX 3239
-#define MACH_TYPE_TONGA2_TFTTIMER 3240
-#define MACH_TYPE_WHISTLER 3241
-#define MACH_TYPE_ASL_PHOENIX 3242
-#define MACH_TYPE_AT91SAM9263OTLITE 3243
-#define MACH_TYPE_DDPLUG 3244
-#define MACH_TYPE_D2PLUG 3245
-#define MACH_TYPE_KZM9D 3246
-#define MACH_TYPE_VERDI_LTE 3247
-#define MACH_TYPE_NANOZOOM 3248
-#define MACH_TYPE_DM3730_SOM_LV 3249
-#define MACH_TYPE_DM3730_TORPEDO 3250
-#define MACH_TYPE_ANCHOVY 3251
-#define MACH_TYPE_RE2REV20 3253
-#define MACH_TYPE_RE2REV21 3254
-#define MACH_TYPE_CNS21XX 3255
-#define MACH_TYPE_RIDER 3257
-#define MACH_TYPE_NSK330 3258
-#define MACH_TYPE_CNS2133EVB 3259
-#define MACH_TYPE_Z3_816X_MOD 3260
-#define MACH_TYPE_Z3_814X_MOD 3261
-#define MACH_TYPE_BEECT 3262
-#define MACH_TYPE_DMA_THUNDERBUG 3263
-#define MACH_TYPE_OMN_AT91SAM9G20 3264
-#define MACH_TYPE_MX25_E2S_UC 3265
-#define MACH_TYPE_MIONE 3266
-#define MACH_TYPE_TOP9000_TCU 3267
-#define MACH_TYPE_TOP9000_BSL 3268
-#define MACH_TYPE_KINGDOM 3269
-#define MACH_TYPE_ARMADILLO460 3270
-#define MACH_TYPE_LQ2 3271
-#define MACH_TYPE_SWEDA_TMS2 3272
#define MACH_TYPE_MX53_LOCO 3273
-#define MACH_TYPE_ACER_A8 3275
-#define MACH_TYPE_ACER_GAUGUIN 3276
-#define MACH_TYPE_GUPPY 3277
-#define MACH_TYPE_MX61_ARD 3278
-#define MACH_TYPE_TX53 3279
-#define MACH_TYPE_OMAPL138_CASE_A3 3280
-#define MACH_TYPE_UEMD 3281
-#define MACH_TYPE_CCWMX51MUT 3282
-#define MACH_TYPE_ROCKHOPPER 3283
-#define MACH_TYPE_ENCORE 3284
-#define MACH_TYPE_HKDKC100 3285
-#define MACH_TYPE_TS42XX 3286
-#define MACH_TYPE_AEBL 3287
#define MACH_TYPE_WARIO 3288
-#define MACH_TYPE_GFS_SPM 3289
#define MACH_TYPE_CM_T3730 3290
-#define MACH_TYPE_ISC3 3291
-#define MACH_TYPE_RASCAL 3292
#define MACH_TYPE_HREFV60 3293
-#define MACH_TYPE_TPT_2_0 3294
-#define MACH_TYPE_SPLENDOR 3296
-#define MACH_TYPE_MSM8X60_QT 3298
-#define MACH_TYPE_HTC_HD_MINI 3299
-#define MACH_TYPE_ATHENE 3300
-#define MACH_TYPE_DEEP_R_EK_1 3301
-#define MACH_TYPE_VIVOW_CT 3302
-#define MACH_TYPE_NERY_1000 3303
-#define MACH_TYPE_RFL109145_SSRV 3304
-#define MACH_TYPE_NMH 3305
-#define MACH_TYPE_WN802T 3306
-#define MACH_TYPE_DRAGONET 3307
-#define MACH_TYPE_AT91SAM9263DESK16L 3309
-#define MACH_TYPE_BCMHANA_SV 3310
-#define MACH_TYPE_BCMHANA_TABLET 3311
-#define MACH_TYPE_KOI 3312
-#define MACH_TYPE_TS4800 3313
-#define MACH_TYPE_TQMA9263 3314
-#define MACH_TYPE_HOLIDAY 3315
-#define MACH_TYPE_DMA6410 3316
-#define MACH_TYPE_PCATS_OVERLAY 3317
-#define MACH_TYPE_HWGW6410 3318
-#define MACH_TYPE_SHENZHOU 3319
-#define MACH_TYPE_CWME9210 3320
-#define MACH_TYPE_CWME9210JS 3321
-#define MACH_TYPE_PGS_SITARA 3322
-#define MACH_TYPE_COLIBRI_T20 3323
-#define MACH_TYPE_W21 3324
-#define MACH_TYPE_POLYSAT1 3325
-#define MACH_TYPE_DATAWAY 3326
-#define MACH_TYPE_COBRAL138 3327
-#define MACH_TYPE_ROVERPCS8 3328
-#define MACH_TYPE_MARVELC 3329
-#define MACH_TYPE_NAVEFIHID 3330
-#define MACH_TYPE_DM365_CV100 3331
-#define MACH_TYPE_ABLE 3332
-#define MACH_TYPE_LEGACY 3333
-#define MACH_TYPE_ICONG 3334
-#define MACH_TYPE_ROVER_G8 3335
-#define MACH_TYPE_T5388P 3336
-#define MACH_TYPE_DINGO 3337
-#define MACH_TYPE_GOFLEXHOME 3338
-#define MACH_TYPE_LANREADYFN511 3340
-#define MACH_TYPE_OMAP3_BAIA 3341
-#define MACH_TYPE_OMAP3SMARTDISPLAY 3342
-#define MACH_TYPE_XILINX 3343
-#define MACH_TYPE_A2F 3344
-#define MACH_TYPE_SKY25 3345
-#define MACH_TYPE_CCMX53 3346
-#define MACH_TYPE_CCMX53JS 3347
-#define MACH_TYPE_CCWMX53 3348
-#define MACH_TYPE_CCWMX53JS 3349
-#define MACH_TYPE_FRISMS 3350
-#define MACH_TYPE_MSM7X27A_FFA 3351
-#define MACH_TYPE_MSM7X27A_SURF 3352
-#define MACH_TYPE_MSM7X27A_RUMI3 3353
-#define MACH_TYPE_DIMMSAM9G20 3354
-#define MACH_TYPE_DIMM_IMX28 3355
-#define MACH_TYPE_AMK_A4 3356
-#define MACH_TYPE_GNET_SGME 3357
-#define MACH_TYPE_SHOOTER_U 3358
-#define MACH_TYPE_VMX53 3359
-#define MACH_TYPE_RHINO 3360
#define MACH_TYPE_ARMLEX4210 3361
-#define MACH_TYPE_SWARCOEXTMODEM 3362
-#define MACH_TYPE_PCM049 3364
-#define MACH_TYPE_VIGOR 3365
-#define MACH_TYPE_OSLO_AMUNDSEN 3366
-#define MACH_TYPE_GSL_DIAMOND 3367
-#define MACH_TYPE_CV2201 3368
-#define MACH_TYPE_CV2202 3369
-#define MACH_TYPE_CV2203 3370
-#define MACH_TYPE_VIT_IBOX 3371
-#define MACH_TYPE_DM6441_ESP 3372
-#define MACH_TYPE_AT91SAM9X5EK 3373
-#define MACH_TYPE_LIBRA 3374
-#define MACH_TYPE_EASYCRRH 3375
-#define MACH_TYPE_TRIPEL 3376
-#define MACH_TYPE_ENDIAN_MINI 3377
+#define MACH_TYPE_SNOWBALL 3363
#define MACH_TYPE_XILINX_EP107 3378
#define MACH_TYPE_NURI 3379
-#define MACH_TYPE_JANUS 3380
-#define MACH_TYPE_DDNAS 3381
-#define MACH_TYPE_TAG 3382
-#define MACH_TYPE_TAGW 3383
-#define MACH_TYPE_NITROGEN_VM_IMX51 3384
-#define MACH_TYPE_VIPRINET 3385
-#define MACH_TYPE_BOCKW 3386
-#define MACH_TYPE_EVA2000 3387
-#define MACH_TYPE_STEELYARD 3388
-#define MACH_TYPE_MACH_SDH001 3390
-#define MACH_TYPE_NSSLSBOARD 3392
-#define MACH_TYPE_GENEVA_B5 3393
-#define MACH_TYPE_SPEAR1340 3394
-#define MACH_TYPE_REXMAS 3395
-#define MACH_TYPE_MSM8960_CDP 3396
-#define MACH_TYPE_MSM8960_MDP 3397
-#define MACH_TYPE_MSM8960_FLUID 3398
-#define MACH_TYPE_MSM8960_APQ 3399
-#define MACH_TYPE_HELIOS_V2 3400
-#define MACH_TYPE_MIF10P 3401
-#define MACH_TYPE_IAM28 3402
-#define MACH_TYPE_PICASSO 3403
-#define MACH_TYPE_MR301A 3404
-#define MACH_TYPE_NOTLE 3405
-#define MACH_TYPE_EELX2 3406
-#define MACH_TYPE_MOON 3407
-#define MACH_TYPE_RUBY 3408
-#define MACH_TYPE_GOLDENGATE 3409
-#define MACH_TYPE_CTBU_GEN2 3410
-#define MACH_TYPE_KMP_AM17_01 3411
-#define MACH_TYPE_WTPLUG 3412
-#define MACH_TYPE_MX27SU2 3413
-#define MACH_TYPE_NB31 3414
-#define MACH_TYPE_HJSDU 3415
-#define MACH_TYPE_TD3_REV1 3416
-#define MACH_TYPE_EAG_CI4000 3417
-#define MACH_TYPE_NET5BIG_NAND_V2 3418
-#define MACH_TYPE_CPX2 3419
-#define MACH_TYPE_NET2BIG_NAND_V2 3420
-#define MACH_TYPE_ECUV5 3421
-#define MACH_TYPE_HSGX6D 3422
-#define MACH_TYPE_DAWAD7 3423
-#define MACH_TYPE_SAM9REPEATER 3424
-#define MACH_TYPE_GT_I5700 3425
-#define MACH_TYPE_CTERA_PLUG_C2 3426
-#define MACH_TYPE_MARVELCT 3427
-#define MACH_TYPE_AG11005 3428
-#define MACH_TYPE_VANGOGH 3430
-#define MACH_TYPE_MATRIX505 3431
-#define MACH_TYPE_OCE_NIGMA 3432
-#define MACH_TYPE_T55 3433
-#define MACH_TYPE_BIO3K 3434
-#define MACH_TYPE_EXPRESSCT 3435
-#define MACH_TYPE_CARDHU 3436
-#define MACH_TYPE_ARUBA 3437
-#define MACH_TYPE_BONAIRE 3438
-#define MACH_TYPE_NUC700EVB 3439
-#define MACH_TYPE_NUC710EVB 3440
-#define MACH_TYPE_NUC740EVB 3441
-#define MACH_TYPE_NUC745EVB 3442
-#define MACH_TYPE_TRANSCEDE 3443
-#define MACH_TYPE_MORA 3444
-#define MACH_TYPE_NDA_EVM 3445
-#define MACH_TYPE_TIMU 3446
-#define MACH_TYPE_EXPRESSH 3447
-#define MACH_TYPE_VERIDIS_A300 3448
-#define MACH_TYPE_DM368_LEOPARD 3449
-#define MACH_TYPE_OMAP_MCOP 3450
-#define MACH_TYPE_TRITIP 3451
-#define MACH_TYPE_SM1K 3452
-#define MACH_TYPE_MONCH 3453
-#define MACH_TYPE_CURACAO 3454
#define MACH_TYPE_ORIGEN 3455
-#define MACH_TYPE_EPC10 3456
-#define MACH_TYPE_SGH_I740 3457
-#define MACH_TYPE_TUNA 3458
-#define MACH_TYPE_MX51_TULIP 3459
-#define MACH_TYPE_MX51_ASTER7 3460
-#define MACH_TYPE_ACRO37XBRD 3461
-#define MACH_TYPE_ELKE 3462
-#define MACH_TYPE_SBC6000X 3463
-#define MACH_TYPE_R1801E 3464
-#define MACH_TYPE_H1600 3465
-#define MACH_TYPE_MINI210 3466
-#define MACH_TYPE_MINI8168 3467
-#define MACH_TYPE_PC7308 3468
-#define MACH_TYPE_KMM2M01 3470
-#define MACH_TYPE_MX51EREBUS 3471
-#define MACH_TYPE_WM8650REFBOARD 3472
-#define MACH_TYPE_TUXRAIL 3473
-#define MACH_TYPE_ARTHUR 3474
-#define MACH_TYPE_DOORBOY 3475
-#define MACH_TYPE_XARINA 3476
-#define MACH_TYPE_ROVERX7 3477
-#define MACH_TYPE_SDVR 3478
-#define MACH_TYPE_ACER_MAYA 3479
-#define MACH_TYPE_PICO 3480
-#define MACH_TYPE_CWMX233 3481
-#define MACH_TYPE_CWAM1808 3482
-#define MACH_TYPE_CWDM365 3483
-#define MACH_TYPE_MX51_MORAY 3484
-#define MACH_TYPE_THALES_CBC 3485
-#define MACH_TYPE_BLUEPOINT 3486
-#define MACH_TYPE_DIR665 3487
-#define MACH_TYPE_ACMEROVER1 3488
-#define MACH_TYPE_SHOOTER_CT 3489
-#define MACH_TYPE_BLISS 3490
-#define MACH_TYPE_BLISSC 3491
-#define MACH_TYPE_THALES_ADC 3492
-#define MACH_TYPE_UBISYS_P9D_EVP 3493
-#define MACH_TYPE_ATDGP318 3494
-#define MACH_TYPE_OMAP5_SEVM 3777
-#define MACH_TYPE_PICOSAM9G45 3838
-#define MACH_TYPE_ARMADILLO_800EVA 3863
+#define MACH_TYPE_NSPIRE 3503
+#define MACH_TYPE_NOKIA_RM696 3522
+#define MACH_TYPE_MIKRAP_X168 3543
+#define MACH_TYPE_DETO_MACARM9 3568
+#define MACH_TYPE_M28EVK 3613
+#define MACH_TYPE_KOTA2 3616
+#define MACH_TYPE_BONITO 3623
+#define MACH_TYPE_OMAP3_EGF 3637
+#define MACH_TYPE_SMDK4212 3638
+#define MACH_TYPE_APX4DEVKIT 3712
+#define MACH_TYPE_SMDK4412 3765
+#define MACH_TYPE_MARZEN 3790
+#define MACH_TYPE_KROME 3797
+#define MACH_TYPE_ARMADILLO800EVA 3863
+#define MACH_TYPE_MX53_UMOBO 3927
+#define MACH_TYPE_MT4 3981
+#define MACH_TYPE_U8520 3990
+#define MACH_TYPE_CHUPACABRA 4098
+#define MACH_TYPE_SCORPION 4099
+#define MACH_TYPE_DAVINCI_HE_HMI10 4100
+#define MACH_TYPE_TOPKICK 4101
+#define MACH_TYPE_M3_AUGUESTRUSH 4102
+#define MACH_TYPE_IPC335X 4103
+#define MACH_TYPE_SUN4I 4104
+#define MACH_TYPE_IMX233_OLINUXINO 4105
+#define MACH_TYPE_K2_WL 4106
+#define MACH_TYPE_K2_UL 4107
+#define MACH_TYPE_K2_CL 4108
+#define MACH_TYPE_MINBARI_W 4109
+#define MACH_TYPE_MINBARI_M 4110
+#define MACH_TYPE_K035 4111
+#define MACH_TYPE_ARIEL 4112
+#define MACH_TYPE_ARIELSAARC 4113
+#define MACH_TYPE_ARIELDKB 4114
+#define MACH_TYPE_ARMADILLO810 4115
+#define MACH_TYPE_TAM335X 4116
+#define MACH_TYPE_GROUPER 4117
+#define MACH_TYPE_MPCSA21_9G20 4118
+#define MACH_TYPE_M6U_CPU 4119
+#define MACH_TYPE_GINKGO 4121
+#define MACH_TYPE_CGT_QMX6 4122
+#define MACH_TYPE_PROFPGA 4123
+#define MACH_TYPE_ACFX100OC 4124
+#define MACH_TYPE_ACFX100NB 4125
+#define MACH_TYPE_CAPRICORN 4126
+#define MACH_TYPE_PISCES 4127
+#define MACH_TYPE_ARIES 4128
+#define MACH_TYPE_CANCER 4129
+#define MACH_TYPE_LEO 4130
+#define MACH_TYPE_VIRGO 4131
+#define MACH_TYPE_SAGITTARIUS 4132
+#define MACH_TYPE_DEVIL 4133
+#define MACH_TYPE_BALLANTINES 4134
+#define MACH_TYPE_OMAP3_PROCERUSVPU 4135
+#define MACH_TYPE_MY27 4136
+#define MACH_TYPE_SUN6I 4137
+#define MACH_TYPE_SUN5I 4138
+#define MACH_TYPE_MX512_MX 4139
#define MACH_TYPE_KZM9G 4140
+#define MACH_TYPE_VDSTBN 4141
+#define MACH_TYPE_CFA10036 4142
+#define MACH_TYPE_CFA10049 4143
+#define MACH_TYPE_PCM051 4144
+#define MACH_TYPE_VYBRID_VF7XX 4145
+#define MACH_TYPE_VYBRID_VF6XX 4146
+#define MACH_TYPE_VYBRID_VF5XX 4147
+#define MACH_TYPE_VYBRID_VF4XX 4148
+#define MACH_TYPE_ARIA_G25 4149
+#define MACH_TYPE_BCM21553 4150
+#define MACH_TYPE_SMDK5410 4151
+#define MACH_TYPE_LPC18XX 4152
+#define MACH_TYPE_ORATISPARTY 4153
+#define MACH_TYPE_QSEVEN 4154
+#define MACH_TYPE_GMV_GENERIC 4155
+#define MACH_TYPE_TH_LINK_ETH 4156
+#define MACH_TYPE_TN_MUNINN 4157
+#define MACH_TYPE_RAMPAGE 4158
+#define MACH_TYPE_VISSTRIM_MV10 4159
+#define MACH_TYPE_MX28_WILMA 4164
+#define MACH_TYPE_MSM8625_FFA 4166
+#define MACH_TYPE_VPU101 4167
+#define MACH_TYPE_BAILEYS 4169
+#define MACH_TYPE_FAMILYBOX 4170
+#define MACH_TYPE_ENSEMBLE_MX35 4171
+#define MACH_TYPE_SC_SPS_1 4172
+#define MACH_TYPE_UCSIMPLY_SAM9260 4173
+#define MACH_TYPE_UNICORN 4174
+#define MACH_TYPE_M9G45A 4175
+#define MACH_TYPE_MTWEBIF 4176
+#define MACH_TYPE_PLAYSTONE 4177
+#define MACH_TYPE_CHELSEA 4178
+#define MACH_TYPE_BAYERN 4179
+#define MACH_TYPE_MITWO 4180
+#define MACH_TYPE_MX25_NOAH 4181
+#define MACH_TYPE_STM_B2020 4182
+#define MACH_TYPE_ANNAX_SRC 4183
+#define MACH_TYPE_IONICS_STRATUS 4184
+#define MACH_TYPE_HUGO 4185
+#define MACH_TYPE_EM300 4186
+#define MACH_TYPE_MMP3_QSEVEN 4187
+#define MACH_TYPE_BOSPHORUS2 4188
+#define MACH_TYPE_TT2200 4189
+#define MACH_TYPE_OCELOT3 4190
+#define MACH_TYPE_TEK_COBRA 4191
+#define MACH_TYPE_PROTOU 4192
+#define MACH_TYPE_MSM8625_EVT 4193
+#define MACH_TYPE_MX53_SELLWOOD 4194
+#define MACH_TYPE_SOMIQ_AM35 4195
+#define MACH_TYPE_SOMIQ_AM37 4196
+#define MACH_TYPE_K2_PLC_CL 4197
+#define MACH_TYPE_TC2 4198
+#define MACH_TYPE_DULEX_J 4199
+#define MACH_TYPE_STM_B2044 4200
+#define MACH_TYPE_DELUXE_J 4201
+#define MACH_TYPE_MANGO2443 4202
+#define MACH_TYPE_CP2DCG 4203
+#define MACH_TYPE_CP2DTG 4204
+#define MACH_TYPE_CP2DUG 4205
+#define MACH_TYPE_VAR_SOM_AM33 4206
+#define MACH_TYPE_PEPPER 4207
+#define MACH_TYPE_MANGO2450 4208
+#define MACH_TYPE_VALENTE_WX_C9 4209
+#define MACH_TYPE_MINITV 4210
+#define MACH_TYPE_U8540 4211
+#define MACH_TYPE_IV_ATLAS_I_Z7E 4212
+#define MACH_TYPE_MACH_TYPE_SKY 4214
+#define MACH_TYPE_BLUESKY 4215
+#define MACH_TYPE_NGROUTER 4216
+#define MACH_TYPE_MX53_DENETIM 4217
+#define MACH_TYPE_OPAL 4218
+#define MACH_TYPE_GNET_US3GREF 4219
+#define MACH_TYPE_GNET_NC3G 4220
+#define MACH_TYPE_GNET_GE3G 4221
+#define MACH_TYPE_ADP2 4222
+#define MACH_TYPE_TQMA28 4223
+#define MACH_TYPE_KACOM3 4224
+#define MACH_TYPE_RRHDEMO 4225
+#define MACH_TYPE_PROTODUG 4226
+#define MACH_TYPE_LAGO 4227
+#define MACH_TYPE_KTT30 4228
+#define MACH_TYPE_TS43XX 4229
+#define MACH_TYPE_MX6Q_DENSO 4230
+#define MACH_TYPE_COMSAT_GSMUMTS8 4231
+#define MACH_TYPE_DREAMX 4232
+#define MACH_TYPE_THUNDERSTONEM 4233
+#define MACH_TYPE_YOYOPAD 4234
+#define MACH_TYPE_YOYOPATIENT 4235
+#define MACH_TYPE_A10L 4236
+#define MACH_TYPE_MQ60 4237
+#define MACH_TYPE_LINKSTATION_LSQL 4238
+#define MACH_TYPE_AM3703GATEWAY 4239
+#define MACH_TYPE_ACCIPITER 4240
+#define MACH_TYPE_MAGNIDUG 4242
+#define MACH_TYPE_HYDRA 4243
+#define MACH_TYPE_SUN3I 4244
+#define MACH_TYPE_STM_B2078 4245
+#define MACH_TYPE_AT91SAM9263DESKV2 4246
+#define MACH_TYPE_DELUXE_R 4247
+#define MACH_TYPE_P_98_V 4248
+#define MACH_TYPE_P_98_C 4249
+#define MACH_TYPE_DAVINCI_AM18XX_OMN 4250
+#define MACH_TYPE_SOCFPGA_CYCLONE5 4251
+#define MACH_TYPE_CABATUIN 4252
+#define MACH_TYPE_YOYOPAD_FT 4253
+#define MACH_TYPE_DAN2400EVB 4254
+#define MACH_TYPE_DAN3400EVB 4255
+#define MACH_TYPE_EDM_SF_IMX6 4256
+#define MACH_TYPE_EDM_CF_IMX6 4257
+#define MACH_TYPE_VPOS3XX 4258
+#define MACH_TYPE_VULCANO_9X5 4259
+#define MACH_TYPE_SPMP8000 4260
+#define MACH_TYPE_CATALINA 4261
+#define MACH_TYPE_RD88F5181L_FE 4262
+#define MACH_TYPE_MX535_MX 4263
+#define MACH_TYPE_ARMADILLO840 4264
+#define MACH_TYPE_SPC9000BASEBOARD 4265
+#define MACH_TYPE_IRIS 4266
+#define MACH_TYPE_PROTODCG 4267
+#define MACH_TYPE_PALMTREE 4268
+#define MACH_TYPE_NOVENA 4269
+#define MACH_TYPE_MA_UM 4270
+#define MACH_TYPE_MA_AM 4271
+#define MACH_TYPE_EMS348 4272
+#define MACH_TYPE_CM_FX6 4273
+#define MACH_TYPE_ARNDALE 4274
+#define MACH_TYPE_Q5XR5 4275
+#define MACH_TYPE_WILLOW 4276
+#define MACH_TYPE_OMAP3621_ODYV3 4277
+#define MACH_TYPE_OMAPL138_PRESONUS 4278
+#define MACH_TYPE_DVF99 4279
+#define MACH_TYPE_IMPRESSION_J 4280
+#define MACH_TYPE_QBLISSA9 4281
+#define MACH_TYPE_ROBIN_HELIVIEW10 4282
+#define MACH_TYPE_SUN7I 4283
+#define MACH_TYPE_MX6Q_HDMIDONGLE 4284
+#define MACH_TYPE_MX6_SID2 4285
+#define MACH_TYPE_HELIOS_V3 4286
+#define MACH_TYPE_HELIOS_V4 4287
+#define MACH_TYPE_Q7_IMX6 4288
+#define MACH_TYPE_ODROIDX 4289
+#define MACH_TYPE_ROBPRO 4290
+#define MACH_TYPE_RESEARCH59IF_MK1 4291
+#define MACH_TYPE_BOBSLEIGH 4292
+#define MACH_TYPE_DCSHGWT3 4293
+#define MACH_TYPE_GLD1018 4294
+#define MACH_TYPE_EV10 4295
+#define MACH_TYPE_NITROGEN6X 4296
+#define MACH_TYPE_P_107_BB 4297
+#define MACH_TYPE_EVITA_UTL 4298
+#define MACH_TYPE_FALCONWING 4299
+#define MACH_TYPE_DCT3 4300
+#define MACH_TYPE_CPX2E_CELL 4301
+#define MACH_TYPE_AMIRO 4302
+#define MACH_TYPE_MX6Q_BRASSBOARD 4303
+#define MACH_TYPE_DALMORE 4304
+#define MACH_TYPE_OMAP3_PORTAL7CP 4305
+#define MACH_TYPE_TEGRA_PLUTO 4306
+#define MACH_TYPE_MX6SL_EVK 4307
+#define MACH_TYPE_M7 4308
+#define MACH_TYPE_PXM2 4309
+#define MACH_TYPE_HABA_KNX_LITE 4310
+#define MACH_TYPE_TAI 4311
+#define MACH_TYPE_PROTOTD 4312
+#define MACH_TYPE_DST_TONTO 4313
+#define MACH_TYPE_DRACO 4314
+#define MACH_TYPE_DXR2 4315
+#define MACH_TYPE_RUT 4316
+#define MACH_TYPE_AM180X_WSC 4317
+#define MACH_TYPE_DELUXE_U 4318
+#define MACH_TYPE_DELUXE_UL 4319
+#define MACH_TYPE_AT91SAM9260MEDTHS 4320
+#define MACH_TYPE_MATRIX516 4321
+#define MACH_TYPE_VID401X 4322
+#define MACH_TYPE_HELIOS_V5 4323
+#define MACH_TYPE_PLAYPAQ2 4324
+#define MACH_TYPE_IGAM 4325
+#define MACH_TYPE_AMICO_I 4326
+#define MACH_TYPE_AMICO_E 4327
+#define MACH_TYPE_SENTIENT_MM3_CK 4328
+#define MACH_TYPE_SMX6 4329
+#define MACH_TYPE_PANGO 4330
+#define MACH_TYPE_NS115_STICK 4331
+#define MACH_TYPE_BCTRM3 4332
+#define MACH_TYPE_DOCTORWS 4333
+#define MACH_TYPE_M2601 4334
+#define MACH_TYPE_VGG1111 4337
+#define MACH_TYPE_COUNTACH 4338
+#define MACH_TYPE_VISSTRIM_SM20 4339
+#define MACH_TYPE_A639 4340
+#define MACH_TYPE_SPACEMONKEY 4341
+#define MACH_TYPE_ZPDU_STAMP 4342
+#define MACH_TYPE_HTC_G7_CLONE 4343
+#define MACH_TYPE_FT2080_CORVUS 4344
+#define MACH_TYPE_FISLAND 4345
+#define MACH_TYPE_ZPDU 4346
+#define MACH_TYPE_URT 4347
+#define MACH_TYPE_CONTI_OVIP 4348
+#define MACH_TYPE_OMAPL138_NAGRA 4349
+#define MACH_TYPE_DA850_AT3KP1 4350
+#define MACH_TYPE_DA850_AT3KP2 4351
+#define MACH_TYPE_SURMA 4352
+#define MACH_TYPE_STM_B2092 4353
+#define MACH_TYPE_MX535_YCR 4354
+#define MACH_TYPE_M7_WL 4355
+#define MACH_TYPE_M7_U 4356
+#define MACH_TYPE_OMAP3_STNDT_EVM 4357
+#define MACH_TYPE_M7_WLV 4358
+#define MACH_TYPE_XAM3517 4359
+#define MACH_TYPE_A220 4360
+#define MACH_TYPE_ACLIMA_ODIE 4361
+#define MACH_TYPE_VIBBLE 4362
+#define MACH_TYPE_K2_U 4363
+#define MACH_TYPE_MX53_EGF 4364
+#define MACH_TYPE_NOVPEK_IMX53 4365
+#define MACH_TYPE_NOVPEK_IMX6X 4366
+#define MACH_TYPE_MX25_SMARTBOX 4367
+#define MACH_TYPE_EICG6410 4368
+#define MACH_TYPE_PICASSO_E3 4369
+#define MACH_TYPE_MOTONAVIGATOR 4370
+#define MACH_TYPE_VARIOCONNECT2 4371
+#define MACH_TYPE_DELUXE_TW 4372
+#define MACH_TYPE_KORE3 4374
+#define MACH_TYPE_MX6S_DRS 4375
+#define MACH_TYPE_CMIMX6 4376
+#define MACH_TYPE_ROTH 4377
+#define MACH_TYPE_EQ4UX 4378
+#define MACH_TYPE_X1PLUS 4379
+#define MACH_TYPE_MODIMX27 4380
+#define MACH_TYPE_VIDEON_HDUAC 4381
+#define MACH_TYPE_BLACKBIRD 4382
+#define MACH_TYPE_RUNMASTER 4383
+#define MACH_TYPE_CERES 4384
+#define MACH_TYPE_NAD435 4385
+#define MACH_TYPE_NS115_PROTO_TYPE 4386
+#define MACH_TYPE_FS20_VCC 4387
+#define MACH_TYPE_MESON6TV_SKT 4389
+#define MACH_TYPE_KEYSTONE 4390
+#define MACH_TYPE_PCM052 4391
+#define MACH_TYPE_QRD_SKUD_PRIME 4393
+#define MACH_TYPE_GUF_SANTARO 4395
+#define MACH_TYPE_SHEEPSHEAD 4396
+#define MACH_TYPE_MX6_IWG15M_MXM 4397
+#define MACH_TYPE_MX6_IWG15M_Q7 4398
+#define MACH_TYPE_AT91SAM9263IF8MIC 4399
+#define MACH_TYPE_MARCOPOLO 4401
+#define MACH_TYPE_MX535_SDCR 4402
+#define MACH_TYPE_MX53_CSB2733 4403
+#define MACH_TYPE_DIVA 4404
+#define MACH_TYPE_NCR_7744 4405
+#define MACH_TYPE_MACALLAN 4406
+#define MACH_TYPE_WNR3500 4407
+#define MACH_TYPE_PGAVRF 4408
+#define MACH_TYPE_HELIOS_V6 4409
+#define MACH_TYPE_LCCT 4410
+#define MACH_TYPE_CSNDUG 4411
+#define MACH_TYPE_WANDBOARD_IMX6 4412
+#define MACH_TYPE_OMAP4_JET 4413
+#define MACH_TYPE_TEGRA_ROTH 4414
+#define MACH_TYPE_M7DCG 4415
+#define MACH_TYPE_M7DUG 4416
+#define MACH_TYPE_M7DTG 4417
+#define MACH_TYPE_AP42X 4418
+#define MACH_TYPE_VAR_SOM_MX6 4419
+#define MACH_TYPE_PDLU 4420
+#define MACH_TYPE_HYDROGEN 4421
+#define MACH_TYPE_NPA211E 4422
+#define MACH_TYPE_ARCADIA 4423
+#define MACH_TYPE_ARCADIA_L 4424
+#define MACH_TYPE_MSM8930DT 4425
+#define MACH_TYPE_KTAM3874 4426
+#define MACH_TYPE_CEC4 4427
+#define MACH_TYPE_APE6EVM 4428
+#define MACH_TYPE_TX6 4429
+#define MACH_TYPE_CFA10037 4431
+#define MACH_TYPE_EZP1000 4433
+#define MACH_TYPE_WGR826V 4434
+#define MACH_TYPE_EXUMA 4435
+#define MACH_TYPE_FREGATE 4436
+#define MACH_TYPE_OSIRISIMX508 4437
+#define MACH_TYPE_ST_EXIGO 4438
+#define MACH_TYPE_PISMO 4439
+#define MACH_TYPE_ATC7 4440
+#define MACH_TYPE_NSPIRECLP 4441
+#define MACH_TYPE_NSPIRETP 4442
+#define MACH_TYPE_NSPIRECX 4443
+#define MACH_TYPE_MAYA 4444
+#define MACH_TYPE_WECCT 4445
+#define MACH_TYPE_M2S 4446
+#define MACH_TYPE_MSM8625Q_EVBD 4447
+#define MACH_TYPE_TINY210 4448
+#define MACH_TYPE_G3 4449
+#define MACH_TYPE_HURRICANE 4450
+#define MACH_TYPE_MX6_POD 4451
+#define MACH_TYPE_ELONDCN 4452
+#define MACH_TYPE_CWMX535 4453
+#define MACH_TYPE_M7_WLJ 4454
+#define MACH_TYPE_QSP_ARM 4455
+#define MACH_TYPE_MSM8625Q_SKUD 4456
+#define MACH_TYPE_HTCMONDRIAN 4457
+#define MACH_TYPE_WATSON_EAD 4458
+#define MACH_TYPE_MITWOA 4459
+#define MACH_TYPE_OMAP3_WOLVERINE 4460
+#define MACH_TYPE_MAPLETREE 4461
+#define MACH_TYPE_MSM8625_FIH_SAE 4462
+#define MACH_TYPE_EPC35 4463
+#define MACH_TYPE_SMARTRTU 4464
+#define MACH_TYPE_RCM101 4465
+#define MACH_TYPE_AMX_IMX53_MXX 4466
+#define MACH_TYPE_ACER_A12 4470
+#define MACH_TYPE_SBC6X 4471
+#define MACH_TYPE_U2 4472
+#define MACH_TYPE_SMDK4270 4473
+#define MACH_TYPE_PRISCILLAG 4474
+#define MACH_TYPE_PRISCILLAC 4475
+#define MACH_TYPE_PRISCILLA 4476
+#define MACH_TYPE_INNOVA_SHPU_V2 4477
+#define MACH_TYPE_MACH_TYPE_DEP2410 4479
+#define MACH_TYPE_BCTRE3 4480
+#define MACH_TYPE_OMAP_M100 4481
+#define MACH_TYPE_FLO 4482
+#define MACH_TYPE_NANOBONE 4483
+#define MACH_TYPE_STM_B2105 4484
+#define MACH_TYPE_OMAP4_BSC_BAP_V3 4485
+#define MACH_TYPE_SS1PAM 4486
+#define MACH_TYPE_PRIMOMINIU 4488
+#define MACH_TYPE_MRT_35HD_DUALNAS_E 4489
+#define MACH_TYPE_KIWI 4490
+#define MACH_TYPE_HW90496 4491
+#define MACH_TYPE_MEP2440 4492
#define MACH_TYPE_COLIBRI_T30 4493
+#define MACH_TYPE_CWV1 4494
+#define MACH_TYPE_NSA325 4495
+#define MACH_TYPE_DPXMTC 4497
+#define MACH_TYPE_TT_STUTTGART 4498
+#define MACH_TYPE_MIRANDA_APCII 4499
+#define MACH_TYPE_MX6Q_MODEROX 4500
+#define MACH_TYPE_MUDSKIPPER 4501
+#define MACH_TYPE_URANIA 4502
+#define MACH_TYPE_STM_B2112 4503
+#define MACH_TYPE_MX6Q_ATS_PHOENIX 4505
+#define MACH_TYPE_STM_B2116 4506
+#define MACH_TYPE_MYTHOLOGY 4507
+#define MACH_TYPE_FC360V1 4508
+#define MACH_TYPE_GPS_SENSOR 4509
+#define MACH_TYPE_GAZELLE 4510
+#define MACH_TYPE_MPQ8064_DMA 4511
+#define MACH_TYPE_WEMS_ASD01 4512
#define MACH_TYPE_APALIS_T30 4513
-#define MACH_TYPE_OMAPL138_LCDK 2495
-
-#ifdef CONFIG_ARCH_EBSA110
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EBSA110
-# endif
-# define machine_is_ebsa110() (machine_arch_type == MACH_TYPE_EBSA110)
-#else
-# define machine_is_ebsa110() (0)
-#endif
-
-#ifdef CONFIG_ARCH_RPC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RISCPC
-# endif
-# define machine_is_riscpc() (machine_arch_type == MACH_TYPE_RISCPC)
-#else
-# define machine_is_riscpc() (0)
-#endif
-
-#ifdef CONFIG_ARCH_EBSA285
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EBSA285
-# endif
-# define machine_is_ebsa285() (machine_arch_type == MACH_TYPE_EBSA285)
-#else
-# define machine_is_ebsa285() (0)
-#endif
-
-#ifdef CONFIG_ARCH_NETWINDER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NETWINDER
-# endif
-# define machine_is_netwinder() (machine_arch_type == MACH_TYPE_NETWINDER)
-#else
-# define machine_is_netwinder() (0)
-#endif
-
-#ifdef CONFIG_ARCH_CATS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CATS
-# endif
-# define machine_is_cats() (machine_arch_type == MACH_TYPE_CATS)
-#else
-# define machine_is_cats() (0)
-#endif
-
-#ifdef CONFIG_ARCH_SHARK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SHARK
-# endif
-# define machine_is_shark() (machine_arch_type == MACH_TYPE_SHARK)
-#else
-# define machine_is_shark() (0)
-#endif
-
-#ifdef CONFIG_SA1100_BRUTUS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BRUTUS
-# endif
-# define machine_is_brutus() (machine_arch_type == MACH_TYPE_BRUTUS)
-#else
-# define machine_is_brutus() (0)
-#endif
-
-#ifdef CONFIG_ARCH_PERSONAL_SERVER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PERSONAL_SERVER
-# endif
-# define machine_is_personal_server() (machine_arch_type == MACH_TYPE_PERSONAL_SERVER)
-#else
-# define machine_is_personal_server() (0)
-#endif
-
-#ifdef CONFIG_ARCH_L7200
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_L7200
-# endif
-# define machine_is_l7200() (machine_arch_type == MACH_TYPE_L7200)
-#else
-# define machine_is_l7200() (0)
-#endif
-
-#ifdef CONFIG_SA1100_PLEB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PLEB
-# endif
-# define machine_is_pleb() (machine_arch_type == MACH_TYPE_PLEB)
-#else
-# define machine_is_pleb() (0)
-#endif
-
-#ifdef CONFIG_ARCH_INTEGRATOR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_INTEGRATOR
-# endif
-# define machine_is_integrator() (machine_arch_type == MACH_TYPE_INTEGRATOR)
-#else
-# define machine_is_integrator() (0)
-#endif
-
-#ifdef CONFIG_SA1100_H3600
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_H3600
-# endif
-# define machine_is_h3600() (machine_arch_type == MACH_TYPE_H3600)
-#else
-# define machine_is_h3600() (0)
-#endif
-
-#ifdef CONFIG_ARCH_P720T
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_P720T
-# endif
-# define machine_is_p720t() (machine_arch_type == MACH_TYPE_P720T)
-#else
-# define machine_is_p720t() (0)
-#endif
-
-#ifdef CONFIG_SA1100_ASSABET
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ASSABET
-# endif
-# define machine_is_assabet() (machine_arch_type == MACH_TYPE_ASSABET)
-#else
-# define machine_is_assabet() (0)
-#endif
-
-#ifdef CONFIG_SA1100_LART
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LART
-# endif
-# define machine_is_lart() (machine_arch_type == MACH_TYPE_LART)
-#else
-# define machine_is_lart() (0)
-#endif
-
-#ifdef CONFIG_SA1100_GRAPHICSCLIENT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GRAPHICSCLIENT
-# endif
-# define machine_is_graphicsclient() (machine_arch_type == MACH_TYPE_GRAPHICSCLIENT)
-#else
-# define machine_is_graphicsclient() (0)
-#endif
-
-#ifdef CONFIG_SA1100_XP860
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_XP860
-# endif
-# define machine_is_xp860() (machine_arch_type == MACH_TYPE_XP860)
-#else
-# define machine_is_xp860() (0)
-#endif
-
-#ifdef CONFIG_SA1100_CERF
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CERF
-# endif
-# define machine_is_cerf() (machine_arch_type == MACH_TYPE_CERF)
-#else
-# define machine_is_cerf() (0)
-#endif
-
-#ifdef CONFIG_SA1100_NANOENGINE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NANOENGINE
-# endif
-# define machine_is_nanoengine() (machine_arch_type == MACH_TYPE_NANOENGINE)
-#else
-# define machine_is_nanoengine() (0)
-#endif
-
-#ifdef CONFIG_SA1100_JORNADA720
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_JORNADA720
-# endif
-# define machine_is_jornada720() (machine_arch_type == MACH_TYPE_JORNADA720)
-#else
-# define machine_is_jornada720() (0)
-#endif
-
-#ifdef CONFIG_ARCH_EDB7211
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EDB7211
-# endif
-# define machine_is_edb7211() (machine_arch_type == MACH_TYPE_EDB7211)
-#else
-# define machine_is_edb7211() (0)
-#endif
-
-#ifdef CONFIG_SA1100_PFS168
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PFS168
-# endif
-# define machine_is_pfs168() (machine_arch_type == MACH_TYPE_PFS168)
-#else
-# define machine_is_pfs168() (0)
-#endif
-
-#ifdef CONFIG_SA1100_FLEXANET
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FLEXANET
-# endif
-# define machine_is_flexanet() (machine_arch_type == MACH_TYPE_FLEXANET)
-#else
-# define machine_is_flexanet() (0)
-#endif
-
-#ifdef CONFIG_SA1100_SIMPAD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SIMPAD
-# endif
-# define machine_is_simpad() (machine_arch_type == MACH_TYPE_SIMPAD)
-#else
-# define machine_is_simpad() (0)
-#endif
-
-#ifdef CONFIG_ARCH_LUBBOCK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LUBBOCK
-# endif
-# define machine_is_lubbock() (machine_arch_type == MACH_TYPE_LUBBOCK)
-#else
-# define machine_is_lubbock() (0)
-#endif
-
-#ifdef CONFIG_ARCH_CLEP7212
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CLEP7212
-# endif
-# define machine_is_clep7212() (machine_arch_type == MACH_TYPE_CLEP7212)
-#else
-# define machine_is_clep7212() (0)
-#endif
-
-#ifdef CONFIG_SA1100_SHANNON
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SHANNON
-# endif
-# define machine_is_shannon() (machine_arch_type == MACH_TYPE_SHANNON)
-#else
-# define machine_is_shannon() (0)
-#endif
-
-#ifdef CONFIG_SA1100_CONSUS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CONSUS
-# endif
-# define machine_is_consus() (machine_arch_type == MACH_TYPE_CONSUS)
-#else
-# define machine_is_consus() (0)
-#endif
-
-#ifdef CONFIG_ARCH_AAED2000
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AAED2000
-# endif
-# define machine_is_aaed2000() (machine_arch_type == MACH_TYPE_AAED2000)
-#else
-# define machine_is_aaed2000() (0)
-#endif
-
-#ifdef CONFIG_ARCH_CDB89712
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CDB89712
-# endif
-# define machine_is_cdb89712() (machine_arch_type == MACH_TYPE_CDB89712)
-#else
-# define machine_is_cdb89712() (0)
-#endif
-
-#ifdef CONFIG_SA1100_GRAPHICSMASTER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GRAPHICSMASTER
-# endif
-# define machine_is_graphicsmaster() (machine_arch_type == MACH_TYPE_GRAPHICSMASTER)
-#else
-# define machine_is_graphicsmaster() (0)
-#endif
-
-#ifdef CONFIG_SA1100_ADSBITSY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ADSBITSY
-# endif
-# define machine_is_adsbitsy() (machine_arch_type == MACH_TYPE_ADSBITSY)
-#else
-# define machine_is_adsbitsy() (0)
-#endif
-
-#ifdef CONFIG_ARCH_PXA_IDP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PXA_IDP
-# endif
-# define machine_is_pxa_idp() (machine_arch_type == MACH_TYPE_PXA_IDP)
-#else
-# define machine_is_pxa_idp() (0)
-#endif
-
-#ifdef CONFIG_SA1100_PT_SYSTEM3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PT_SYSTEM3
-# endif
-# define machine_is_pt_system3() (machine_arch_type == MACH_TYPE_PT_SYSTEM3)
-#else
-# define machine_is_pt_system3() (0)
-#endif
-
-#ifdef CONFIG_ARCH_AUTCPU12
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AUTCPU12
-# endif
-# define machine_is_autcpu12() (machine_arch_type == MACH_TYPE_AUTCPU12)
-#else
-# define machine_is_autcpu12() (0)
-#endif
-
-#ifdef CONFIG_SA1100_H3100
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_H3100
-# endif
-# define machine_is_h3100() (machine_arch_type == MACH_TYPE_H3100)
-#else
-# define machine_is_h3100() (0)
-#endif
-
-#ifdef CONFIG_SA1100_COLLIE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_COLLIE
-# endif
-# define machine_is_collie() (machine_arch_type == MACH_TYPE_COLLIE)
-#else
-# define machine_is_collie() (0)
-#endif
-
-#ifdef CONFIG_SA1100_BADGE4
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BADGE4
-# endif
-# define machine_is_badge4() (machine_arch_type == MACH_TYPE_BADGE4)
-#else
-# define machine_is_badge4() (0)
-#endif
-
-#ifdef CONFIG_ARCH_FORTUNET
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FORTUNET
-# endif
-# define machine_is_fortunet() (machine_arch_type == MACH_TYPE_FORTUNET)
-#else
-# define machine_is_fortunet() (0)
-#endif
-
-#ifdef CONFIG_ARCH_MX1ADS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX1ADS
-# endif
-# define machine_is_mx1ads() (machine_arch_type == MACH_TYPE_MX1ADS)
-#else
-# define machine_is_mx1ads() (0)
-#endif
-
-#ifdef CONFIG_ARCH_H7201
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_H7201
-# endif
-# define machine_is_h7201() (machine_arch_type == MACH_TYPE_H7201)
-#else
-# define machine_is_h7201() (0)
-#endif
-
-#ifdef CONFIG_ARCH_H7202
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_H7202
-# endif
-# define machine_is_h7202() (machine_arch_type == MACH_TYPE_H7202)
-#else
-# define machine_is_h7202() (0)
-#endif
-
-#ifdef CONFIG_ARCH_IQ80321
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IQ80321
-# endif
-# define machine_is_iq80321() (machine_arch_type == MACH_TYPE_IQ80321)
-#else
-# define machine_is_iq80321() (0)
-#endif
-
-#ifdef CONFIG_ARCH_KS8695
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KS8695
-# endif
-# define machine_is_ks8695() (machine_arch_type == MACH_TYPE_KS8695)
-#else
-# define machine_is_ks8695() (0)
-#endif
-
-#ifdef CONFIG_ARCH_SMDK2410
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDK2410
-# endif
-# define machine_is_smdk2410() (machine_arch_type == MACH_TYPE_SMDK2410)
-#else
-# define machine_is_smdk2410() (0)
-#endif
-
-#ifdef CONFIG_ARCH_CEIVA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CEIVA
-# endif
-# define machine_is_ceiva() (machine_arch_type == MACH_TYPE_CEIVA)
-#else
-# define machine_is_ceiva() (0)
-#endif
-
-#ifdef CONFIG_MACH_VOICEBLUE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VOICEBLUE
-# endif
-# define machine_is_voiceblue() (machine_arch_type == MACH_TYPE_VOICEBLUE)
-#else
-# define machine_is_voiceblue() (0)
-#endif
-
-#ifdef CONFIG_ARCH_H5400
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_H5400
-# endif
-# define machine_is_h5400() (machine_arch_type == MACH_TYPE_H5400)
-#else
-# define machine_is_h5400() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_INNOVATOR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_INNOVATOR
-# endif
-# define machine_is_omap_innovator() (machine_arch_type == MACH_TYPE_OMAP_INNOVATOR)
-#else
-# define machine_is_omap_innovator() (0)
-#endif
-
-#ifdef CONFIG_ARCH_IXDP2400
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IXDP2400
-# endif
-# define machine_is_ixdp2400() (machine_arch_type == MACH_TYPE_IXDP2400)
-#else
-# define machine_is_ixdp2400() (0)
-#endif
-
-#ifdef CONFIG_ARCH_IXDP2800
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IXDP2800
-# endif
-# define machine_is_ixdp2800() (machine_arch_type == MACH_TYPE_IXDP2800)
-#else
-# define machine_is_ixdp2800() (0)
-#endif
-
-#ifdef CONFIG_ARCH_IXDP425
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IXDP425
-# endif
-# define machine_is_ixdp425() (machine_arch_type == MACH_TYPE_IXDP425)
-#else
-# define machine_is_ixdp425() (0)
-#endif
-
-#ifdef CONFIG_SA1100_HACKKIT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HACKKIT
-# endif
-# define machine_is_hackkit() (machine_arch_type == MACH_TYPE_HACKKIT)
-#else
-# define machine_is_hackkit() (0)
-#endif
-
-#ifdef CONFIG_ARCH_IXCDP1100
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IXCDP1100
-# endif
-# define machine_is_ixcdp1100() (machine_arch_type == MACH_TYPE_IXCDP1100)
-#else
-# define machine_is_ixcdp1100() (0)
-#endif
-
-#ifdef CONFIG_ARCH_AT91RM9200DK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91RM9200DK
-# endif
-# define machine_is_at91rm9200dk() (machine_arch_type == MACH_TYPE_AT91RM9200DK)
-#else
-# define machine_is_at91rm9200dk() (0)
-#endif
-
-#ifdef CONFIG_ARCH_CINTEGRATOR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CINTEGRATOR
-# endif
-# define machine_is_cintegrator() (machine_arch_type == MACH_TYPE_CINTEGRATOR)
-#else
-# define machine_is_cintegrator() (0)
-#endif
-
-#ifdef CONFIG_ARCH_VIPER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VIPER
-# endif
-# define machine_is_viper() (machine_arch_type == MACH_TYPE_VIPER)
-#else
-# define machine_is_viper() (0)
-#endif
-
-#ifdef CONFIG_ARCH_ADI_COYOTE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ADI_COYOTE
-# endif
-# define machine_is_adi_coyote() (machine_arch_type == MACH_TYPE_ADI_COYOTE)
-#else
-# define machine_is_adi_coyote() (0)
-#endif
-
-#ifdef CONFIG_ARCH_IXDP2401
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IXDP2401
-# endif
-# define machine_is_ixdp2401() (machine_arch_type == MACH_TYPE_IXDP2401)
-#else
-# define machine_is_ixdp2401() (0)
-#endif
-
-#ifdef CONFIG_ARCH_IXDP2801
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IXDP2801
-# endif
-# define machine_is_ixdp2801() (machine_arch_type == MACH_TYPE_IXDP2801)
-#else
-# define machine_is_ixdp2801() (0)
-#endif
-
-#ifdef CONFIG_ARCH_IQ31244
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IQ31244
-# endif
-# define machine_is_iq31244() (machine_arch_type == MACH_TYPE_IQ31244)
-#else
-# define machine_is_iq31244() (0)
-#endif
-
-#ifdef CONFIG_ARCH_BAST
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BAST
-# endif
-# define machine_is_bast() (machine_arch_type == MACH_TYPE_BAST)
-#else
-# define machine_is_bast() (0)
-#endif
-
-#ifdef CONFIG_ARCH_H1940
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_H1940
-# endif
-# define machine_is_h1940() (machine_arch_type == MACH_TYPE_H1940)
-#else
-# define machine_is_h1940() (0)
-#endif
-
-#ifdef CONFIG_ARCH_ENP2611
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ENP2611
-# endif
-# define machine_is_enp2611() (machine_arch_type == MACH_TYPE_ENP2611)
-#else
-# define machine_is_enp2611() (0)
-#endif
-
-#ifdef CONFIG_ARCH_S3C2440
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_S3C2440
-# endif
-# define machine_is_s3c2440() (machine_arch_type == MACH_TYPE_S3C2440)
-#else
-# define machine_is_s3c2440() (0)
-#endif
-
-#ifdef CONFIG_ARCH_GUMSTIX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GUMSTIX
-# endif
-# define machine_is_gumstix() (machine_arch_type == MACH_TYPE_GUMSTIX)
-#else
-# define machine_is_gumstix() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_H2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_H2
-# endif
-# define machine_is_omap_h2() (machine_arch_type == MACH_TYPE_OMAP_H2)
-#else
-# define machine_is_omap_h2() (0)
-#endif
-
-#ifdef CONFIG_MACH_E740
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_E740
-# endif
-# define machine_is_e740() (machine_arch_type == MACH_TYPE_E740)
-#else
-# define machine_is_e740() (0)
-#endif
-
-#ifdef CONFIG_ARCH_IQ80331
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IQ80331
-# endif
-# define machine_is_iq80331() (machine_arch_type == MACH_TYPE_IQ80331)
-#else
-# define machine_is_iq80331() (0)
-#endif
-
-#ifdef CONFIG_ARCH_VERSATILE_PB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VERSATILE_PB
-# endif
-# define machine_is_versatile_pb() (machine_arch_type == MACH_TYPE_VERSATILE_PB)
-#else
-# define machine_is_versatile_pb() (0)
-#endif
-
-#ifdef CONFIG_MACH_KEV7A400
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KEV7A400
-# endif
-# define machine_is_kev7a400() (machine_arch_type == MACH_TYPE_KEV7A400)
-#else
-# define machine_is_kev7a400() (0)
-#endif
-
-#ifdef CONFIG_MACH_LPD7A400
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LPD7A400
-# endif
-# define machine_is_lpd7a400() (machine_arch_type == MACH_TYPE_LPD7A400)
-#else
-# define machine_is_lpd7a400() (0)
-#endif
-
-#ifdef CONFIG_MACH_LPD7A404
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LPD7A404
-# endif
-# define machine_is_lpd7a404() (machine_arch_type == MACH_TYPE_LPD7A404)
-#else
-# define machine_is_lpd7a404() (0)
-#endif
-
-#ifdef CONFIG_MACH_CSB337
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CSB337
-# endif
-# define machine_is_csb337() (machine_arch_type == MACH_TYPE_CSB337)
-#else
-# define machine_is_csb337() (0)
-#endif
-
-#ifdef CONFIG_MACH_MAINSTONE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MAINSTONE
-# endif
-# define machine_is_mainstone() (machine_arch_type == MACH_TYPE_MAINSTONE)
-#else
-# define machine_is_mainstone() (0)
-#endif
-
-#ifdef CONFIG_MACH_XCEP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_XCEP
-# endif
-# define machine_is_xcep() (machine_arch_type == MACH_TYPE_XCEP)
-#else
-# define machine_is_xcep() (0)
-#endif
-
-#ifdef CONFIG_MACH_ARCOM_VULCAN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ARCOM_VULCAN
-# endif
-# define machine_is_arcom_vulcan() (machine_arch_type == MACH_TYPE_ARCOM_VULCAN)
-#else
-# define machine_is_arcom_vulcan() (0)
-#endif
-
-#ifdef CONFIG_MACH_NOMADIK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NOMADIK
-# endif
-# define machine_is_nomadik() (machine_arch_type == MACH_TYPE_NOMADIK)
-#else
-# define machine_is_nomadik() (0)
-#endif
-
-#ifdef CONFIG_MACH_CORGI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CORGI
-# endif
-# define machine_is_corgi() (machine_arch_type == MACH_TYPE_CORGI)
-#else
-# define machine_is_corgi() (0)
-#endif
-
-#ifdef CONFIG_MACH_POODLE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_POODLE
-# endif
-# define machine_is_poodle() (machine_arch_type == MACH_TYPE_POODLE)
-#else
-# define machine_is_poodle() (0)
-#endif
-
-#ifdef CONFIG_MACH_ARMCORE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ARMCORE
-# endif
-# define machine_is_armcore() (machine_arch_type == MACH_TYPE_ARMCORE)
-#else
-# define machine_is_armcore() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX31ADS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX31ADS
-# endif
-# define machine_is_mx31ads() (machine_arch_type == MACH_TYPE_MX31ADS)
-#else
-# define machine_is_mx31ads() (0)
-#endif
-
-#ifdef CONFIG_MACH_HIMALAYA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HIMALAYA
-# endif
-# define machine_is_himalaya() (machine_arch_type == MACH_TYPE_HIMALAYA)
-#else
-# define machine_is_himalaya() (0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9312
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EDB9312
-# endif
-# define machine_is_edb9312() (machine_arch_type == MACH_TYPE_EDB9312)
-#else
-# define machine_is_edb9312() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_GENERIC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_GENERIC
-# endif
-# define machine_is_omap_generic() (machine_arch_type == MACH_TYPE_OMAP_GENERIC)
-#else
-# define machine_is_omap_generic() (0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9301
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EDB9301
-# endif
-# define machine_is_edb9301() (machine_arch_type == MACH_TYPE_EDB9301)
-#else
-# define machine_is_edb9301() (0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9315
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EDB9315
-# endif
-# define machine_is_edb9315() (machine_arch_type == MACH_TYPE_EDB9315)
-#else
-# define machine_is_edb9315() (0)
-#endif
-
-#ifdef CONFIG_MACH_VR1000
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VR1000
-# endif
-# define machine_is_vr1000() (machine_arch_type == MACH_TYPE_VR1000)
-#else
-# define machine_is_vr1000() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PERSEUS2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_PERSEUS2
-# endif
-# define machine_is_omap_perseus2() (machine_arch_type == MACH_TYPE_OMAP_PERSEUS2)
-#else
-# define machine_is_omap_perseus2() (0)
-#endif
-
-#ifdef CONFIG_MACH_E800
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_E800
-# endif
-# define machine_is_e800() (machine_arch_type == MACH_TYPE_E800)
-#else
-# define machine_is_e800() (0)
-#endif
-
-#ifdef CONFIG_MACH_E750
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_E750
-# endif
-# define machine_is_e750() (machine_arch_type == MACH_TYPE_E750)
-#else
-# define machine_is_e750() (0)
-#endif
-
-#ifdef CONFIG_MACH_SCB9328
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SCB9328
-# endif
-# define machine_is_scb9328() (machine_arch_type == MACH_TYPE_SCB9328)
-#else
-# define machine_is_scb9328() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_H3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_H3
-# endif
-# define machine_is_omap_h3() (machine_arch_type == MACH_TYPE_OMAP_H3)
-#else
-# define machine_is_omap_h3() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_H4
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_H4
-# endif
-# define machine_is_omap_h4() (machine_arch_type == MACH_TYPE_OMAP_H4)
-#else
-# define machine_is_omap_h4() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_OSK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_OSK
-# endif
-# define machine_is_omap_osk() (machine_arch_type == MACH_TYPE_OMAP_OSK)
-#else
-# define machine_is_omap_osk() (0)
-#endif
-
-#ifdef CONFIG_MACH_TOSA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TOSA
-# endif
-# define machine_is_tosa() (machine_arch_type == MACH_TYPE_TOSA)
-#else
-# define machine_is_tosa() (0)
-#endif
-
-#ifdef CONFIG_MACH_AVILA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AVILA
-# endif
-# define machine_is_avila() (machine_arch_type == MACH_TYPE_AVILA)
-#else
-# define machine_is_avila() (0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9302
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EDB9302
-# endif
-# define machine_is_edb9302() (machine_arch_type == MACH_TYPE_EDB9302)
-#else
-# define machine_is_edb9302() (0)
-#endif
-
-#ifdef CONFIG_MACH_HUSKY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HUSKY
-# endif
-# define machine_is_husky() (machine_arch_type == MACH_TYPE_HUSKY)
-#else
-# define machine_is_husky() (0)
-#endif
-
-#ifdef CONFIG_MACH_SHEPHERD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SHEPHERD
-# endif
-# define machine_is_shepherd() (machine_arch_type == MACH_TYPE_SHEPHERD)
-#else
-# define machine_is_shepherd() (0)
-#endif
-
-#ifdef CONFIG_MACH_H4700
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_H4700
-# endif
-# define machine_is_h4700() (machine_arch_type == MACH_TYPE_H4700)
-#else
-# define machine_is_h4700() (0)
-#endif
-
-#ifdef CONFIG_MACH_RX3715
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RX3715
-# endif
-# define machine_is_rx3715() (machine_arch_type == MACH_TYPE_RX3715)
-#else
-# define machine_is_rx3715() (0)
-#endif
-
-#ifdef CONFIG_MACH_NSLU2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NSLU2
-# endif
-# define machine_is_nslu2() (machine_arch_type == MACH_TYPE_NSLU2)
-#else
-# define machine_is_nslu2() (0)
-#endif
-
-#ifdef CONFIG_MACH_E400
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_E400
-# endif
-# define machine_is_e400() (machine_arch_type == MACH_TYPE_E400)
-#else
-# define machine_is_e400() (0)
-#endif
-
-#ifdef CONFIG_MACH_IXDPG425
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IXDPG425
-# endif
-# define machine_is_ixdpg425() (machine_arch_type == MACH_TYPE_IXDPG425)
-#else
-# define machine_is_ixdpg425() (0)
-#endif
-
-#ifdef CONFIG_MACH_VERSATILE_AB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VERSATILE_AB
-# endif
-# define machine_is_versatile_ab() (machine_arch_type == MACH_TYPE_VERSATILE_AB)
-#else
-# define machine_is_versatile_ab() (0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9307
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EDB9307
-# endif
-# define machine_is_edb9307() (machine_arch_type == MACH_TYPE_EDB9307)
-#else
-# define machine_is_edb9307() (0)
-#endif
-
-#ifdef CONFIG_MACH_KB9200
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KB9200
-# endif
-# define machine_is_kb9200() (machine_arch_type == MACH_TYPE_KB9200)
-#else
-# define machine_is_kb9200() (0)
-#endif
-
-#ifdef CONFIG_MACH_SX1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SX1
-# endif
-# define machine_is_sx1() (machine_arch_type == MACH_TYPE_SX1)
-#else
-# define machine_is_sx1() (0)
-#endif
-
-#ifdef CONFIG_MACH_IXDP465
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IXDP465
-# endif
-# define machine_is_ixdp465() (machine_arch_type == MACH_TYPE_IXDP465)
-#else
-# define machine_is_ixdp465() (0)
-#endif
-
-#ifdef CONFIG_MACH_IXDP2351
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IXDP2351
-# endif
-# define machine_is_ixdp2351() (machine_arch_type == MACH_TYPE_IXDP2351)
-#else
-# define machine_is_ixdp2351() (0)
-#endif
-
-#ifdef CONFIG_MACH_IQ80332
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IQ80332
-# endif
-# define machine_is_iq80332() (machine_arch_type == MACH_TYPE_IQ80332)
-#else
-# define machine_is_iq80332() (0)
-#endif
-
-#ifdef CONFIG_MACH_GTWX5715
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GTWX5715
-# endif
-# define machine_is_gtwx5715() (machine_arch_type == MACH_TYPE_GTWX5715)
-#else
-# define machine_is_gtwx5715() (0)
-#endif
-
-#ifdef CONFIG_MACH_CSB637
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CSB637
-# endif
-# define machine_is_csb637() (machine_arch_type == MACH_TYPE_CSB637)
-#else
-# define machine_is_csb637() (0)
-#endif
-
-#ifdef CONFIG_MACH_N30
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_N30
-# endif
-# define machine_is_n30() (machine_arch_type == MACH_TYPE_N30)
-#else
-# define machine_is_n30() (0)
-#endif
-
-#ifdef CONFIG_MACH_NEC_MP900
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NEC_MP900
-# endif
-# define machine_is_nec_mp900() (machine_arch_type == MACH_TYPE_NEC_MP900)
-#else
-# define machine_is_nec_mp900() (0)
-#endif
-
-#ifdef CONFIG_MACH_KAFA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KAFA
-# endif
-# define machine_is_kafa() (machine_arch_type == MACH_TYPE_KAFA)
-#else
-# define machine_is_kafa() (0)
-#endif
-
-#ifdef CONFIG_MACH_TS72XX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TS72XX
-# endif
-# define machine_is_ts72xx() (machine_arch_type == MACH_TYPE_TS72XX)
-#else
-# define machine_is_ts72xx() (0)
-#endif
-
-#ifdef CONFIG_MACH_OTOM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OTOM
-# endif
-# define machine_is_otom() (machine_arch_type == MACH_TYPE_OTOM)
-#else
-# define machine_is_otom() (0)
-#endif
-
-#ifdef CONFIG_MACH_NEXCODER_2440
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NEXCODER_2440
-# endif
-# define machine_is_nexcoder_2440() (machine_arch_type == MACH_TYPE_NEXCODER_2440)
-#else
-# define machine_is_nexcoder_2440() (0)
-#endif
-
-#ifdef CONFIG_MACH_ECO920
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ECO920
-# endif
-# define machine_is_eco920() (machine_arch_type == MACH_TYPE_ECO920)
-#else
-# define machine_is_eco920() (0)
-#endif
-
-#ifdef CONFIG_MACH_ROADRUNNER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ROADRUNNER
-# endif
-# define machine_is_roadrunner() (machine_arch_type == MACH_TYPE_ROADRUNNER)
-#else
-# define machine_is_roadrunner() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91RM9200EK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91RM9200EK
-# endif
-# define machine_is_at91rm9200ek() (machine_arch_type == MACH_TYPE_AT91RM9200EK)
-#else
-# define machine_is_at91rm9200ek() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPITZ
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPITZ
-# endif
-# define machine_is_spitz() (machine_arch_type == MACH_TYPE_SPITZ)
-#else
-# define machine_is_spitz() (0)
-#endif
-
-#ifdef CONFIG_MACH_ADSSPHERE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ADSSPHERE
-# endif
-# define machine_is_adssphere() (machine_arch_type == MACH_TYPE_ADSSPHERE)
-#else
-# define machine_is_adssphere() (0)
-#endif
-
-#ifdef CONFIG_MACH_COLIBRI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_COLIBRI
-# endif
-# define machine_is_colibri() (machine_arch_type == MACH_TYPE_COLIBRI)
-#else
-# define machine_is_colibri() (0)
-#endif
-
-#ifdef CONFIG_MACH_GATEWAY7001
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GATEWAY7001
-# endif
-# define machine_is_gateway7001() (machine_arch_type == MACH_TYPE_GATEWAY7001)
-#else
-# define machine_is_gateway7001() (0)
-#endif
-
-#ifdef CONFIG_MACH_PCM027
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PCM027
-# endif
-# define machine_is_pcm027() (machine_arch_type == MACH_TYPE_PCM027)
-#else
-# define machine_is_pcm027() (0)
-#endif
-
-#ifdef CONFIG_MACH_ANUBIS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ANUBIS
-# endif
-# define machine_is_anubis() (machine_arch_type == MACH_TYPE_ANUBIS)
-#else
-# define machine_is_anubis() (0)
-#endif
-
-#ifdef CONFIG_MACH_AKITA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AKITA
-# endif
-# define machine_is_akita() (machine_arch_type == MACH_TYPE_AKITA)
-#else
-# define machine_is_akita() (0)
-#endif
-
-#ifdef CONFIG_MACH_E330
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_E330
-# endif
-# define machine_is_e330() (machine_arch_type == MACH_TYPE_E330)
-#else
-# define machine_is_e330() (0)
-#endif
-
-#ifdef CONFIG_MACH_NOKIA770
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NOKIA770
-# endif
-# define machine_is_nokia770() (machine_arch_type == MACH_TYPE_NOKIA770)
-#else
-# define machine_is_nokia770() (0)
-#endif
-
-#ifdef CONFIG_MACH_CARMEVA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CARMEVA
-# endif
-# define machine_is_carmeva() (machine_arch_type == MACH_TYPE_CARMEVA)
-#else
-# define machine_is_carmeva() (0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9315A
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EDB9315A
-# endif
-# define machine_is_edb9315a() (machine_arch_type == MACH_TYPE_EDB9315A)
-#else
-# define machine_is_edb9315a() (0)
-#endif
-
-#ifdef CONFIG_MACH_STARGATE2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_STARGATE2
-# endif
-# define machine_is_stargate2() (machine_arch_type == MACH_TYPE_STARGATE2)
-#else
-# define machine_is_stargate2() (0)
-#endif
-
-#ifdef CONFIG_MACH_INTELMOTE2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_INTELMOTE2
-# endif
-# define machine_is_intelmote2() (machine_arch_type == MACH_TYPE_INTELMOTE2)
-#else
-# define machine_is_intelmote2() (0)
-#endif
-
-#ifdef CONFIG_MACH_TRIZEPS4
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TRIZEPS4
-# endif
-# define machine_is_trizeps4() (machine_arch_type == MACH_TYPE_TRIZEPS4)
-#else
-# define machine_is_trizeps4() (0)
-#endif
-
-#ifdef CONFIG_MACH_PNX4008
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PNX4008
-# endif
-# define machine_is_pnx4008() (machine_arch_type == MACH_TYPE_PNX4008)
-#else
-# define machine_is_pnx4008() (0)
-#endif
-
-#ifdef CONFIG_MACH_IQ81340SC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IQ81340SC
-# endif
-# define machine_is_iq81340sc() (machine_arch_type == MACH_TYPE_IQ81340SC)
-#else
-# define machine_is_iq81340sc() (0)
-#endif
-
-#ifdef CONFIG_MACH_IQ81340MC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IQ81340MC
-# endif
-# define machine_is_iq81340mc() (machine_arch_type == MACH_TYPE_IQ81340MC)
-#else
-# define machine_is_iq81340mc() (0)
-#endif
-
-#ifdef CONFIG_MACH_MICRO9
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MICRO9
-# endif
-# define machine_is_micro9() (machine_arch_type == MACH_TYPE_MICRO9)
-#else
-# define machine_is_micro9() (0)
-#endif
-
-#ifdef CONFIG_MACH_MICRO9L
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MICRO9L
-# endif
-# define machine_is_micro9l() (machine_arch_type == MACH_TYPE_MICRO9L)
-#else
-# define machine_is_micro9l() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PALMTE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_PALMTE
-# endif
-# define machine_is_omap_palmte() (machine_arch_type == MACH_TYPE_OMAP_PALMTE)
-#else
-# define machine_is_omap_palmte() (0)
-#endif
-
-#ifdef CONFIG_MACH_REALVIEW_EB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_REALVIEW_EB
-# endif
-# define machine_is_realview_eb() (machine_arch_type == MACH_TYPE_REALVIEW_EB)
-#else
-# define machine_is_realview_eb() (0)
-#endif
-
-#ifdef CONFIG_MACH_BORZOI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BORZOI
-# endif
-# define machine_is_borzoi() (machine_arch_type == MACH_TYPE_BORZOI)
-#else
-# define machine_is_borzoi() (0)
-#endif
-
-#ifdef CONFIG_MACH_PALMLD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PALMLD
-# endif
-# define machine_is_palmld() (machine_arch_type == MACH_TYPE_PALMLD)
-#else
-# define machine_is_palmld() (0)
-#endif
-
-#ifdef CONFIG_MACH_IXDP28X5
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IXDP28X5
-# endif
-# define machine_is_ixdp28x5() (machine_arch_type == MACH_TYPE_IXDP28X5)
-#else
-# define machine_is_ixdp28x5() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PALMTT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_PALMTT
-# endif
-# define machine_is_omap_palmtt() (machine_arch_type == MACH_TYPE_OMAP_PALMTT)
-#else
-# define machine_is_omap_palmtt() (0)
-#endif
-
-#ifdef CONFIG_MACH_ARCOM_ZEUS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ARCOM_ZEUS
-# endif
-# define machine_is_arcom_zeus() (machine_arch_type == MACH_TYPE_ARCOM_ZEUS)
-#else
-# define machine_is_arcom_zeus() (0)
-#endif
-
-#ifdef CONFIG_MACH_OSIRIS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OSIRIS
-# endif
-# define machine_is_osiris() (machine_arch_type == MACH_TYPE_OSIRIS)
-#else
-# define machine_is_osiris() (0)
-#endif
-
-#ifdef CONFIG_MACH_PALMTE2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PALMTE2
-# endif
-# define machine_is_palmte2() (machine_arch_type == MACH_TYPE_PALMTE2)
-#else
-# define machine_is_palmte2() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX27ADS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX27ADS
-# endif
-# define machine_is_mx27ads() (machine_arch_type == MACH_TYPE_MX27ADS)
-#else
-# define machine_is_mx27ads() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9261EK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91SAM9261EK
-# endif
-# define machine_is_at91sam9261ek() (machine_arch_type == MACH_TYPE_AT91SAM9261EK)
-#else
-# define machine_is_at91sam9261ek() (0)
-#endif
-
-#ifdef CONFIG_MACH_LOFT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LOFT
-# endif
-# define machine_is_loft() (machine_arch_type == MACH_TYPE_LOFT)
-#else
-# define machine_is_loft() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX21ADS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX21ADS
-# endif
-# define machine_is_mx21ads() (machine_arch_type == MACH_TYPE_MX21ADS)
-#else
-# define machine_is_mx21ads() (0)
-#endif
-
-#ifdef CONFIG_MACH_AMS_DELTA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AMS_DELTA
-# endif
-# define machine_is_ams_delta() (machine_arch_type == MACH_TYPE_AMS_DELTA)
-#else
-# define machine_is_ams_delta() (0)
-#endif
-
-#ifdef CONFIG_MACH_NAS100D
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NAS100D
-# endif
-# define machine_is_nas100d() (machine_arch_type == MACH_TYPE_NAS100D)
-#else
-# define machine_is_nas100d() (0)
-#endif
-
-#ifdef CONFIG_MACH_MAGICIAN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MAGICIAN
-# endif
-# define machine_is_magician() (machine_arch_type == MACH_TYPE_MAGICIAN)
-#else
-# define machine_is_magician() (0)
-#endif
-
-#ifdef CONFIG_MACH_NXDKN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NXDKN
-# endif
-# define machine_is_nxdkn() (machine_arch_type == MACH_TYPE_NXDKN)
-#else
-# define machine_is_nxdkn() (0)
-#endif
-
-#ifdef CONFIG_MACH_PALMTX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PALMTX
-# endif
-# define machine_is_palmtx() (machine_arch_type == MACH_TYPE_PALMTX)
-#else
-# define machine_is_palmtx() (0)
-#endif
-
-#ifdef CONFIG_MACH_S3C2413
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_S3C2413
-# endif
-# define machine_is_s3c2413() (machine_arch_type == MACH_TYPE_S3C2413)
-#else
-# define machine_is_s3c2413() (0)
-#endif
-
-#ifdef CONFIG_MACH_WG302V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WG302V2
-# endif
-# define machine_is_wg302v2() (machine_arch_type == MACH_TYPE_WG302V2)
-#else
-# define machine_is_wg302v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_2430SDP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_2430SDP
-# endif
-# define machine_is_omap_2430sdp() (machine_arch_type == MACH_TYPE_OMAP_2430SDP)
-#else
-# define machine_is_omap_2430sdp() (0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DAVINCI_EVM
-# endif
-# define machine_is_davinci_evm() (machine_arch_type == MACH_TYPE_DAVINCI_EVM)
-#else
-# define machine_is_davinci_evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_PALMZ72
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PALMZ72
-# endif
-# define machine_is_palmz72() (machine_arch_type == MACH_TYPE_PALMZ72)
-#else
-# define machine_is_palmz72() (0)
-#endif
-
-#ifdef CONFIG_MACH_NXDB500
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NXDB500
-# endif
-# define machine_is_nxdb500() (machine_arch_type == MACH_TYPE_NXDB500)
-#else
-# define machine_is_nxdb500() (0)
-#endif
-
-#ifdef CONFIG_MACH_PALMT5
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PALMT5
-# endif
-# define machine_is_palmt5() (machine_arch_type == MACH_TYPE_PALMT5)
-#else
-# define machine_is_palmt5() (0)
-#endif
-
-#ifdef CONFIG_MACH_PALMTC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PALMTC
-# endif
-# define machine_is_palmtc() (machine_arch_type == MACH_TYPE_PALMTC)
-#else
-# define machine_is_palmtc() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_APOLLON
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_APOLLON
-# endif
-# define machine_is_omap_apollon() (machine_arch_type == MACH_TYPE_OMAP_APOLLON)
-#else
-# define machine_is_omap_apollon() (0)
-#endif
-
-#ifdef CONFIG_MACH_ATEB9200
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ATEB9200
-# endif
-# define machine_is_ateb9200() (machine_arch_type == MACH_TYPE_ATEB9200)
-#else
-# define machine_is_ateb9200() (0)
-#endif
-
-#ifdef CONFIG_MACH_N35
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_N35
-# endif
-# define machine_is_n35() (machine_arch_type == MACH_TYPE_N35)
-#else
-# define machine_is_n35() (0)
-#endif
-
-#ifdef CONFIG_MACH_LOGICPD_PXA270
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LOGICPD_PXA270
-# endif
-# define machine_is_logicpd_pxa270() (machine_arch_type == MACH_TYPE_LOGICPD_PXA270)
-#else
-# define machine_is_logicpd_pxa270() (0)
-#endif
-
-#ifdef CONFIG_MACH_NXEB500HMI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NXEB500HMI
-# endif
-# define machine_is_nxeb500hmi() (machine_arch_type == MACH_TYPE_NXEB500HMI)
-#else
-# define machine_is_nxeb500hmi() (0)
-#endif
-
-#ifdef CONFIG_MACH_ESPRESSO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ESPRESSO
-# endif
-# define machine_is_espresso() (machine_arch_type == MACH_TYPE_ESPRESSO)
-#else
-# define machine_is_espresso() (0)
-#endif
-
-#ifdef CONFIG_MACH_RX1950
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RX1950
-# endif
-# define machine_is_rx1950() (machine_arch_type == MACH_TYPE_RX1950)
-#else
-# define machine_is_rx1950() (0)
-#endif
-
-#ifdef CONFIG_MACH_GESBC9312
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GESBC9312
-# endif
-# define machine_is_gesbc9312() (machine_arch_type == MACH_TYPE_GESBC9312)
-#else
-# define machine_is_gesbc9312() (0)
-#endif
-
-#ifdef CONFIG_MACH_PICOTUX2XX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PICOTUX2XX
-# endif
-# define machine_is_picotux2xx() (machine_arch_type == MACH_TYPE_PICOTUX2XX)
-#else
-# define machine_is_picotux2xx() (0)
-#endif
-
-#ifdef CONFIG_MACH_DSMG600
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DSMG600
-# endif
-# define machine_is_dsmg600() (machine_arch_type == MACH_TYPE_DSMG600)
-#else
-# define machine_is_dsmg600() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_FSAMPLE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_FSAMPLE
-# endif
-# define machine_is_omap_fsample() (machine_arch_type == MACH_TYPE_OMAP_FSAMPLE)
-#else
-# define machine_is_omap_fsample() (0)
-#endif
-
-#ifdef CONFIG_MACH_SNAPPER_CL15
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SNAPPER_CL15
-# endif
-# define machine_is_snapper_cl15() (machine_arch_type == MACH_TYPE_SNAPPER_CL15)
-#else
-# define machine_is_snapper_cl15() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_PALMZ71
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_PALMZ71
-# endif
-# define machine_is_omap_palmz71() (machine_arch_type == MACH_TYPE_OMAP_PALMZ71)
-#else
-# define machine_is_omap_palmz71() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2412
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDK2412
-# endif
-# define machine_is_smdk2412() (machine_arch_type == MACH_TYPE_SMDK2412)
-#else
-# define machine_is_smdk2412() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2413
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDK2413
-# endif
-# define machine_is_smdk2413() (machine_arch_type == MACH_TYPE_SMDK2413)
-#else
-# define machine_is_smdk2413() (0)
-#endif
-
-#ifdef CONFIG_MACH_AML_M5900
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AML_M5900
-# endif
-# define machine_is_aml_m5900() (machine_arch_type == MACH_TYPE_AML_M5900)
-#else
-# define machine_is_aml_m5900() (0)
-#endif
-
-#ifdef CONFIG_MACH_ECBAT91
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ECBAT91
-# endif
-# define machine_is_ecbat91() (machine_arch_type == MACH_TYPE_ECBAT91)
-#else
-# define machine_is_ecbat91() (0)
-#endif
-
-#ifdef CONFIG_MACH_ONEARM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ONEARM
-# endif
-# define machine_is_onearm() (machine_arch_type == MACH_TYPE_ONEARM)
-#else
-# define machine_is_onearm() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2443
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDK2443
-# endif
-# define machine_is_smdk2443() (machine_arch_type == MACH_TYPE_SMDK2443)
-#else
-# define machine_is_smdk2443() (0)
-#endif
-
-#ifdef CONFIG_MACH_FSG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FSG
-# endif
-# define machine_is_fsg() (machine_arch_type == MACH_TYPE_FSG)
-#else
-# define machine_is_fsg() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9260EK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91SAM9260EK
-# endif
-# define machine_is_at91sam9260ek() (machine_arch_type == MACH_TYPE_AT91SAM9260EK)
-#else
-# define machine_is_at91sam9260ek() (0)
-#endif
-
-#ifdef CONFIG_MACH_GLANTANK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GLANTANK
-# endif
-# define machine_is_glantank() (machine_arch_type == MACH_TYPE_GLANTANK)
-#else
-# define machine_is_glantank() (0)
-#endif
-
-#ifdef CONFIG_MACH_N2100
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_N2100
-# endif
-# define machine_is_n2100() (machine_arch_type == MACH_TYPE_N2100)
-#else
-# define machine_is_n2100() (0)
-#endif
-
-#ifdef CONFIG_MACH_QT2410
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_QT2410
-# endif
-# define machine_is_qt2410() (machine_arch_type == MACH_TYPE_QT2410)
-#else
-# define machine_is_qt2410() (0)
-#endif
-
-#ifdef CONFIG_MACH_KIXRP435
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KIXRP435
-# endif
-# define machine_is_kixrp435() (machine_arch_type == MACH_TYPE_KIXRP435)
-#else
-# define machine_is_kixrp435() (0)
-#endif
-
-#ifdef CONFIG_MACH_CC9P9360DEV
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CC9P9360DEV
-# endif
-# define machine_is_cc9p9360dev() (machine_arch_type == MACH_TYPE_CC9P9360DEV)
-#else
-# define machine_is_cc9p9360dev() (0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9302A
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EDB9302A
-# endif
-# define machine_is_edb9302a() (machine_arch_type == MACH_TYPE_EDB9302A)
-#else
-# define machine_is_edb9302a() (0)
-#endif
-
-#ifdef CONFIG_MACH_EDB9307A
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EDB9307A
-# endif
-# define machine_is_edb9307a() (machine_arch_type == MACH_TYPE_EDB9307A)
-#else
-# define machine_is_edb9307a() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_3430SDP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_3430SDP
-# endif
-# define machine_is_omap_3430sdp() (machine_arch_type == MACH_TYPE_OMAP_3430SDP)
-#else
-# define machine_is_omap_3430sdp() (0)
-#endif
-
-#ifdef CONFIG_MACH_VSTMS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VSTMS
-# endif
-# define machine_is_vstms() (machine_arch_type == MACH_TYPE_VSTMS)
-#else
-# define machine_is_vstms() (0)
-#endif
-
-#ifdef CONFIG_MACH_MICRO9M
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MICRO9M
-# endif
-# define machine_is_micro9m() (machine_arch_type == MACH_TYPE_MICRO9M)
-#else
-# define machine_is_micro9m() (0)
-#endif
-
-#ifdef CONFIG_MACH_BUG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BUG
-# endif
-# define machine_is_bug() (machine_arch_type == MACH_TYPE_BUG)
-#else
-# define machine_is_bug() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9263EK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91SAM9263EK
-# endif
-# define machine_is_at91sam9263ek() (machine_arch_type == MACH_TYPE_AT91SAM9263EK)
-#else
-# define machine_is_at91sam9263ek() (0)
-#endif
-
-#ifdef CONFIG_MACH_EM7210
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EM7210
-# endif
-# define machine_is_em7210() (machine_arch_type == MACH_TYPE_EM7210)
-#else
-# define machine_is_em7210() (0)
-#endif
-
-#ifdef CONFIG_MACH_VPAC270
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VPAC270
-# endif
-# define machine_is_vpac270() (machine_arch_type == MACH_TYPE_VPAC270)
-#else
-# define machine_is_vpac270() (0)
-#endif
-
-#ifdef CONFIG_MACH_TREO680
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TREO680
-# endif
-# define machine_is_treo680() (machine_arch_type == MACH_TYPE_TREO680)
-#else
-# define machine_is_treo680() (0)
-#endif
-
-#ifdef CONFIG_MACH_ZYLONITE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ZYLONITE
-# endif
-# define machine_is_zylonite() (machine_arch_type == MACH_TYPE_ZYLONITE)
-#else
-# define machine_is_zylonite() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX31LITE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX31LITE
-# endif
-# define machine_is_mx31lite() (machine_arch_type == MACH_TYPE_MX31LITE)
-#else
-# define machine_is_mx31lite() (0)
-#endif
-
-#ifdef CONFIG_MACH_MIOA701
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MIOA701
-# endif
-# define machine_is_mioa701() (machine_arch_type == MACH_TYPE_MIOA701)
-#else
-# define machine_is_mioa701() (0)
-#endif
-
-#ifdef CONFIG_MACH_ARMADILLO5X0
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ARMADILLO5X0
-# endif
-# define machine_is_armadillo5x0() (machine_arch_type == MACH_TYPE_ARMADILLO5X0)
-#else
-# define machine_is_armadillo5x0() (0)
-#endif
-
-#ifdef CONFIG_MACH_CC9P9360JS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CC9P9360JS
-# endif
-# define machine_is_cc9p9360js() (machine_arch_type == MACH_TYPE_CC9P9360JS)
-#else
-# define machine_is_cc9p9360js() (0)
-#endif
-
-#ifdef CONFIG_MACH_NOKIA_N800
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NOKIA_N800
-# endif
-# define machine_is_nokia_n800() (machine_arch_type == MACH_TYPE_NOKIA_N800)
-#else
-# define machine_is_nokia_n800() (0)
-#endif
-
-#ifdef CONFIG_MACH_EP80219
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EP80219
-# endif
-# define machine_is_ep80219() (machine_arch_type == MACH_TYPE_EP80219)
-#else
-# define machine_is_ep80219() (0)
-#endif
-
-#ifdef CONFIG_MACH_GORAMO_MLR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GORAMO_MLR
-# endif
-# define machine_is_goramo_mlr() (machine_arch_type == MACH_TYPE_GORAMO_MLR)
-#else
-# define machine_is_goramo_mlr() (0)
-#endif
-
-#ifdef CONFIG_MACH_EM_X270
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EM_X270
-# endif
-# define machine_is_em_x270() (machine_arch_type == MACH_TYPE_EM_X270)
-#else
-# define machine_is_em_x270() (0)
-#endif
-
-#ifdef CONFIG_MACH_NEO1973_GTA02
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NEO1973_GTA02
-# endif
-# define machine_is_neo1973_gta02() (machine_arch_type == MACH_TYPE_NEO1973_GTA02)
-#else
-# define machine_is_neo1973_gta02() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9RLEK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91SAM9RLEK
-# endif
-# define machine_is_at91sam9rlek() (machine_arch_type == MACH_TYPE_AT91SAM9RLEK)
-#else
-# define machine_is_at91sam9rlek() (0)
-#endif
-
-#ifdef CONFIG_MACH_COLIBRI320
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_COLIBRI320
-# endif
-# define machine_is_colibri320() (machine_arch_type == MACH_TYPE_COLIBRI320)
-#else
-# define machine_is_colibri320() (0)
-#endif
-
-#ifdef CONFIG_MACH_CAM60
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CAM60
-# endif
-# define machine_is_cam60() (machine_arch_type == MACH_TYPE_CAM60)
-#else
-# define machine_is_cam60() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91EB01
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91EB01
-# endif
-# define machine_is_at91eb01() (machine_arch_type == MACH_TYPE_AT91EB01)
-#else
-# define machine_is_at91eb01() (0)
-#endif
-
-#ifdef CONFIG_MACH_DB88F5281
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DB88F5281
-# endif
-# define machine_is_db88f5281() (machine_arch_type == MACH_TYPE_DB88F5281)
-#else
-# define machine_is_db88f5281() (0)
-#endif
-
-#ifdef CONFIG_MACH_CSB726
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CSB726
-# endif
-# define machine_is_csb726() (machine_arch_type == MACH_TYPE_CSB726)
-#else
-# define machine_is_csb726() (0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM6467_EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DAVINCI_DM6467_EVM
-# endif
-# define machine_is_davinci_dm6467_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467_EVM)
-#else
-# define machine_is_davinci_dm6467_evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM355_EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DAVINCI_DM355_EVM
-# endif
-# define machine_is_davinci_dm355_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM355_EVM)
-#else
-# define machine_is_davinci_dm355_evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_LITTLETON
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LITTLETON
-# endif
-# define machine_is_littleton() (machine_arch_type == MACH_TYPE_LITTLETON)
-#else
-# define machine_is_littleton() (0)
-#endif
-
-#ifdef CONFIG_MACH_REALVIEW_PB11MP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_REALVIEW_PB11MP
-# endif
-# define machine_is_realview_pb11mp() (machine_arch_type == MACH_TYPE_REALVIEW_PB11MP)
-#else
-# define machine_is_realview_pb11mp() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX27_3DS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX27_3DS
-# endif
-# define machine_is_mx27_3ds() (machine_arch_type == MACH_TYPE_MX27_3DS)
-#else
-# define machine_is_mx27_3ds() (0)
-#endif
-
-#ifdef CONFIG_MACH_HALIBUT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HALIBUT
-# endif
-# define machine_is_halibut() (machine_arch_type == MACH_TYPE_HALIBUT)
-#else
-# define machine_is_halibut() (0)
-#endif
-
-#ifdef CONFIG_MACH_TROUT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TROUT
-# endif
-# define machine_is_trout() (machine_arch_type == MACH_TYPE_TROUT)
-#else
-# define machine_is_trout() (0)
-#endif
-
-#ifdef CONFIG_MACH_TCT_HAMMER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TCT_HAMMER
-# endif
-# define machine_is_tct_hammer() (machine_arch_type == MACH_TYPE_TCT_HAMMER)
-#else
-# define machine_is_tct_hammer() (0)
-#endif
-
-#ifdef CONFIG_MACH_HERALD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HERALD
-# endif
-# define machine_is_herald() (machine_arch_type == MACH_TYPE_HERALD)
-#else
-# define machine_is_herald() (0)
-#endif
-
-#ifdef CONFIG_MACH_SIM_ONE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SIM_ONE
-# endif
-# define machine_is_sim_one() (machine_arch_type == MACH_TYPE_SIM_ONE)
-#else
-# define machine_is_sim_one() (0)
-#endif
-
-#ifdef CONFIG_MACH_JIVE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_JIVE
-# endif
-# define machine_is_jive() (machine_arch_type == MACH_TYPE_JIVE)
-#else
-# define machine_is_jive() (0)
-#endif
-
-#ifdef CONFIG_MACH_SAM9_L9260
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SAM9_L9260
-# endif
-# define machine_is_sam9_l9260() (machine_arch_type == MACH_TYPE_SAM9_L9260)
-#else
-# define machine_is_sam9_l9260() (0)
-#endif
-
-#ifdef CONFIG_MACH_REALVIEW_PB1176
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_REALVIEW_PB1176
-# endif
-# define machine_is_realview_pb1176() (machine_arch_type == MACH_TYPE_REALVIEW_PB1176)
-#else
-# define machine_is_realview_pb1176() (0)
-#endif
-
-#ifdef CONFIG_MACH_YL9200
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_YL9200
-# endif
-# define machine_is_yl9200() (machine_arch_type == MACH_TYPE_YL9200)
-#else
-# define machine_is_yl9200() (0)
-#endif
-
-#ifdef CONFIG_MACH_RD88F5182
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RD88F5182
-# endif
-# define machine_is_rd88f5182() (machine_arch_type == MACH_TYPE_RD88F5182)
-#else
-# define machine_is_rd88f5182() (0)
-#endif
-
-#ifdef CONFIG_MACH_KUROBOX_PRO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KUROBOX_PRO
-# endif
-# define machine_is_kurobox_pro() (machine_arch_type == MACH_TYPE_KUROBOX_PRO)
-#else
-# define machine_is_kurobox_pro() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX31_3DS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX31_3DS
-# endif
-# define machine_is_mx31_3ds() (machine_arch_type == MACH_TYPE_MX31_3DS)
-#else
-# define machine_is_mx31_3ds() (0)
-#endif
-
-#ifdef CONFIG_MACH_QONG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_QONG
-# endif
-# define machine_is_qong() (machine_arch_type == MACH_TYPE_QONG)
-#else
-# define machine_is_qong() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP2EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP2EVM
-# endif
-# define machine_is_omap2evm() (machine_arch_type == MACH_TYPE_OMAP2EVM)
-#else
-# define machine_is_omap2evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3EVM
-# endif
-# define machine_is_omap3evm() (machine_arch_type == MACH_TYPE_OMAP3EVM)
-#else
-# define machine_is_omap3evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_DNS323
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DNS323
-# endif
-# define machine_is_dns323() (machine_arch_type == MACH_TYPE_DNS323)
-#else
-# define machine_is_dns323() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_BEAGLE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3_BEAGLE
-# endif
-# define machine_is_omap3_beagle() (machine_arch_type == MACH_TYPE_OMAP3_BEAGLE)
-#else
-# define machine_is_omap3_beagle() (0)
-#endif
-
-#ifdef CONFIG_MACH_NOKIA_N810
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NOKIA_N810
-# endif
-# define machine_is_nokia_n810() (machine_arch_type == MACH_TYPE_NOKIA_N810)
-#else
-# define machine_is_nokia_n810() (0)
-#endif
-
-#ifdef CONFIG_MACH_PCM038
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PCM038
-# endif
-# define machine_is_pcm038() (machine_arch_type == MACH_TYPE_PCM038)
-#else
-# define machine_is_pcm038() (0)
-#endif
-
-#ifdef CONFIG_MACH_TS209
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TS209
-# endif
-# define machine_is_ts_x09() (machine_arch_type == MACH_TYPE_TS209)
-#else
-# define machine_is_ts_x09() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91CAP9ADK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91CAP9ADK
-# endif
-# define machine_is_at91cap9adk() (machine_arch_type == MACH_TYPE_AT91CAP9ADK)
-#else
-# define machine_is_at91cap9adk() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX31MOBOARD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX31MOBOARD
-# endif
-# define machine_is_mx31moboard() (machine_arch_type == MACH_TYPE_MX31MOBOARD)
-#else
-# define machine_is_mx31moboard() (0)
-#endif
-
-#ifdef CONFIG_MACH_TERASTATION_PRO2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TERASTATION_PRO2
-# endif
-# define machine_is_terastation_pro2() (machine_arch_type == MACH_TYPE_TERASTATION_PRO2)
-#else
-# define machine_is_terastation_pro2() (0)
-#endif
-
-#ifdef CONFIG_MACH_LINKSTATION_PRO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LINKSTATION_PRO
-# endif
-# define machine_is_linkstation_pro() (machine_arch_type == MACH_TYPE_LINKSTATION_PRO)
-#else
-# define machine_is_linkstation_pro() (0)
-#endif
-
-#ifdef CONFIG_MACH_E350
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_E350
-# endif
-# define machine_is_e350() (machine_arch_type == MACH_TYPE_E350)
-#else
-# define machine_is_e350() (0)
-#endif
-
-#ifdef CONFIG_MACH_TS409
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TS409
-# endif
-# define machine_is_ts409() (machine_arch_type == MACH_TYPE_TS409)
-#else
-# define machine_is_ts409() (0)
-#endif
-
-#ifdef CONFIG_MACH_CM_X300
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CM_X300
-# endif
-# define machine_is_cm_x300() (machine_arch_type == MACH_TYPE_CM_X300)
-#else
-# define machine_is_cm_x300() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9G20EK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91SAM9G20EK
-# endif
-# define machine_is_at91sam9g20ek() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK)
-#else
-# define machine_is_at91sam9g20ek() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK6410
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDK6410
-# endif
-# define machine_is_smdk6410() (machine_arch_type == MACH_TYPE_SMDK6410)
-#else
-# define machine_is_smdk6410() (0)
-#endif
-
-#ifdef CONFIG_MACH_U300
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_U300
-# endif
-# define machine_is_u300() (machine_arch_type == MACH_TYPE_U300)
-#else
-# define machine_is_u300() (0)
-#endif
-
-#ifdef CONFIG_MACH_WRT350N_V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WRT350N_V2
-# endif
-# define machine_is_wrt350n_v2() (machine_arch_type == MACH_TYPE_WRT350N_V2)
-#else
-# define machine_is_wrt350n_v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_LDP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_LDP
-# endif
-# define machine_is_omap_ldp() (machine_arch_type == MACH_TYPE_OMAP_LDP)
-#else
-# define machine_is_omap_ldp() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX35_3DS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX35_3DS
-# endif
-# define machine_is_mx35_3ds() (machine_arch_type == MACH_TYPE_MX35_3DS)
-#else
-# define machine_is_mx35_3ds() (0)
-#endif
-
-#ifdef CONFIG_MACH_NEUROS_OSD2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NEUROS_OSD2
-# endif
-# define machine_is_neuros_osd2() (machine_arch_type == MACH_TYPE_NEUROS_OSD2)
-#else
-# define machine_is_neuros_osd2() (0)
-#endif
-
-#ifdef CONFIG_MACH_TRIZEPS4WL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TRIZEPS4WL
-# endif
-# define machine_is_trizeps4wl() (machine_arch_type == MACH_TYPE_TRIZEPS4WL)
-#else
-# define machine_is_trizeps4wl() (0)
-#endif
-
-#ifdef CONFIG_MACH_TS78XX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TS78XX
-# endif
-# define machine_is_ts78xx() (machine_arch_type == MACH_TYPE_TS78XX)
-#else
-# define machine_is_ts78xx() (0)
-#endif
-
-#ifdef CONFIG_MACH_SFFSDR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SFFSDR
-# endif
-# define machine_is_sffsdr() (machine_arch_type == MACH_TYPE_SFFSDR)
-#else
-# define machine_is_sffsdr() (0)
-#endif
-
-#ifdef CONFIG_MACH_PCM037
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PCM037
-# endif
-# define machine_is_pcm037() (machine_arch_type == MACH_TYPE_PCM037)
-#else
-# define machine_is_pcm037() (0)
-#endif
-
-#ifdef CONFIG_MACH_DB88F6281_BP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DB88F6281_BP
-# endif
-# define machine_is_db88f6281_bp() (machine_arch_type == MACH_TYPE_DB88F6281_BP)
-#else
-# define machine_is_db88f6281_bp() (0)
-#endif
-
-#ifdef CONFIG_MACH_RD88F6192_NAS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RD88F6192_NAS
-# endif
-# define machine_is_rd88f6192_nas() (machine_arch_type == MACH_TYPE_RD88F6192_NAS)
-#else
-# define machine_is_rd88f6192_nas() (0)
-#endif
-
-#ifdef CONFIG_MACH_RD88F6281
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RD88F6281
-# endif
-# define machine_is_rd88f6281() (machine_arch_type == MACH_TYPE_RD88F6281)
-#else
-# define machine_is_rd88f6281() (0)
-#endif
-
-#ifdef CONFIG_MACH_DB78X00_BP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DB78X00_BP
-# endif
-# define machine_is_db78x00_bp() (machine_arch_type == MACH_TYPE_DB78X00_BP)
-#else
-# define machine_is_db78x00_bp() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK2416
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDK2416
-# endif
-# define machine_is_smdk2416() (machine_arch_type == MACH_TYPE_SMDK2416)
-#else
-# define machine_is_smdk2416() (0)
-#endif
-
-#ifdef CONFIG_MACH_WBD111
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WBD111
-# endif
-# define machine_is_wbd111() (machine_arch_type == MACH_TYPE_WBD111)
-#else
-# define machine_is_wbd111() (0)
-#endif
-
-#ifdef CONFIG_MACH_MV2120
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MV2120
-# endif
-# define machine_is_mv2120() (machine_arch_type == MACH_TYPE_MV2120)
-#else
-# define machine_is_mv2120() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_3DS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX51_3DS
-# endif
-# define machine_is_mx51_3ds() (machine_arch_type == MACH_TYPE_MX51_3DS)
-#else
-# define machine_is_mx51_3ds() (0)
-#endif
-
-#ifdef CONFIG_MACH_IMX27LITE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IMX27LITE
-# endif
-# define machine_is_imx27lite() (machine_arch_type == MACH_TYPE_IMX27LITE)
-#else
-# define machine_is_imx27lite() (0)
-#endif
-
-#ifdef CONFIG_MACH_USB_A9260
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_USB_A9260
-# endif
-# define machine_is_usb_a9260() (machine_arch_type == MACH_TYPE_USB_A9260)
-#else
-# define machine_is_usb_a9260() (0)
-#endif
-
-#ifdef CONFIG_MACH_USB_A9263
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_USB_A9263
-# endif
-# define machine_is_usb_a9263() (machine_arch_type == MACH_TYPE_USB_A9263)
-#else
-# define machine_is_usb_a9263() (0)
-#endif
-
-#ifdef CONFIG_MACH_QIL_A9260
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_QIL_A9260
-# endif
-# define machine_is_qil_a9260() (machine_arch_type == MACH_TYPE_QIL_A9260)
-#else
-# define machine_is_qil_a9260() (0)
-#endif
-
-#ifdef CONFIG_MACH_KZM_ARM11_01
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KZM_ARM11_01
-# endif
-# define machine_is_kzm_arm11_01() (machine_arch_type == MACH_TYPE_KZM_ARM11_01)
-#else
-# define machine_is_kzm_arm11_01() (0)
-#endif
-
-#ifdef CONFIG_MACH_NOKIA_N810_WIMAX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NOKIA_N810_WIMAX
-# endif
-# define machine_is_nokia_n810_wimax() (machine_arch_type == MACH_TYPE_NOKIA_N810_WIMAX)
-#else
-# define machine_is_nokia_n810_wimax() (0)
-#endif
-
-#ifdef CONFIG_MACH_SAPPHIRE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SAPPHIRE
-# endif
-# define machine_is_sapphire() (machine_arch_type == MACH_TYPE_SAPPHIRE)
-#else
-# define machine_is_sapphire() (0)
-#endif
-
-#ifdef CONFIG_MACH_STMP37XX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_STMP37XX
-# endif
-# define machine_is_stmp37xx() (machine_arch_type == MACH_TYPE_STMP37XX)
-#else
-# define machine_is_stmp37xx() (0)
-#endif
-
-#ifdef CONFIG_MACH_STMP378X
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_STMP378X
-# endif
-# define machine_is_stmp378x() (machine_arch_type == MACH_TYPE_STMP378X)
-#else
-# define machine_is_stmp378x() (0)
-#endif
-
-#ifdef CONFIG_MACH_EZX_A780
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EZX_A780
-# endif
-# define machine_is_ezx_a780() (machine_arch_type == MACH_TYPE_EZX_A780)
-#else
-# define machine_is_ezx_a780() (0)
-#endif
-
-#ifdef CONFIG_MACH_EZX_E680
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EZX_E680
-# endif
-# define machine_is_ezx_e680() (machine_arch_type == MACH_TYPE_EZX_E680)
-#else
-# define machine_is_ezx_e680() (0)
-#endif
-
-#ifdef CONFIG_MACH_EZX_A1200
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EZX_A1200
-# endif
-# define machine_is_ezx_a1200() (machine_arch_type == MACH_TYPE_EZX_A1200)
-#else
-# define machine_is_ezx_a1200() (0)
-#endif
-
-#ifdef CONFIG_MACH_EZX_E6
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EZX_E6
-# endif
-# define machine_is_ezx_e6() (machine_arch_type == MACH_TYPE_EZX_E6)
-#else
-# define machine_is_ezx_e6() (0)
-#endif
-
-#ifdef CONFIG_MACH_EZX_E2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EZX_E2
-# endif
-# define machine_is_ezx_e2() (machine_arch_type == MACH_TYPE_EZX_E2)
-#else
-# define machine_is_ezx_e2() (0)
-#endif
-
-#ifdef CONFIG_MACH_EZX_A910
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EZX_A910
-# endif
-# define machine_is_ezx_a910() (machine_arch_type == MACH_TYPE_EZX_A910)
-#else
-# define machine_is_ezx_a910() (0)
-#endif
-
-#ifdef CONFIG_MACH_EDMINI_V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EDMINI_V2
-# endif
-# define machine_is_edmini_v2() (machine_arch_type == MACH_TYPE_EDMINI_V2)
-#else
-# define machine_is_edmini_v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_ZIPIT2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ZIPIT2
-# endif
-# define machine_is_zipit2() (machine_arch_type == MACH_TYPE_ZIPIT2)
-#else
-# define machine_is_zipit2() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_PANDORA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3_PANDORA
-# endif
-# define machine_is_omap3_pandora() (machine_arch_type == MACH_TYPE_OMAP3_PANDORA)
-#else
-# define machine_is_omap3_pandora() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSS2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSS2
-# endif
-# define machine_is_mss2() (machine_arch_type == MACH_TYPE_MSS2)
-#else
-# define machine_is_mss2() (0)
-#endif
-
-#ifdef CONFIG_MACH_LB88RC8480
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LB88RC8480
-# endif
-# define machine_is_lb88rc8480() (machine_arch_type == MACH_TYPE_LB88RC8480)
-#else
-# define machine_is_lb88rc8480() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX25_3DS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX25_3DS
-# endif
-# define machine_is_mx25_3ds() (machine_arch_type == MACH_TYPE_MX25_3DS)
-#else
-# define machine_is_mx25_3ds() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3530_LV_SOM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3530_LV_SOM
-# endif
-# define machine_is_omap3530_lv_som() (machine_arch_type == MACH_TYPE_OMAP3530_LV_SOM)
-#else
-# define machine_is_omap3530_lv_som() (0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DA830_EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DAVINCI_DA830_EVM
-# endif
-# define machine_is_davinci_da830_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM)
-#else
-# define machine_is_davinci_da830_evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT572D940HFEB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT572D940HFEB
-# endif
-# define machine_is_at572d940hfek() (machine_arch_type == MACH_TYPE_AT572D940HFEB)
-#else
-# define machine_is_at572d940hfek() (0)
-#endif
-
-#ifdef CONFIG_MACH_DOVE_DB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DOVE_DB
-# endif
-# define machine_is_dove_db() (machine_arch_type == MACH_TYPE_DOVE_DB)
-#else
-# define machine_is_dove_db() (0)
-#endif
-
-#ifdef CONFIG_MACH_OVERO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OVERO
-# endif
-# define machine_is_overo() (machine_arch_type == MACH_TYPE_OVERO)
-#else
-# define machine_is_overo() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT2440EVB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT2440EVB
-# endif
-# define machine_is_at2440evb() (machine_arch_type == MACH_TYPE_AT2440EVB)
-#else
-# define machine_is_at2440evb() (0)
-#endif
-
-#ifdef CONFIG_MACH_NEOCORE926
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NEOCORE926
-# endif
-# define machine_is_neocore926() (machine_arch_type == MACH_TYPE_NEOCORE926)
-#else
-# define machine_is_neocore926() (0)
-#endif
-
-#ifdef CONFIG_MACH_WNR854T
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WNR854T
-# endif
-# define machine_is_wnr854t() (machine_arch_type == MACH_TYPE_WNR854T)
-#else
-# define machine_is_wnr854t() (0)
-#endif
-
-#ifdef CONFIG_MACH_RD88F5181L_GE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RD88F5181L_GE
-# endif
-# define machine_is_rd88f5181l_ge() (machine_arch_type == MACH_TYPE_RD88F5181L_GE)
-#else
-# define machine_is_rd88f5181l_ge() (0)
-#endif
-
-#ifdef CONFIG_MACH_RD88F5181L_FXO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RD88F5181L_FXO
-# endif
-# define machine_is_rd88f5181l_fxo() (machine_arch_type == MACH_TYPE_RD88F5181L_FXO)
-#else
-# define machine_is_rd88f5181l_fxo() (0)
-#endif
-
-#ifdef CONFIG_MACH_STAMP9G20
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_STAMP9G20
-# endif
-# define machine_is_stamp9g20() (machine_arch_type == MACH_TYPE_STAMP9G20)
-#else
-# define machine_is_stamp9g20() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMDKC100
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDKC100
-# endif
-# define machine_is_smdkc100() (machine_arch_type == MACH_TYPE_SMDKC100)
-#else
-# define machine_is_smdkc100() (0)
-#endif
-
-#ifdef CONFIG_MACH_TAVOREVB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TAVOREVB
-# endif
-# define machine_is_tavorevb() (machine_arch_type == MACH_TYPE_TAVOREVB)
-#else
-# define machine_is_tavorevb() (0)
-#endif
-
-#ifdef CONFIG_MACH_SAAR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SAAR
-# endif
-# define machine_is_saar() (machine_arch_type == MACH_TYPE_SAAR)
-#else
-# define machine_is_saar() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9M10G45EK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91SAM9M10G45EK
-# endif
-# define machine_is_at91sam9m10g45ek() (machine_arch_type == MACH_TYPE_AT91SAM9M10G45EK)
-#else
-# define machine_is_at91sam9m10g45ek() (0)
-#endif
-
-#ifdef CONFIG_MACH_MXLADS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MXLADS
-# endif
-# define machine_is_mxlads() (machine_arch_type == MACH_TYPE_MXLADS)
-#else
-# define machine_is_mxlads() (0)
-#endif
-
-#ifdef CONFIG_MACH_LINKSTATION_MINI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LINKSTATION_MINI
-# endif
-# define machine_is_linkstation_mini() (machine_arch_type == MACH_TYPE_LINKSTATION_MINI)
-#else
-# define machine_is_linkstation_mini() (0)
-#endif
-
-#ifdef CONFIG_MACH_AFEB9260
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AFEB9260
-# endif
-# define machine_is_afeb9260() (machine_arch_type == MACH_TYPE_AFEB9260)
-#else
-# define machine_is_afeb9260() (0)
-#endif
-
-#ifdef CONFIG_MACH_IMX27IPCAM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IMX27IPCAM
-# endif
-# define machine_is_imx27ipcam() (machine_arch_type == MACH_TYPE_IMX27IPCAM)
-#else
-# define machine_is_imx27ipcam() (0)
-#endif
-
-#ifdef CONFIG_MACH_RD88F6183AP_GE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RD88F6183AP_GE
-# endif
-# define machine_is_rd88f6183ap_ge() (machine_arch_type == MACH_TYPE_RD88F6183AP_GE)
-#else
-# define machine_is_rd88f6183ap_ge() (0)
-#endif
-
-#ifdef CONFIG_MACH_REALVIEW_PBA8
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_REALVIEW_PBA8
-# endif
-# define machine_is_realview_pba8() (machine_arch_type == MACH_TYPE_REALVIEW_PBA8)
-#else
-# define machine_is_realview_pba8() (0)
-#endif
-
-#ifdef CONFIG_MACH_REALVIEW_PBX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_REALVIEW_PBX
-# endif
-# define machine_is_realview_pbx() (machine_arch_type == MACH_TYPE_REALVIEW_PBX)
-#else
-# define machine_is_realview_pbx() (0)
-#endif
-
-#ifdef CONFIG_MACH_MICRO9S
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MICRO9S
-# endif
-# define machine_is_micro9s() (machine_arch_type == MACH_TYPE_MICRO9S)
-#else
-# define machine_is_micro9s() (0)
-#endif
-
-#ifdef CONFIG_MACH_RUT100
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RUT100
-# endif
-# define machine_is_rut100() (machine_arch_type == MACH_TYPE_RUT100)
-#else
-# define machine_is_rut100() (0)
-#endif
-
-#ifdef CONFIG_MACH_G3EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_G3EVM
-# endif
-# define machine_is_g3evm() (machine_arch_type == MACH_TYPE_G3EVM)
-#else
-# define machine_is_g3evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_W90P910EVB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_W90P910EVB
-# endif
-# define machine_is_w90p910evb() (machine_arch_type == MACH_TYPE_W90P910EVB)
-#else
-# define machine_is_w90p910evb() (0)
-#endif
-
-#ifdef CONFIG_MACH_W90P950EVB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_W90P950EVB
-# endif
-# define machine_is_w90p950evb() (machine_arch_type == MACH_TYPE_W90P950EVB)
-#else
-# define machine_is_w90p950evb() (0)
-#endif
-
-#ifdef CONFIG_MACH_W90N960EVB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_W90N960EVB
-# endif
-# define machine_is_w90n960evb() (machine_arch_type == MACH_TYPE_W90N960EVB)
-#else
-# define machine_is_w90n960evb() (0)
-#endif
-
-#ifdef CONFIG_MACH_MV88F6281GTW_GE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MV88F6281GTW_GE
-# endif
-# define machine_is_mv88f6281gtw_ge() (machine_arch_type == MACH_TYPE_MV88F6281GTW_GE)
-#else
-# define machine_is_mv88f6281gtw_ge() (0)
-#endif
-
-#ifdef CONFIG_MACH_NCP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NCP
-# endif
-# define machine_is_ncp() (machine_arch_type == MACH_TYPE_NCP)
-#else
-# define machine_is_ncp() (0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM365_EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DAVINCI_DM365_EVM
-# endif
-# define machine_is_davinci_dm365_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_EVM)
-#else
-# define machine_is_davinci_dm365_evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_CENTRO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CENTRO
-# endif
-# define machine_is_centro() (machine_arch_type == MACH_TYPE_CENTRO)
-#else
-# define machine_is_centro() (0)
-#endif
-
-#ifdef CONFIG_MACH_NOKIA_RX51
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NOKIA_RX51
-# endif
-# define machine_is_nokia_rx51() (machine_arch_type == MACH_TYPE_NOKIA_RX51)
-#else
-# define machine_is_nokia_rx51() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_ZOOM2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_ZOOM2
-# endif
-# define machine_is_omap_zoom2() (machine_arch_type == MACH_TYPE_OMAP_ZOOM2)
-#else
-# define machine_is_omap_zoom2() (0)
-#endif
-
-#ifdef CONFIG_MACH_ACS5K
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ACS5K
-# endif
-# define machine_is_acs5k() (machine_arch_type == MACH_TYPE_ACS5K)
-#else
-# define machine_is_acs5k() (0)
-#endif
-
-#ifdef CONFIG_MACH_SNAPPER_9260
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SNAPPER_9260
-# endif
-# define machine_is_snapper_9260() (machine_arch_type == MACH_TYPE_SNAPPER_9260)
-#else
-# define machine_is_snapper_9260() (0)
-#endif
-
-#ifdef CONFIG_MACH_DSM320
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DSM320
-# endif
-# define machine_is_dsm320() (machine_arch_type == MACH_TYPE_DSM320)
-#else
-# define machine_is_dsm320() (0)
-#endif
-
-#ifdef CONFIG_MACH_EXEDA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EXEDA
-# endif
-# define machine_is_exeda() (machine_arch_type == MACH_TYPE_EXEDA)
-#else
-# define machine_is_exeda() (0)
-#endif
-
-#ifdef CONFIG_MACH_MINI2440
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MINI2440
-# endif
-# define machine_is_mini2440() (machine_arch_type == MACH_TYPE_MINI2440)
-#else
-# define machine_is_mini2440() (0)
-#endif
-
-#ifdef CONFIG_MACH_COLIBRI300
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_COLIBRI300
-# endif
-# define machine_is_colibri300() (machine_arch_type == MACH_TYPE_COLIBRI300)
-#else
-# define machine_is_colibri300() (0)
-#endif
-
-#ifdef CONFIG_MACH_LINKSTATION_LS_HGL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LINKSTATION_LS_HGL
-# endif
-# define machine_is_linkstation_ls_hgl() (machine_arch_type == MACH_TYPE_LINKSTATION_LS_HGL)
-#else
-# define machine_is_linkstation_ls_hgl() (0)
-#endif
-
-#ifdef CONFIG_MACH_CPUAT9G20
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CPUAT9G20
-# endif
-# define machine_is_cpuat9g20() (machine_arch_type == MACH_TYPE_CPUAT9G20)
-#else
-# define machine_is_cpuat9g20() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK6440
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDK6440
-# endif
-# define machine_is_smdk6440() (machine_arch_type == MACH_TYPE_SMDK6440)
-#else
-# define machine_is_smdk6440() (0)
-#endif
-
-#ifdef CONFIG_MACH_NAS4220B
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NAS4220B
-# endif
-# define machine_is_nas4220b() (machine_arch_type == MACH_TYPE_NAS4220B)
-#else
-# define machine_is_nas4220b() (0)
-#endif
-
-#ifdef CONFIG_MACH_ZYLONITE2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ZYLONITE2
-# endif
-# define machine_is_zylonite2() (machine_arch_type == MACH_TYPE_ZYLONITE2)
-#else
-# define machine_is_zylonite2() (0)
-#endif
-
-#ifdef CONFIG_MACH_ASPENITE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ASPENITE
-# endif
-# define machine_is_aspenite() (machine_arch_type == MACH_TYPE_ASPENITE)
-#else
-# define machine_is_aspenite() (0)
-#endif
-
-#ifdef CONFIG_MACH_TTC_DKB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TTC_DKB
-# endif
-# define machine_is_ttc_dkb() (machine_arch_type == MACH_TYPE_TTC_DKB)
-#else
-# define machine_is_ttc_dkb() (0)
-#endif
-
-#ifdef CONFIG_MACH_PCM043
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PCM043
-# endif
-# define machine_is_pcm043() (machine_arch_type == MACH_TYPE_PCM043)
-#else
-# define machine_is_pcm043() (0)
-#endif
-
-#ifdef CONFIG_MACH_SHEEVAPLUG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SHEEVAPLUG
-# endif
-# define machine_is_sheevaplug() (machine_arch_type == MACH_TYPE_SHEEVAPLUG)
-#else
-# define machine_is_sheevaplug() (0)
-#endif
-
-#ifdef CONFIG_MACH_AVENGERS_LITE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AVENGERS_LITE
-# endif
-# define machine_is_avengers_lite() (machine_arch_type == MACH_TYPE_AVENGERS_LITE)
-#else
-# define machine_is_avengers_lite() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_BABBAGE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX51_BABBAGE
-# endif
-# define machine_is_mx51_babbage() (machine_arch_type == MACH_TYPE_MX51_BABBAGE)
-#else
-# define machine_is_mx51_babbage() (0)
-#endif
-
-#ifdef CONFIG_MACH_RD78X00_MASA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RD78X00_MASA
-# endif
-# define machine_is_rd78x00_masa() (machine_arch_type == MACH_TYPE_RD78X00_MASA)
-#else
-# define machine_is_rd78x00_masa() (0)
-#endif
-
-#ifdef CONFIG_MACH_DM355_LEOPARD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DM355_LEOPARD
-# endif
-# define machine_is_dm355_leopard() (machine_arch_type == MACH_TYPE_DM355_LEOPARD)
-#else
-# define machine_is_dm355_leopard() (0)
-#endif
-
-#ifdef CONFIG_MACH_TS219
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TS219
-# endif
-# define machine_is_ts219() (machine_arch_type == MACH_TYPE_TS219)
-#else
-# define machine_is_ts219() (0)
-#endif
-
-#ifdef CONFIG_MACH_PCA100
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PCA100
-# endif
-# define machine_is_pca100() (machine_arch_type == MACH_TYPE_PCA100)
-#else
-# define machine_is_pca100() (0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DA850_EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DAVINCI_DA850_EVM
-# endif
-# define machine_is_davinci_da850_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM)
-#else
-# define machine_is_davinci_da850_evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9G10EK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91SAM9G10EK
-# endif
-# define machine_is_at91sam9g10ek() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK)
-#else
-# define machine_is_at91sam9g10ek() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_4430SDP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_4430SDP
-# endif
-# define machine_is_omap_4430sdp() (machine_arch_type == MACH_TYPE_OMAP_4430SDP)
-#else
-# define machine_is_omap_4430sdp() (0)
-#endif
-
-#ifdef CONFIG_MACH_MAGX_ZN5
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MAGX_ZN5
-# endif
-# define machine_is_magx_zn5() (machine_arch_type == MACH_TYPE_MAGX_ZN5)
-#else
-# define machine_is_magx_zn5() (0)
-#endif
-
-#ifdef CONFIG_MACH_BTMAVB101
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BTMAVB101
-# endif
-# define machine_is_btmavb101() (machine_arch_type == MACH_TYPE_BTMAVB101)
-#else
-# define machine_is_btmavb101() (0)
-#endif
-
-#ifdef CONFIG_MACH_BTMAWB101
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BTMAWB101
-# endif
-# define machine_is_btmawb101() (machine_arch_type == MACH_TYPE_BTMAWB101)
-#else
-# define machine_is_btmawb101() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_TORPEDO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3_TORPEDO
-# endif
-# define machine_is_omap3_torpedo() (machine_arch_type == MACH_TYPE_OMAP3_TORPEDO)
-#else
-# define machine_is_omap3_torpedo() (0)
-#endif
-
-#ifdef CONFIG_MACH_ANW6410
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ANW6410
-# endif
-# define machine_is_anw6410() (machine_arch_type == MACH_TYPE_ANW6410)
-#else
-# define machine_is_anw6410() (0)
-#endif
-
-#ifdef CONFIG_MACH_IMX27_VISSTRIM_M10
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IMX27_VISSTRIM_M10
-# endif
-# define machine_is_imx27_visstrim_m10() (machine_arch_type == MACH_TYPE_IMX27_VISSTRIM_M10)
-#else
-# define machine_is_imx27_visstrim_m10() (0)
-#endif
-
-#ifdef CONFIG_MACH_PORTUXG20
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PORTUXG20
-# endif
-# define machine_is_portuxg20() (machine_arch_type == MACH_TYPE_PORTUXG20)
-#else
-# define machine_is_portuxg20() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMDKC110
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDKC110
-# endif
-# define machine_is_smdkc110() (machine_arch_type == MACH_TYPE_SMDKC110)
-#else
-# define machine_is_smdkc110() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3517EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3517EVM
-# endif
-# define machine_is_omap3517evm() (machine_arch_type == MACH_TYPE_OMAP3517EVM)
-#else
-# define machine_is_omap3517evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_NETSPACE_V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NETSPACE_V2
-# endif
-# define machine_is_netspace_v2() (machine_arch_type == MACH_TYPE_NETSPACE_V2)
-#else
-# define machine_is_netspace_v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_NETSPACE_MAX_V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NETSPACE_MAX_V2
-# endif
-# define machine_is_netspace_max_v2() (machine_arch_type == MACH_TYPE_NETSPACE_MAX_V2)
-#else
-# define machine_is_netspace_max_v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_D2NET_V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_D2NET_V2
-# endif
-# define machine_is_d2net_v2() (machine_arch_type == MACH_TYPE_D2NET_V2)
-#else
-# define machine_is_d2net_v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_NET2BIG_V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NET2BIG_V2
-# endif
-# define machine_is_net2big_v2() (machine_arch_type == MACH_TYPE_NET2BIG_V2)
-#else
-# define machine_is_net2big_v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_NET5BIG_V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NET5BIG_V2
-# endif
-# define machine_is_net5big_v2() (machine_arch_type == MACH_TYPE_NET5BIG_V2)
-#else
-# define machine_is_net5big_v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_INETSPACE_V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_INETSPACE_V2
-# endif
-# define machine_is_inetspace_v2() (machine_arch_type == MACH_TYPE_INETSPACE_V2)
-#else
-# define machine_is_inetspace_v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9G45EKES
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91SAM9G45EKES
-# endif
-# define machine_is_at91sam9g45ekes() (machine_arch_type == MACH_TYPE_AT91SAM9G45EKES)
-#else
-# define machine_is_at91sam9g45ekes() (0)
-#endif
-
-#ifdef CONFIG_MACH_PC7302
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PC7302
-# endif
-# define machine_is_pc7302() (machine_arch_type == MACH_TYPE_PC7302)
-#else
-# define machine_is_pc7302() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPEAR600
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPEAR600
-# endif
-# define machine_is_spear600() (machine_arch_type == MACH_TYPE_SPEAR600)
-#else
-# define machine_is_spear600() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPEAR300
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPEAR300
-# endif
-# define machine_is_spear300() (machine_arch_type == MACH_TYPE_SPEAR300)
-#else
-# define machine_is_spear300() (0)
-#endif
-
-#ifdef CONFIG_MACH_LILLY1131
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LILLY1131
-# endif
-# define machine_is_lilly1131() (machine_arch_type == MACH_TYPE_LILLY1131)
-#else
-# define machine_is_lilly1131() (0)
-#endif
-
-#ifdef CONFIG_MACH_HMT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HMT
-# endif
-# define machine_is_hmt() (machine_arch_type == MACH_TYPE_HMT)
-#else
-# define machine_is_hmt() (0)
-#endif
-
-#ifdef CONFIG_MACH_VEXPRESS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VEXPRESS
-# endif
-# define machine_is_vexpress() (machine_arch_type == MACH_TYPE_VEXPRESS)
-#else
-# define machine_is_vexpress() (0)
-#endif
-
-#ifdef CONFIG_MACH_D2NET
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_D2NET
-# endif
-# define machine_is_d2net() (machine_arch_type == MACH_TYPE_D2NET)
-#else
-# define machine_is_d2net() (0)
-#endif
-
-#ifdef CONFIG_MACH_BIGDISK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BIGDISK
-# endif
-# define machine_is_bigdisk() (machine_arch_type == MACH_TYPE_BIGDISK)
-#else
-# define machine_is_bigdisk() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9G20EK_2MMC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91SAM9G20EK_2MMC
-# endif
-# define machine_is_at91sam9g20ek_2mmc() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK_2MMC)
-#else
-# define machine_is_at91sam9g20ek_2mmc() (0)
-#endif
-
-#ifdef CONFIG_MACH_BCMRING
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BCMRING
-# endif
-# define machine_is_bcmring() (machine_arch_type == MACH_TYPE_BCMRING)
-#else
-# define machine_is_bcmring() (0)
-#endif
-
-#ifdef CONFIG_MACH_DP6XX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DP6XX
-# endif
-# define machine_is_dp6xx() (machine_arch_type == MACH_TYPE_DP6XX)
-#else
-# define machine_is_dp6xx() (0)
-#endif
-
-#ifdef CONFIG_MACH_MAHIMAHI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MAHIMAHI
-# endif
-# define machine_is_mahimahi() (machine_arch_type == MACH_TYPE_MAHIMAHI)
-#else
-# define machine_is_mahimahi() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK6442
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDK6442
-# endif
-# define machine_is_smdk6442() (machine_arch_type == MACH_TYPE_SMDK6442)
-#else
-# define machine_is_smdk6442() (0)
-#endif
-
-#ifdef CONFIG_MACH_OPENRD_BASE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OPENRD_BASE
-# endif
-# define machine_is_openrd_base() (machine_arch_type == MACH_TYPE_OPENRD_BASE)
-#else
-# define machine_is_openrd_base() (0)
-#endif
-
-#ifdef CONFIG_MACH_DEVKIT8000
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DEVKIT8000
-# endif
-# define machine_is_devkit8000() (machine_arch_type == MACH_TYPE_DEVKIT8000)
-#else
-# define machine_is_devkit8000() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_EFIKAMX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX51_EFIKAMX
-# endif
-# define machine_is_mx51_efikamx() (machine_arch_type == MACH_TYPE_MX51_EFIKAMX)
-#else
-# define machine_is_mx51_efikamx() (0)
-#endif
-
-#ifdef CONFIG_MACH_CM_T35
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CM_T35
-# endif
-# define machine_is_cm_t35() (machine_arch_type == MACH_TYPE_CM_T35)
-#else
-# define machine_is_cm_t35() (0)
-#endif
-
-#ifdef CONFIG_MACH_NET2BIG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NET2BIG
-# endif
-# define machine_is_net2big() (machine_arch_type == MACH_TYPE_NET2BIG)
-#else
-# define machine_is_net2big() (0)
-#endif
-
-#ifdef CONFIG_MACH_IGEP0020
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IGEP0020
-# endif
-# define machine_is_igep0020() (machine_arch_type == MACH_TYPE_IGEP0020)
-#else
-# define machine_is_igep0020() (0)
-#endif
-
-#ifdef CONFIG_MACH_NUC932EVB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NUC932EVB
-# endif
-# define machine_is_nuc932evb() (machine_arch_type == MACH_TYPE_NUC932EVB)
-#else
-# define machine_is_nuc932evb() (0)
-#endif
-
-#ifdef CONFIG_MACH_OPENRD_CLIENT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OPENRD_CLIENT
-# endif
-# define machine_is_openrd_client() (machine_arch_type == MACH_TYPE_OPENRD_CLIENT)
-#else
-# define machine_is_openrd_client() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_EFIKASB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX51_EFIKASB
-# endif
-# define machine_is_mx51_efikasb() (machine_arch_type == MACH_TYPE_MX51_EFIKASB)
-#else
-# define machine_is_mx51_efikasb() (0)
-#endif
-
-#ifdef CONFIG_MACH_MARVELL_JASPER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MARVELL_JASPER
-# endif
-# define machine_is_marvell_jasper() (machine_arch_type == MACH_TYPE_MARVELL_JASPER)
-#else
-# define machine_is_marvell_jasper() (0)
-#endif
-
-#ifdef CONFIG_MACH_FLINT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FLINT
-# endif
-# define machine_is_flint() (machine_arch_type == MACH_TYPE_FLINT)
-#else
-# define machine_is_flint() (0)
-#endif
-
-#ifdef CONFIG_MACH_TAVOREVB3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TAVOREVB3
-# endif
-# define machine_is_tavorevb3() (machine_arch_type == MACH_TYPE_TAVOREVB3)
-#else
-# define machine_is_tavorevb3() (0)
-#endif
-
-#ifdef CONFIG_MACH_TOUCHBOOK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TOUCHBOOK
-# endif
-# define machine_is_touchbook() (machine_arch_type == MACH_TYPE_TOUCHBOOK)
-#else
-# define machine_is_touchbook() (0)
-#endif
-
-#ifdef CONFIG_MACH_RAUMFELD_RC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RAUMFELD_RC
-# endif
-# define machine_is_raumfeld_rc() (machine_arch_type == MACH_TYPE_RAUMFELD_RC)
-#else
-# define machine_is_raumfeld_rc() (0)
-#endif
-
-#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RAUMFELD_CONNECTOR
-# endif
-# define machine_is_raumfeld_connector() (machine_arch_type == MACH_TYPE_RAUMFELD_CONNECTOR)
-#else
-# define machine_is_raumfeld_connector() (0)
-#endif
-
-#ifdef CONFIG_MACH_RAUMFELD_SPEAKER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RAUMFELD_SPEAKER
-# endif
-# define machine_is_raumfeld_speaker() (machine_arch_type == MACH_TYPE_RAUMFELD_SPEAKER)
-#else
-# define machine_is_raumfeld_speaker() (0)
-#endif
-
-#ifdef CONFIG_MACH_TNETV107X
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TNETV107X
-# endif
-# define machine_is_tnetv107x() (machine_arch_type == MACH_TYPE_TNETV107X)
-#else
-# define machine_is_tnetv107x() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMDKV210
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDKV210
-# endif
-# define machine_is_smdkv210() (machine_arch_type == MACH_TYPE_SMDKV210)
-#else
-# define machine_is_smdkv210() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_ZOOM3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_ZOOM3
-# endif
-# define machine_is_omap_zoom3() (machine_arch_type == MACH_TYPE_OMAP_ZOOM3)
-#else
-# define machine_is_omap_zoom3() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_3630SDP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_3630SDP
-# endif
-# define machine_is_omap_3630sdp() (machine_arch_type == MACH_TYPE_OMAP_3630SDP)
-#else
-# define machine_is_omap_3630sdp() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMARTQ7
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMARTQ7
-# endif
-# define machine_is_smartq7() (machine_arch_type == MACH_TYPE_SMARTQ7)
-#else
-# define machine_is_smartq7() (0)
-#endif
-
-#ifdef CONFIG_MACH_WATSON_EFM_PLUGIN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WATSON_EFM_PLUGIN
-# endif
-# define machine_is_watson_efm_plugin() (machine_arch_type == MACH_TYPE_WATSON_EFM_PLUGIN)
-#else
-# define machine_is_watson_efm_plugin() (0)
-#endif
-
-#ifdef CONFIG_MACH_G4EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_G4EVM
-# endif
-# define machine_is_g4evm() (machine_arch_type == MACH_TYPE_G4EVM)
-#else
-# define machine_is_g4evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAPL138_HAWKBOARD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAPL138_HAWKBOARD
-# endif
-# define machine_is_omapl138_hawkboard() (machine_arch_type == MACH_TYPE_OMAPL138_HAWKBOARD)
-#else
-# define machine_is_omapl138_hawkboard() (0)
-#endif
-
-#ifdef CONFIG_MACH_TS41X
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TS41X
-# endif
-# define machine_is_ts41x() (machine_arch_type == MACH_TYPE_TS41X)
-#else
-# define machine_is_ts41x() (0)
-#endif
-
-#ifdef CONFIG_MACH_PHY3250
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PHY3250
-# endif
-# define machine_is_phy3250() (machine_arch_type == MACH_TYPE_PHY3250)
-#else
-# define machine_is_phy3250() (0)
-#endif
-
-#ifdef CONFIG_MACH_MINI6410
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MINI6410
-# endif
-# define machine_is_mini6410() (machine_arch_type == MACH_TYPE_MINI6410)
-#else
-# define machine_is_mini6410() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX28EVK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX28EVK
-# endif
-# define machine_is_mx28evk() (machine_arch_type == MACH_TYPE_MX28EVK)
-#else
-# define machine_is_mx28evk() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMARTQ5
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMARTQ5
-# endif
-# define machine_is_smartq5() (machine_arch_type == MACH_TYPE_SMARTQ5)
-#else
-# define machine_is_smartq5() (0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM6467TEVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DAVINCI_DM6467TEVM
-# endif
-# define machine_is_davinci_dm6467tevm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467TEVM)
-#else
-# define machine_is_davinci_dm6467tevm() (0)
-#endif
-
-#ifdef CONFIG_MACH_MXT_TD60
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MXT_TD60
-# endif
-# define machine_is_mxt_td60() (machine_arch_type == MACH_TYPE_MXT_TD60)
-#else
-# define machine_is_mxt_td60() (0)
-#endif
-
-#ifdef CONFIG_MACH_RIOT_BEI2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RIOT_BEI2
-# endif
-# define machine_is_riot_bei2() (machine_arch_type == MACH_TYPE_RIOT_BEI2)
-#else
-# define machine_is_riot_bei2() (0)
-#endif
-
-#ifdef CONFIG_MACH_RIOT_X37
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RIOT_X37
-# endif
-# define machine_is_riot_x37() (machine_arch_type == MACH_TYPE_RIOT_X37)
-#else
-# define machine_is_riot_x37() (0)
-#endif
-
-#ifdef CONFIG_MACH_CAPC7117
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CAPC7117
-# endif
-# define machine_is_capc7117() (machine_arch_type == MACH_TYPE_CAPC7117)
-#else
-# define machine_is_capc7117() (0)
-#endif
-
-#ifdef CONFIG_MACH_ICONTROL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ICONTROL
-# endif
-# define machine_is_icontrol() (machine_arch_type == MACH_TYPE_ICONTROL)
-#else
-# define machine_is_icontrol() (0)
-#endif
-
-#ifdef CONFIG_MACH_QSD8X50A_ST1_5
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_QSD8X50A_ST1_5
-# endif
-# define machine_is_qsd8x50a_st1_5() (machine_arch_type == MACH_TYPE_QSD8X50A_ST1_5)
-#else
-# define machine_is_qsd8x50a_st1_5() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX23EVK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX23EVK
-# endif
-# define machine_is_mx23evk() (machine_arch_type == MACH_TYPE_MX23EVK)
-#else
-# define machine_is_mx23evk() (0)
-#endif
-
-#ifdef CONFIG_MACH_AP4EVB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AP4EVB
-# endif
-# define machine_is_ap4evb() (machine_arch_type == MACH_TYPE_AP4EVB)
-#else
-# define machine_is_ap4evb() (0)
-#endif
-
-#ifdef CONFIG_MACH_MITYOMAPL138
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MITYOMAPL138
-# endif
-# define machine_is_mityomapl138() (machine_arch_type == MACH_TYPE_MITYOMAPL138)
-#else
-# define machine_is_mityomapl138() (0)
-#endif
-
-#ifdef CONFIG_MACH_GURUPLUG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GURUPLUG
-# endif
-# define machine_is_guruplug() (machine_arch_type == MACH_TYPE_GURUPLUG)
-#else
-# define machine_is_guruplug() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPEAR310
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPEAR310
-# endif
-# define machine_is_spear310() (machine_arch_type == MACH_TYPE_SPEAR310)
-#else
-# define machine_is_spear310() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPEAR320
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPEAR320
-# endif
-# define machine_is_spear320() (machine_arch_type == MACH_TYPE_SPEAR320)
-#else
-# define machine_is_spear320() (0)
-#endif
-
-#ifdef CONFIG_MACH_AQUILA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AQUILA
-# endif
-# define machine_is_aquila() (machine_arch_type == MACH_TYPE_AQUILA)
-#else
-# define machine_is_aquila() (0)
-#endif
-
-#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ESATA_SHEEVAPLUG
-# endif
-# define machine_is_sheeva_esata() (machine_arch_type == MACH_TYPE_ESATA_SHEEVAPLUG)
-#else
-# define machine_is_sheeva_esata() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X30_SURF
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM7X30_SURF
-# endif
-# define machine_is_msm7x30_surf() (machine_arch_type == MACH_TYPE_MSM7X30_SURF)
-#else
-# define machine_is_msm7x30_surf() (0)
-#endif
-
-#ifdef CONFIG_MACH_EA2478DEVKIT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EA2478DEVKIT
-# endif
-# define machine_is_ea2478devkit() (machine_arch_type == MACH_TYPE_EA2478DEVKIT)
-#else
-# define machine_is_ea2478devkit() (0)
-#endif
-
-#ifdef CONFIG_MACH_TERASTATION_WXL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TERASTATION_WXL
-# endif
-# define machine_is_terastation_wxl() (machine_arch_type == MACH_TYPE_TERASTATION_WXL)
-#else
-# define machine_is_terastation_wxl() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X25_SURF
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM7X25_SURF
-# endif
-# define machine_is_msm7x25_surf() (machine_arch_type == MACH_TYPE_MSM7X25_SURF)
-#else
-# define machine_is_msm7x25_surf() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X25_FFA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM7X25_FFA
-# endif
-# define machine_is_msm7x25_ffa() (machine_arch_type == MACH_TYPE_MSM7X25_FFA)
-#else
-# define machine_is_msm7x25_ffa() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X27_SURF
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM7X27_SURF
-# endif
-# define machine_is_msm7x27_surf() (machine_arch_type == MACH_TYPE_MSM7X27_SURF)
-#else
-# define machine_is_msm7x27_surf() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X27_FFA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM7X27_FFA
-# endif
-# define machine_is_msm7x27_ffa() (machine_arch_type == MACH_TYPE_MSM7X27_FFA)
-#else
-# define machine_is_msm7x27_ffa() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X30_FFA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM7X30_FFA
-# endif
-# define machine_is_msm7x30_ffa() (machine_arch_type == MACH_TYPE_MSM7X30_FFA)
-#else
-# define machine_is_msm7x30_ffa() (0)
-#endif
-
-#ifdef CONFIG_MACH_QSD8X50_SURF
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_QSD8X50_SURF
-# endif
-# define machine_is_qsd8x50_surf() (machine_arch_type == MACH_TYPE_QSD8X50_SURF)
-#else
-# define machine_is_qsd8x50_surf() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX53_EVK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX53_EVK
-# endif
-# define machine_is_mx53_evk() (machine_arch_type == MACH_TYPE_MX53_EVK)
-#else
-# define machine_is_mx53_evk() (0)
-#endif
-
-#ifdef CONFIG_MACH_IGEP0030
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IGEP0030
-# endif
-# define machine_is_igep0030() (machine_arch_type == MACH_TYPE_IGEP0030)
-#else
-# define machine_is_igep0030() (0)
-#endif
-
-#ifdef CONFIG_MACH_SBC3530
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SBC3530
-# endif
-# define machine_is_sbc3530() (machine_arch_type == MACH_TYPE_SBC3530)
-#else
-# define machine_is_sbc3530() (0)
-#endif
-
-#ifdef CONFIG_MACH_SAARB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SAARB
-# endif
-# define machine_is_saarb() (machine_arch_type == MACH_TYPE_SAARB)
-#else
-# define machine_is_saarb() (0)
-#endif
-
-#ifdef CONFIG_MACH_HARMONY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HARMONY
-# endif
-# define machine_is_harmony() (machine_arch_type == MACH_TYPE_HARMONY)
-#else
-# define machine_is_harmony() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X30_FLUID
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM7X30_FLUID
-# endif
-# define machine_is_msm7x30_fluid() (machine_arch_type == MACH_TYPE_MSM7X30_FLUID)
-#else
-# define machine_is_msm7x30_fluid() (0)
-#endif
-
-#ifdef CONFIG_MACH_CM_T3517
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CM_T3517
-# endif
-# define machine_is_cm_t3517() (machine_arch_type == MACH_TYPE_CM_T3517)
-#else
-# define machine_is_cm_t3517() (0)
-#endif
-
-#ifdef CONFIG_MACH_WBD222
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WBD222
-# endif
-# define machine_is_wbd222() (machine_arch_type == MACH_TYPE_WBD222)
-#else
-# define machine_is_wbd222() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_SURF
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8X60_SURF
-# endif
-# define machine_is_msm8x60_surf() (machine_arch_type == MACH_TYPE_MSM8X60_SURF)
-#else
-# define machine_is_msm8x60_surf() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_SIM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8X60_SIM
-# endif
-# define machine_is_msm8x60_sim() (machine_arch_type == MACH_TYPE_MSM8X60_SIM)
-#else
-# define machine_is_msm8x60_sim() (0)
-#endif
-
-#ifdef CONFIG_MACH_TCC8000_SDK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TCC8000_SDK
-# endif
-# define machine_is_tcc8000_sdk() (machine_arch_type == MACH_TYPE_TCC8000_SDK)
-#else
-# define machine_is_tcc8000_sdk() (0)
-#endif
-
-#ifdef CONFIG_MACH_NANOS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NANOS
-# endif
-# define machine_is_nanos() (machine_arch_type == MACH_TYPE_NANOS)
-#else
-# define machine_is_nanos() (0)
-#endif
-
-#ifdef CONFIG_MACH_STAMP9G45
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_STAMP9G45
-# endif
-# define machine_is_stamp9g45() (machine_arch_type == MACH_TYPE_STAMP9G45)
-#else
-# define machine_is_stamp9g45() (0)
-#endif
-
-#ifdef CONFIG_MACH_CNS3420VB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CNS3420VB
-# endif
-# define machine_is_cns3420vb() (machine_arch_type == MACH_TYPE_CNS3420VB)
-#else
-# define machine_is_cns3420vb() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP4_PANDA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP4_PANDA
-# endif
-# define machine_is_omap4_panda() (machine_arch_type == MACH_TYPE_OMAP4_PANDA)
-#else
-# define machine_is_omap4_panda() (0)
-#endif
-
-#ifdef CONFIG_MACH_TI8168EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TI8168EVM
-# endif
-# define machine_is_ti8168evm() (machine_arch_type == MACH_TYPE_TI8168EVM)
-#else
-# define machine_is_ti8168evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_TETON_BGA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TETON_BGA
-# endif
-# define machine_is_teton_bga() (machine_arch_type == MACH_TYPE_TETON_BGA)
-#else
-# define machine_is_teton_bga() (0)
-#endif
-
-#ifdef CONFIG_MACH_EUKREA_CPUIMX25SD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX25SD
-# endif
-# define machine_is_eukrea_cpuimx25sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX25SD)
-#else
-# define machine_is_eukrea_cpuimx25sd() (0)
-#endif
-
-#ifdef CONFIG_MACH_EUKREA_CPUIMX35SD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX35SD
-# endif
-# define machine_is_eukrea_cpuimx35sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX35SD)
-#else
-# define machine_is_eukrea_cpuimx35sd() (0)
-#endif
-
-#ifdef CONFIG_MACH_EUKREA_CPUIMX51SD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX51SD
-# endif
-# define machine_is_eukrea_cpuimx51sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51SD)
-#else
-# define machine_is_eukrea_cpuimx51sd() (0)
-#endif
-
-#ifdef CONFIG_MACH_EUKREA_CPUIMX51
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX51
-# endif
-# define machine_is_eukrea_cpuimx51() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51)
-#else
-# define machine_is_eukrea_cpuimx51() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMDKC210
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDKC210
-# endif
-# define machine_is_smdkc210() (machine_arch_type == MACH_TYPE_SMDKC210)
-#else
-# define machine_is_smdkc210() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_BRAILLO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3_BRAILLO
-# endif
-# define machine_is_omap3_braillo() (machine_arch_type == MACH_TYPE_OMAP3_BRAILLO)
-#else
-# define machine_is_omap3_braillo() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPYPLUG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPYPLUG
-# endif
-# define machine_is_spyplug() (machine_arch_type == MACH_TYPE_SPYPLUG)
-#else
-# define machine_is_spyplug() (0)
-#endif
-
-#ifdef CONFIG_MACH_GINGER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GINGER
-# endif
-# define machine_is_ginger() (machine_arch_type == MACH_TYPE_GINGER)
-#else
-# define machine_is_ginger() (0)
-#endif
-
-#ifdef CONFIG_MACH_TNY_T3530
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TNY_T3530
-# endif
-# define machine_is_tny_t3530() (machine_arch_type == MACH_TYPE_TNY_T3530)
-#else
-# define machine_is_tny_t3530() (0)
-#endif
-
-#ifdef CONFIG_MACH_PCA102
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PCA102
-# endif
-# define machine_is_pca102() (machine_arch_type == MACH_TYPE_PCA102)
-#else
-# define machine_is_pca102() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPADE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPADE
-# endif
-# define machine_is_spade() (machine_arch_type == MACH_TYPE_SPADE)
-#else
-# define machine_is_spade() (0)
-#endif
-
-#ifdef CONFIG_MACH_MXC25_TOPAZ
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MXC25_TOPAZ
-# endif
-# define machine_is_mxc25_topaz() (machine_arch_type == MACH_TYPE_MXC25_TOPAZ)
-#else
-# define machine_is_mxc25_topaz() (0)
-#endif
-
-#ifdef CONFIG_MACH_T5325
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_T5325
-# endif
-# define machine_is_t5325() (machine_arch_type == MACH_TYPE_T5325)
-#else
-# define machine_is_t5325() (0)
-#endif
-
-#ifdef CONFIG_MACH_GW2361
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GW2361
-# endif
-# define machine_is_gw2361() (machine_arch_type == MACH_TYPE_GW2361)
-#else
-# define machine_is_gw2361() (0)
-#endif
-
-#ifdef CONFIG_MACH_ELOG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ELOG
-# endif
-# define machine_is_elog() (machine_arch_type == MACH_TYPE_ELOG)
-#else
-# define machine_is_elog() (0)
-#endif
-
-#ifdef CONFIG_MACH_INCOME
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_INCOME
-# endif
-# define machine_is_income() (machine_arch_type == MACH_TYPE_INCOME)
-#else
-# define machine_is_income() (0)
-#endif
-
-#ifdef CONFIG_MACH_BCM589X
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BCM589X
-# endif
-# define machine_is_bcm589x() (machine_arch_type == MACH_TYPE_BCM589X)
-#else
-# define machine_is_bcm589x() (0)
-#endif
-
-#ifdef CONFIG_MACH_ETNA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ETNA
-# endif
-# define machine_is_etna() (machine_arch_type == MACH_TYPE_ETNA)
-#else
-# define machine_is_etna() (0)
-#endif
-
-#ifdef CONFIG_MACH_HAWKS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HAWKS
-# endif
-# define machine_is_hawks() (machine_arch_type == MACH_TYPE_HAWKS)
-#else
-# define machine_is_hawks() (0)
-#endif
-
-#ifdef CONFIG_MACH_MESON
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MESON
-# endif
-# define machine_is_meson() (machine_arch_type == MACH_TYPE_MESON)
-#else
-# define machine_is_meson() (0)
-#endif
-
-#ifdef CONFIG_MACH_XSBASE255
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_XSBASE255
-# endif
-# define machine_is_xsbase255() (machine_arch_type == MACH_TYPE_XSBASE255)
-#else
-# define machine_is_xsbase255() (0)
-#endif
-
-#ifdef CONFIG_MACH_PVM2030
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PVM2030
-# endif
-# define machine_is_pvm2030() (machine_arch_type == MACH_TYPE_PVM2030)
-#else
-# define machine_is_pvm2030() (0)
-#endif
-
-#ifdef CONFIG_MACH_MIOA502
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MIOA502
-# endif
-# define machine_is_mioa502() (machine_arch_type == MACH_TYPE_MIOA502)
-#else
-# define machine_is_mioa502() (0)
-#endif
-
-#ifdef CONFIG_MACH_VVBOX_SDORIG2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VVBOX_SDORIG2
-# endif
-# define machine_is_vvbox_sdorig2() (machine_arch_type == MACH_TYPE_VVBOX_SDORIG2)
-#else
-# define machine_is_vvbox_sdorig2() (0)
-#endif
-
-#ifdef CONFIG_MACH_VVBOX_SDLITE2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VVBOX_SDLITE2
-# endif
-# define machine_is_vvbox_sdlite2() (machine_arch_type == MACH_TYPE_VVBOX_SDLITE2)
-#else
-# define machine_is_vvbox_sdlite2() (0)
-#endif
-
-#ifdef CONFIG_MACH_VVBOX_SDPRO4
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VVBOX_SDPRO4
-# endif
-# define machine_is_vvbox_sdpro4() (machine_arch_type == MACH_TYPE_VVBOX_SDPRO4)
-#else
-# define machine_is_vvbox_sdpro4() (0)
-#endif
-
-#ifdef CONFIG_MACH_HTC_SPV_M700
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HTC_SPV_M700
-# endif
-# define machine_is_htc_spv_m700() (machine_arch_type == MACH_TYPE_HTC_SPV_M700)
-#else
-# define machine_is_htc_spv_m700() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX257SX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX257SX
-# endif
-# define machine_is_mx257sx() (machine_arch_type == MACH_TYPE_MX257SX)
-#else
-# define machine_is_mx257sx() (0)
-#endif
-
-#ifdef CONFIG_MACH_GONI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GONI
-# endif
-# define machine_is_goni() (machine_arch_type == MACH_TYPE_GONI)
-#else
-# define machine_is_goni() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X55_SVLTE_FFA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8X55_SVLTE_FFA
-# endif
-# define machine_is_msm8x55_svlte_ffa() (machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_FFA)
-#else
-# define machine_is_msm8x55_svlte_ffa() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X55_SVLTE_SURF
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8X55_SVLTE_SURF
-# endif
-# define machine_is_msm8x55_svlte_surf() (machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_SURF)
-#else
-# define machine_is_msm8x55_svlte_surf() (0)
-#endif
-
-#ifdef CONFIG_MACH_QUICKSTEP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_QUICKSTEP
-# endif
-# define machine_is_quickstep() (machine_arch_type == MACH_TYPE_QUICKSTEP)
-#else
-# define machine_is_quickstep() (0)
-#endif
-
-#ifdef CONFIG_MACH_DMW96
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DMW96
-# endif
-# define machine_is_dmw96() (machine_arch_type == MACH_TYPE_DMW96)
-#else
-# define machine_is_dmw96() (0)
-#endif
-
-#ifdef CONFIG_MACH_HAMMERHEAD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HAMMERHEAD
-# endif
-# define machine_is_hammerhead() (machine_arch_type == MACH_TYPE_HAMMERHEAD)
-#else
-# define machine_is_hammerhead() (0)
-#endif
-
-#ifdef CONFIG_MACH_TRIDENT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TRIDENT
-# endif
-# define machine_is_trident() (machine_arch_type == MACH_TYPE_TRIDENT)
-#else
-# define machine_is_trident() (0)
-#endif
-
-#ifdef CONFIG_MACH_LIGHTNING
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LIGHTNING
-# endif
-# define machine_is_lightning() (machine_arch_type == MACH_TYPE_LIGHTNING)
-#else
-# define machine_is_lightning() (0)
-#endif
-
-#ifdef CONFIG_MACH_ICONNECT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ICONNECT
-# endif
-# define machine_is_iconnect() (machine_arch_type == MACH_TYPE_ICONNECT)
-#else
-# define machine_is_iconnect() (0)
-#endif
-
-#ifdef CONFIG_MACH_AUTOBOT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AUTOBOT
-# endif
-# define machine_is_autobot() (machine_arch_type == MACH_TYPE_AUTOBOT)
-#else
-# define machine_is_autobot() (0)
-#endif
-
-#ifdef CONFIG_MACH_COCONUT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_COCONUT
-# endif
-# define machine_is_coconut() (machine_arch_type == MACH_TYPE_COCONUT)
-#else
-# define machine_is_coconut() (0)
-#endif
-
-#ifdef CONFIG_MACH_DURIAN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DURIAN
-# endif
-# define machine_is_durian() (machine_arch_type == MACH_TYPE_DURIAN)
-#else
-# define machine_is_durian() (0)
-#endif
-
-#ifdef CONFIG_MACH_CAYENNE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CAYENNE
-# endif
-# define machine_is_cayenne() (machine_arch_type == MACH_TYPE_CAYENNE)
-#else
-# define machine_is_cayenne() (0)
-#endif
-
-#ifdef CONFIG_MACH_FUJI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FUJI
-# endif
-# define machine_is_fuji() (machine_arch_type == MACH_TYPE_FUJI)
-#else
-# define machine_is_fuji() (0)
-#endif
-
-#ifdef CONFIG_MACH_SYNOLOGY_6282
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SYNOLOGY_6282
-# endif
-# define machine_is_synology_6282() (machine_arch_type == MACH_TYPE_SYNOLOGY_6282)
-#else
-# define machine_is_synology_6282() (0)
-#endif
-
-#ifdef CONFIG_MACH_EM1SY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EM1SY
-# endif
-# define machine_is_em1sy() (machine_arch_type == MACH_TYPE_EM1SY)
-#else
-# define machine_is_em1sy() (0)
-#endif
-
-#ifdef CONFIG_MACH_M502
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_M502
-# endif
-# define machine_is_m502() (machine_arch_type == MACH_TYPE_M502)
-#else
-# define machine_is_m502() (0)
-#endif
-
-#ifdef CONFIG_MACH_MATRIX518
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MATRIX518
-# endif
-# define machine_is_matrix518() (machine_arch_type == MACH_TYPE_MATRIX518)
-#else
-# define machine_is_matrix518() (0)
-#endif
-
-#ifdef CONFIG_MACH_TINY_GURNARD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TINY_GURNARD
-# endif
-# define machine_is_tiny_gurnard() (machine_arch_type == MACH_TYPE_TINY_GURNARD)
-#else
-# define machine_is_tiny_gurnard() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPEAR1310
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPEAR1310
-# endif
-# define machine_is_spear1310() (machine_arch_type == MACH_TYPE_SPEAR1310)
-#else
-# define machine_is_spear1310() (0)
-#endif
-
-#ifdef CONFIG_MACH_BV07
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BV07
-# endif
-# define machine_is_bv07() (machine_arch_type == MACH_TYPE_BV07)
-#else
-# define machine_is_bv07() (0)
-#endif
-
-#ifdef CONFIG_MACH_MXT_TD61
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MXT_TD61
-# endif
-# define machine_is_mxt_td61() (machine_arch_type == MACH_TYPE_MXT_TD61)
-#else
-# define machine_is_mxt_td61() (0)
-#endif
-
-#ifdef CONFIG_MACH_OPENRD_ULTIMATE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OPENRD_ULTIMATE
-# endif
-# define machine_is_openrd_ultimate() (machine_arch_type == MACH_TYPE_OPENRD_ULTIMATE)
-#else
-# define machine_is_openrd_ultimate() (0)
-#endif
-
-#ifdef CONFIG_MACH_DEVIXP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DEVIXP
-# endif
-# define machine_is_devixp() (machine_arch_type == MACH_TYPE_DEVIXP)
-#else
-# define machine_is_devixp() (0)
-#endif
-
-#ifdef CONFIG_MACH_MICCPT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MICCPT
-# endif
-# define machine_is_miccpt() (machine_arch_type == MACH_TYPE_MICCPT)
-#else
-# define machine_is_miccpt() (0)
-#endif
-
-#ifdef CONFIG_MACH_MIC256
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MIC256
-# endif
-# define machine_is_mic256() (machine_arch_type == MACH_TYPE_MIC256)
-#else
-# define machine_is_mic256() (0)
-#endif
-
-#ifdef CONFIG_MACH_AS1167
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AS1167
-# endif
-# define machine_is_as1167() (machine_arch_type == MACH_TYPE_AS1167)
-#else
-# define machine_is_as1167() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_IBIZA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3_IBIZA
-# endif
-# define machine_is_omap3_ibiza() (machine_arch_type == MACH_TYPE_OMAP3_IBIZA)
-#else
-# define machine_is_omap3_ibiza() (0)
-#endif
-
-#ifdef CONFIG_MACH_U5500
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_U5500
-# endif
-# define machine_is_u5500() (machine_arch_type == MACH_TYPE_U5500)
-#else
-# define machine_is_u5500() (0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_PICTO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DAVINCI_PICTO
-# endif
-# define machine_is_davinci_picto() (machine_arch_type == MACH_TYPE_DAVINCI_PICTO)
-#else
-# define machine_is_davinci_picto() (0)
-#endif
-
-#ifdef CONFIG_MACH_MECHA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MECHA
-# endif
-# define machine_is_mecha() (machine_arch_type == MACH_TYPE_MECHA)
-#else
-# define machine_is_mecha() (0)
-#endif
-
-#ifdef CONFIG_MACH_BUBBA3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BUBBA3
-# endif
-# define machine_is_bubba3() (machine_arch_type == MACH_TYPE_BUBBA3)
-#else
-# define machine_is_bubba3() (0)
-#endif
-
-#ifdef CONFIG_MACH_PUPITRE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PUPITRE
-# endif
-# define machine_is_pupitre() (machine_arch_type == MACH_TYPE_PUPITRE)
-#else
-# define machine_is_pupitre() (0)
-#endif
-
-#ifdef CONFIG_MACH_TEGRA_VOGUE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TEGRA_VOGUE
-# endif
-# define machine_is_tegra_vogue() (machine_arch_type == MACH_TYPE_TEGRA_VOGUE)
-#else
-# define machine_is_tegra_vogue() (0)
-#endif
-
-#ifdef CONFIG_MACH_TEGRA_E1165
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TEGRA_E1165
-# endif
-# define machine_is_tegra_e1165() (machine_arch_type == MACH_TYPE_TEGRA_E1165)
-#else
-# define machine_is_tegra_e1165() (0)
-#endif
-
-#ifdef CONFIG_MACH_SIMPLENET
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SIMPLENET
-# endif
-# define machine_is_simplenet() (machine_arch_type == MACH_TYPE_SIMPLENET)
-#else
-# define machine_is_simplenet() (0)
-#endif
-
-#ifdef CONFIG_MACH_EC4350TBM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EC4350TBM
-# endif
-# define machine_is_ec4350tbm() (machine_arch_type == MACH_TYPE_EC4350TBM)
-#else
-# define machine_is_ec4350tbm() (0)
-#endif
-
-#ifdef CONFIG_MACH_PEC_TC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PEC_TC
-# endif
-# define machine_is_pec_tc() (machine_arch_type == MACH_TYPE_PEC_TC)
-#else
-# define machine_is_pec_tc() (0)
-#endif
-
-#ifdef CONFIG_MACH_PEC_HC2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PEC_HC2
-# endif
-# define machine_is_pec_hc2() (machine_arch_type == MACH_TYPE_PEC_HC2)
-#else
-# define machine_is_pec_hc2() (0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_MOBILIS_A
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ESL_MOBILIS_A
-# endif
-# define machine_is_esl_mobilis_a() (machine_arch_type == MACH_TYPE_ESL_MOBILIS_A)
-#else
-# define machine_is_esl_mobilis_a() (0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_MOBILIS_B
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ESL_MOBILIS_B
-# endif
-# define machine_is_esl_mobilis_b() (machine_arch_type == MACH_TYPE_ESL_MOBILIS_B)
-#else
-# define machine_is_esl_mobilis_b() (0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_WAVE_A
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ESL_WAVE_A
-# endif
-# define machine_is_esl_wave_a() (machine_arch_type == MACH_TYPE_ESL_WAVE_A)
-#else
-# define machine_is_esl_wave_a() (0)
-#endif
-
-#ifdef CONFIG_MACH_ESL_WAVE_B
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ESL_WAVE_B
-# endif
-# define machine_is_esl_wave_b() (machine_arch_type == MACH_TYPE_ESL_WAVE_B)
-#else
-# define machine_is_esl_wave_b() (0)
-#endif
-
-#ifdef CONFIG_MACH_UNISENSE_MMM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_UNISENSE_MMM
-# endif
-# define machine_is_unisense_mmm() (machine_arch_type == MACH_TYPE_UNISENSE_MMM)
-#else
-# define machine_is_unisense_mmm() (0)
-#endif
-
-#ifdef CONFIG_MACH_BLUESHARK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BLUESHARK
-# endif
-# define machine_is_blueshark() (machine_arch_type == MACH_TYPE_BLUESHARK)
-#else
-# define machine_is_blueshark() (0)
-#endif
-
-#ifdef CONFIG_MACH_E10
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_E10
-# endif
-# define machine_is_e10() (machine_arch_type == MACH_TYPE_E10)
-#else
-# define machine_is_e10() (0)
-#endif
-
-#ifdef CONFIG_MACH_APP3K_ROBIN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_APP3K_ROBIN
-# endif
-# define machine_is_app3k_robin() (machine_arch_type == MACH_TYPE_APP3K_ROBIN)
-#else
-# define machine_is_app3k_robin() (0)
-#endif
-
-#ifdef CONFIG_MACH_POV15HD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_POV15HD
-# endif
-# define machine_is_pov15hd() (machine_arch_type == MACH_TYPE_POV15HD)
-#else
-# define machine_is_pov15hd() (0)
-#endif
-
-#ifdef CONFIG_MACH_STELLA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_STELLA
-# endif
-# define machine_is_stella() (machine_arch_type == MACH_TYPE_STELLA)
-#else
-# define machine_is_stella() (0)
-#endif
-
-#ifdef CONFIG_MACH_LINKSTATION_LSCHL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LINKSTATION_LSCHL
-# endif
-# define machine_is_linkstation_lschl() (machine_arch_type == MACH_TYPE_LINKSTATION_LSCHL)
-#else
-# define machine_is_linkstation_lschl() (0)
-#endif
-
-#ifdef CONFIG_MACH_NETWALKER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NETWALKER
-# endif
-# define machine_is_netwalker() (machine_arch_type == MACH_TYPE_NETWALKER)
-#else
-# define machine_is_netwalker() (0)
-#endif
-
-#ifdef CONFIG_MACH_ACSX106
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ACSX106
-# endif
-# define machine_is_acsx106() (machine_arch_type == MACH_TYPE_ACSX106)
-#else
-# define machine_is_acsx106() (0)
-#endif
-
-#ifdef CONFIG_MACH_ATLAS5_C1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ATLAS5_C1
-# endif
-# define machine_is_atlas5_c1() (machine_arch_type == MACH_TYPE_ATLAS5_C1)
-#else
-# define machine_is_atlas5_c1() (0)
-#endif
-
-#ifdef CONFIG_MACH_NSB3AST
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NSB3AST
-# endif
-# define machine_is_nsb3ast() (machine_arch_type == MACH_TYPE_NSB3AST)
-#else
-# define machine_is_nsb3ast() (0)
-#endif
-
-#ifdef CONFIG_MACH_GNET_SLC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GNET_SLC
-# endif
-# define machine_is_gnet_slc() (machine_arch_type == MACH_TYPE_GNET_SLC)
-#else
-# define machine_is_gnet_slc() (0)
-#endif
-
-#ifdef CONFIG_MACH_AF4000
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AF4000
-# endif
-# define machine_is_af4000() (machine_arch_type == MACH_TYPE_AF4000)
-#else
-# define machine_is_af4000() (0)
-#endif
-
-#ifdef CONFIG_MACH_ARK9431
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ARK9431
-# endif
-# define machine_is_ark9431() (machine_arch_type == MACH_TYPE_ARK9431)
-#else
-# define machine_is_ark9431() (0)
-#endif
-
-#ifdef CONFIG_MACH_FS_S5PC100
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FS_S5PC100
-# endif
-# define machine_is_fs_s5pc100() (machine_arch_type == MACH_TYPE_FS_S5PC100)
-#else
-# define machine_is_fs_s5pc100() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3505NOVA8
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3505NOVA8
-# endif
-# define machine_is_omap3505nova8() (machine_arch_type == MACH_TYPE_OMAP3505NOVA8)
-#else
-# define machine_is_omap3505nova8() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3621_EDP1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3621_EDP1
-# endif
-# define machine_is_omap3621_edp1() (machine_arch_type == MACH_TYPE_OMAP3621_EDP1)
-#else
-# define machine_is_omap3621_edp1() (0)
-#endif
-
-#ifdef CONFIG_MACH_ORATISAES
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ORATISAES
-# endif
-# define machine_is_oratisaes() (machine_arch_type == MACH_TYPE_ORATISAES)
-#else
-# define machine_is_oratisaes() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMDKV310
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDKV310
-# endif
-# define machine_is_smdkv310() (machine_arch_type == MACH_TYPE_SMDKV310)
-#else
-# define machine_is_smdkv310() (0)
-#endif
-
-#ifdef CONFIG_MACH_SIEMENS_L0
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SIEMENS_L0
-# endif
-# define machine_is_siemens_l0() (machine_arch_type == MACH_TYPE_SIEMENS_L0)
-#else
-# define machine_is_siemens_l0() (0)
-#endif
-
-#ifdef CONFIG_MACH_VENTANA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VENTANA
-# endif
-# define machine_is_ventana() (machine_arch_type == MACH_TYPE_VENTANA)
-#else
-# define machine_is_ventana() (0)
-#endif
-
-#ifdef CONFIG_MACH_WM8505_7IN_NETBOOK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WM8505_7IN_NETBOOK
-# endif
-# define machine_is_wm8505_7in_netbook() (machine_arch_type == MACH_TYPE_WM8505_7IN_NETBOOK)
-#else
-# define machine_is_wm8505_7in_netbook() (0)
-#endif
-
-#ifdef CONFIG_MACH_EC4350SDB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EC4350SDB
-# endif
-# define machine_is_ec4350sdb() (machine_arch_type == MACH_TYPE_EC4350SDB)
-#else
-# define machine_is_ec4350sdb() (0)
-#endif
-
-#ifdef CONFIG_MACH_MIMAS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MIMAS
-# endif
-# define machine_is_mimas() (machine_arch_type == MACH_TYPE_MIMAS)
-#else
-# define machine_is_mimas() (0)
-#endif
-
-#ifdef CONFIG_MACH_TITAN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TITAN
-# endif
-# define machine_is_titan() (machine_arch_type == MACH_TYPE_TITAN)
-#else
-# define machine_is_titan() (0)
-#endif
-
-#ifdef CONFIG_MACH_CRANEBOARD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CRANEBOARD
-# endif
-# define machine_is_craneboard() (machine_arch_type == MACH_TYPE_CRANEBOARD)
-#else
-# define machine_is_craneboard() (0)
-#endif
-
-#ifdef CONFIG_MACH_ES2440
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ES2440
-# endif
-# define machine_is_es2440() (machine_arch_type == MACH_TYPE_ES2440)
-#else
-# define machine_is_es2440() (0)
-#endif
-
-#ifdef CONFIG_MACH_NAJAY_A9263
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NAJAY_A9263
-# endif
-# define machine_is_najay_a9263() (machine_arch_type == MACH_TYPE_NAJAY_A9263)
-#else
-# define machine_is_najay_a9263() (0)
-#endif
-
-#ifdef CONFIG_MACH_HTCTORNADO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HTCTORNADO
-# endif
-# define machine_is_htctornado() (machine_arch_type == MACH_TYPE_HTCTORNADO)
-#else
-# define machine_is_htctornado() (0)
-#endif
-
-#ifdef CONFIG_MACH_DIMM_MX257
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DIMM_MX257
-# endif
-# define machine_is_dimm_mx257() (machine_arch_type == MACH_TYPE_DIMM_MX257)
-#else
-# define machine_is_dimm_mx257() (0)
-#endif
-
-#ifdef CONFIG_MACH_JIGEN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_JIGEN
-# endif
-# define machine_is_jigen301() (machine_arch_type == MACH_TYPE_JIGEN)
-#else
-# define machine_is_jigen301() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMDK6450
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDK6450
-# endif
-# define machine_is_smdk6450() (machine_arch_type == MACH_TYPE_SMDK6450)
-#else
-# define machine_is_smdk6450() (0)
-#endif
-
-#ifdef CONFIG_MACH_MENO_QNG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MENO_QNG
-# endif
-# define machine_is_meno_qng() (machine_arch_type == MACH_TYPE_MENO_QNG)
-#else
-# define machine_is_meno_qng() (0)
-#endif
-
-#ifdef CONFIG_MACH_NS2416
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NS2416
-# endif
-# define machine_is_ns2416() (machine_arch_type == MACH_TYPE_NS2416)
-#else
-# define machine_is_ns2416() (0)
-#endif
-
-#ifdef CONFIG_MACH_RPC353
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RPC353
-# endif
-# define machine_is_rpc353() (machine_arch_type == MACH_TYPE_RPC353)
-#else
-# define machine_is_rpc353() (0)
-#endif
-
-#ifdef CONFIG_MACH_TQ6410
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TQ6410
-# endif
-# define machine_is_tq6410() (machine_arch_type == MACH_TYPE_TQ6410)
-#else
-# define machine_is_tq6410() (0)
-#endif
-
-#ifdef CONFIG_MACH_SKY6410
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SKY6410
-# endif
-# define machine_is_sky6410() (machine_arch_type == MACH_TYPE_SKY6410)
-#else
-# define machine_is_sky6410() (0)
-#endif
-
-#ifdef CONFIG_MACH_DYNASTY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DYNASTY
-# endif
-# define machine_is_dynasty() (machine_arch_type == MACH_TYPE_DYNASTY)
-#else
-# define machine_is_dynasty() (0)
-#endif
-
-#ifdef CONFIG_MACH_VIVO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VIVO
-# endif
-# define machine_is_vivo() (machine_arch_type == MACH_TYPE_VIVO)
-#else
-# define machine_is_vivo() (0)
-#endif
-
-#ifdef CONFIG_MACH_BURY_BL7582
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BURY_BL7582
-# endif
-# define machine_is_bury_bl7582() (machine_arch_type == MACH_TYPE_BURY_BL7582)
-#else
-# define machine_is_bury_bl7582() (0)
-#endif
-
-#ifdef CONFIG_MACH_BURY_BPS5270
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BURY_BPS5270
-# endif
-# define machine_is_bury_bps5270() (machine_arch_type == MACH_TYPE_BURY_BPS5270)
-#else
-# define machine_is_bury_bps5270() (0)
-#endif
-
-#ifdef CONFIG_MACH_BASI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BASI
-# endif
-# define machine_is_basi() (machine_arch_type == MACH_TYPE_BASI)
-#else
-# define machine_is_basi() (0)
-#endif
-
-#ifdef CONFIG_MACH_TN200
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TN200
-# endif
-# define machine_is_tn200() (machine_arch_type == MACH_TYPE_TN200)
-#else
-# define machine_is_tn200() (0)
-#endif
-
-#ifdef CONFIG_MACH_C2MMI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_C2MMI
-# endif
-# define machine_is_c2mmi() (machine_arch_type == MACH_TYPE_C2MMI)
-#else
-# define machine_is_c2mmi() (0)
-#endif
-
-#ifdef CONFIG_MACH_MESON_6236M
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MESON_6236M
-# endif
-# define machine_is_meson_6236m() (machine_arch_type == MACH_TYPE_MESON_6236M)
-#else
-# define machine_is_meson_6236m() (0)
-#endif
-
-#ifdef CONFIG_MACH_MESON_8626M
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MESON_8626M
-# endif
-# define machine_is_meson_8626m() (machine_arch_type == MACH_TYPE_MESON_8626M)
-#else
-# define machine_is_meson_8626m() (0)
-#endif
-
-#ifdef CONFIG_MACH_TUBE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TUBE
-# endif
-# define machine_is_tube() (machine_arch_type == MACH_TYPE_TUBE)
-#else
-# define machine_is_tube() (0)
-#endif
-
-#ifdef CONFIG_MACH_MESSINA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MESSINA
-# endif
-# define machine_is_messina() (machine_arch_type == MACH_TYPE_MESSINA)
-#else
-# define machine_is_messina() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX50_ARM2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX50_ARM2
-# endif
-# define machine_is_mx50_arm2() (machine_arch_type == MACH_TYPE_MX50_ARM2)
-#else
-# define machine_is_mx50_arm2() (0)
-#endif
-
-#ifdef CONFIG_MACH_CETUS9263
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CETUS9263
-# endif
-# define machine_is_cetus9263() (machine_arch_type == MACH_TYPE_CETUS9263)
-#else
-# define machine_is_cetus9263() (0)
-#endif
-
-#ifdef CONFIG_MACH_BROWNSTONE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BROWNSTONE
-# endif
-# define machine_is_brownstone() (machine_arch_type == MACH_TYPE_BROWNSTONE)
-#else
-# define machine_is_brownstone() (0)
-#endif
-
-#ifdef CONFIG_MACH_VMX25
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VMX25
-# endif
-# define machine_is_vmx25() (machine_arch_type == MACH_TYPE_VMX25)
-#else
-# define machine_is_vmx25() (0)
-#endif
-
-#ifdef CONFIG_MACH_VMX51
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VMX51
-# endif
-# define machine_is_vmx51() (machine_arch_type == MACH_TYPE_VMX51)
-#else
-# define machine_is_vmx51() (0)
-#endif
-
-#ifdef CONFIG_MACH_ABACUS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ABACUS
-# endif
-# define machine_is_abacus() (machine_arch_type == MACH_TYPE_ABACUS)
-#else
-# define machine_is_abacus() (0)
-#endif
-
-#ifdef CONFIG_MACH_CM4745
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CM4745
-# endif
-# define machine_is_cm4745() (machine_arch_type == MACH_TYPE_CM4745)
-#else
-# define machine_is_cm4745() (0)
-#endif
-
-#ifdef CONFIG_MACH_ORATISLINK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ORATISLINK
-# endif
-# define machine_is_oratislink() (machine_arch_type == MACH_TYPE_ORATISLINK)
-#else
-# define machine_is_oratislink() (0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM365_DVR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DAVINCI_DM365_DVR
-# endif
-# define machine_is_davinci_dm365_dvr() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_DVR)
-#else
-# define machine_is_davinci_dm365_dvr() (0)
-#endif
-
-#ifdef CONFIG_MACH_NETVIZ
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NETVIZ
-# endif
-# define machine_is_netviz() (machine_arch_type == MACH_TYPE_NETVIZ)
-#else
-# define machine_is_netviz() (0)
-#endif
-
-#ifdef CONFIG_MACH_FLEXIBITY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FLEXIBITY
-# endif
-# define machine_is_flexibity() (machine_arch_type == MACH_TYPE_FLEXIBITY)
-#else
-# define machine_is_flexibity() (0)
-#endif
-
-#ifdef CONFIG_MACH_WLAN_COMPUTER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WLAN_COMPUTER
-# endif
-# define machine_is_wlan_computer() (machine_arch_type == MACH_TYPE_WLAN_COMPUTER)
-#else
-# define machine_is_wlan_computer() (0)
-#endif
-
-#ifdef CONFIG_MACH_LPC24XX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LPC24XX
-# endif
-# define machine_is_lpc24xx() (machine_arch_type == MACH_TYPE_LPC24XX)
-#else
-# define machine_is_lpc24xx() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPICA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPICA
-# endif
-# define machine_is_spica() (machine_arch_type == MACH_TYPE_SPICA)
-#else
-# define machine_is_spica() (0)
-#endif
-
-#ifdef CONFIG_MACH_GPSDISPLAY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GPSDISPLAY
-# endif
-# define machine_is_gpsdisplay() (machine_arch_type == MACH_TYPE_GPSDISPLAY)
-#else
-# define machine_is_gpsdisplay() (0)
-#endif
-
-#ifdef CONFIG_MACH_BIPNET
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BIPNET
-# endif
-# define machine_is_bipnet() (machine_arch_type == MACH_TYPE_BIPNET)
-#else
-# define machine_is_bipnet() (0)
-#endif
-
-#ifdef CONFIG_MACH_OVERO_CTU_INERTIAL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OVERO_CTU_INERTIAL
-# endif
-# define machine_is_overo_ctu_inertial() (machine_arch_type == MACH_TYPE_OVERO_CTU_INERTIAL)
-#else
-# define machine_is_overo_ctu_inertial() (0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM355_MMM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DAVINCI_DM355_MMM
-# endif
-# define machine_is_davinci_dm355_mmm() (machine_arch_type == MACH_TYPE_DAVINCI_DM355_MMM)
-#else
-# define machine_is_davinci_dm355_mmm() (0)
-#endif
-
-#ifdef CONFIG_MACH_PC9260_V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PC9260_V2
-# endif
-# define machine_is_pc9260_v2() (machine_arch_type == MACH_TYPE_PC9260_V2)
-#else
-# define machine_is_pc9260_v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_PTX7545
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PTX7545
-# endif
-# define machine_is_ptx7545() (machine_arch_type == MACH_TYPE_PTX7545)
-#else
-# define machine_is_ptx7545() (0)
-#endif
-
-#ifdef CONFIG_MACH_TM_EFDC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TM_EFDC
-# endif
-# define machine_is_tm_efdc() (machine_arch_type == MACH_TYPE_TM_EFDC)
-#else
-# define machine_is_tm_efdc() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_WALDO1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3_WALDO1
-# endif
-# define machine_is_omap3_waldo1() (machine_arch_type == MACH_TYPE_OMAP3_WALDO1)
-#else
-# define machine_is_omap3_waldo1() (0)
-#endif
-
-#ifdef CONFIG_MACH_FLYER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FLYER
-# endif
-# define machine_is_flyer() (machine_arch_type == MACH_TYPE_FLYER)
-#else
-# define machine_is_flyer() (0)
-#endif
-
-#ifdef CONFIG_MACH_TORNADO3240
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TORNADO3240
-# endif
-# define machine_is_tornado3240() (machine_arch_type == MACH_TYPE_TORNADO3240)
-#else
-# define machine_is_tornado3240() (0)
-#endif
-
-#ifdef CONFIG_MACH_SOLI_01
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SOLI_01
-# endif
-# define machine_is_soli_01() (machine_arch_type == MACH_TYPE_SOLI_01)
-#else
-# define machine_is_soli_01() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAPL138_EUROPALC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAPL138_EUROPALC
-# endif
-# define machine_is_omapl138_europalc() (machine_arch_type == MACH_TYPE_OMAPL138_EUROPALC)
-#else
-# define machine_is_omapl138_europalc() (0)
-#endif
-
-#ifdef CONFIG_MACH_HELIOS_V1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HELIOS_V1
-# endif
-# define machine_is_helios_v1() (machine_arch_type == MACH_TYPE_HELIOS_V1)
-#else
-# define machine_is_helios_v1() (0)
-#endif
-
-#ifdef CONFIG_MACH_NETSPACE_LITE_V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NETSPACE_LITE_V2
-# endif
-# define machine_is_netspace_lite_v2() (machine_arch_type == MACH_TYPE_NETSPACE_LITE_V2)
-#else
-# define machine_is_netspace_lite_v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_SSC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SSC
-# endif
-# define machine_is_ssc() (machine_arch_type == MACH_TYPE_SSC)
-#else
-# define machine_is_ssc() (0)
-#endif
-
-#ifdef CONFIG_MACH_PREMIERWAVE_EN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PREMIERWAVE_EN
-# endif
-# define machine_is_premierwave_en() (machine_arch_type == MACH_TYPE_PREMIERWAVE_EN)
-#else
-# define machine_is_premierwave_en() (0)
-#endif
-
-#ifdef CONFIG_MACH_WASABI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WASABI
-# endif
-# define machine_is_wasabi() (machine_arch_type == MACH_TYPE_WASABI)
-#else
-# define machine_is_wasabi() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX50_RDP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX50_RDP
-# endif
-# define machine_is_mx50_rdp() (machine_arch_type == MACH_TYPE_MX50_RDP)
-#else
-# define machine_is_mx50_rdp() (0)
-#endif
-
-#ifdef CONFIG_MACH_UNIVERSAL_C210
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_UNIVERSAL_C210
-# endif
-# define machine_is_universal_c210() (machine_arch_type == MACH_TYPE_UNIVERSAL_C210)
-#else
-# define machine_is_universal_c210() (0)
-#endif
-
-#ifdef CONFIG_MACH_REAL6410
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_REAL6410
-# endif
-# define machine_is_real6410() (machine_arch_type == MACH_TYPE_REAL6410)
-#else
-# define machine_is_real6410() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPX_SAKURA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPX_SAKURA
-# endif
-# define machine_is_spx_sakura() (machine_arch_type == MACH_TYPE_SPX_SAKURA)
-#else
-# define machine_is_spx_sakura() (0)
-#endif
-
-#ifdef CONFIG_MACH_IJ3K_2440
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IJ3K_2440
-# endif
-# define machine_is_ij3k_2440() (machine_arch_type == MACH_TYPE_IJ3K_2440)
-#else
-# define machine_is_ij3k_2440() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_BC10
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3_BC10
-# endif
-# define machine_is_omap3_bc10() (machine_arch_type == MACH_TYPE_OMAP3_BC10)
-#else
-# define machine_is_omap3_bc10() (0)
-#endif
-
-#ifdef CONFIG_MACH_THEBE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_THEBE
-# endif
-# define machine_is_thebe() (machine_arch_type == MACH_TYPE_THEBE)
-#else
-# define machine_is_thebe() (0)
-#endif
-
-#ifdef CONFIG_MACH_RV082
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RV082
-# endif
-# define machine_is_rv082() (machine_arch_type == MACH_TYPE_RV082)
-#else
-# define machine_is_rv082() (0)
-#endif
-
-#ifdef CONFIG_MACH_ARMLGUEST
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ARMLGUEST
-# endif
-# define machine_is_armlguest() (machine_arch_type == MACH_TYPE_ARMLGUEST)
-#else
-# define machine_is_armlguest() (0)
-#endif
-
-#ifdef CONFIG_MACH_TJINC1000
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TJINC1000
-# endif
-# define machine_is_tjinc1000() (machine_arch_type == MACH_TYPE_TJINC1000)
-#else
-# define machine_is_tjinc1000() (0)
-#endif
-
-#ifdef CONFIG_MACH_DOCKSTAR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DOCKSTAR
-# endif
-# define machine_is_dockstar() (machine_arch_type == MACH_TYPE_DOCKSTAR)
-#else
-# define machine_is_dockstar() (0)
-#endif
-
-#ifdef CONFIG_MACH_AX8008
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AX8008
-# endif
-# define machine_is_ax8008() (machine_arch_type == MACH_TYPE_AX8008)
-#else
-# define machine_is_ax8008() (0)
-#endif
-
-#ifdef CONFIG_MACH_GNET_SGCE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GNET_SGCE
-# endif
-# define machine_is_gnet_sgce() (machine_arch_type == MACH_TYPE_GNET_SGCE)
-#else
-# define machine_is_gnet_sgce() (0)
-#endif
-
-#ifdef CONFIG_MACH_PXWNAS_500_1000
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PXWNAS_500_1000
-# endif
-# define machine_is_pxwnas_500_1000() (machine_arch_type == MACH_TYPE_PXWNAS_500_1000)
-#else
-# define machine_is_pxwnas_500_1000() (0)
-#endif
-
-#ifdef CONFIG_MACH_EA20
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EA20
-# endif
-# define machine_is_ea20() (machine_arch_type == MACH_TYPE_EA20)
-#else
-# define machine_is_ea20() (0)
-#endif
-
-#ifdef CONFIG_MACH_AWM2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AWM2
-# endif
-# define machine_is_awm2() (machine_arch_type == MACH_TYPE_AWM2)
-#else
-# define machine_is_awm2() (0)
-#endif
-
-#ifdef CONFIG_MACH_TI8148EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TI8148EVM
-# endif
-# define machine_is_ti8148evm() (machine_arch_type == MACH_TYPE_TI8148EVM)
-#else
-# define machine_is_ti8148evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_SEABOARD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SEABOARD
-# endif
-# define machine_is_seaboard() (machine_arch_type == MACH_TYPE_SEABOARD)
-#else
-# define machine_is_seaboard() (0)
-#endif
-
-#ifdef CONFIG_MACH_LINKSTATION_CHLV2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LINKSTATION_CHLV2
-# endif
-# define machine_is_linkstation_chlv2() (machine_arch_type == MACH_TYPE_LINKSTATION_CHLV2)
-#else
-# define machine_is_linkstation_chlv2() (0)
-#endif
-
-#ifdef CONFIG_MACH_TERA_PRO2_RACK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TERA_PRO2_RACK
-# endif
-# define machine_is_tera_pro2_rack() (machine_arch_type == MACH_TYPE_TERA_PRO2_RACK)
-#else
-# define machine_is_tera_pro2_rack() (0)
-#endif
-
-#ifdef CONFIG_MACH_RUBYS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RUBYS
-# endif
-# define machine_is_rubys() (machine_arch_type == MACH_TYPE_RUBYS)
-#else
-# define machine_is_rubys() (0)
-#endif
-
-#ifdef CONFIG_MACH_AQUARIUS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AQUARIUS
-# endif
-# define machine_is_aquarius() (machine_arch_type == MACH_TYPE_AQUARIUS)
-#else
-# define machine_is_aquarius() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX53_ARD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX53_ARD
-# endif
-# define machine_is_mx53_ard() (machine_arch_type == MACH_TYPE_MX53_ARD)
-#else
-# define machine_is_mx53_ard() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX53_SMD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX53_SMD
-# endif
-# define machine_is_mx53_smd() (machine_arch_type == MACH_TYPE_MX53_SMD)
-#else
-# define machine_is_mx53_smd() (0)
-#endif
-
-#ifdef CONFIG_MACH_LSWXL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LSWXL
-# endif
-# define machine_is_lswxl() (machine_arch_type == MACH_TYPE_LSWXL)
-#else
-# define machine_is_lswxl() (0)
-#endif
-
-#ifdef CONFIG_MACH_DOVE_AVNG_V3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DOVE_AVNG_V3
-# endif
-# define machine_is_dove_avng_v3() (machine_arch_type == MACH_TYPE_DOVE_AVNG_V3)
-#else
-# define machine_is_dove_avng_v3() (0)
-#endif
-
-#ifdef CONFIG_MACH_SDI_ESS_9263
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SDI_ESS_9263
-# endif
-# define machine_is_sdi_ess_9263() (machine_arch_type == MACH_TYPE_SDI_ESS_9263)
-#else
-# define machine_is_sdi_ess_9263() (0)
-#endif
-
-#ifdef CONFIG_MACH_JOCPU550
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_JOCPU550
-# endif
-# define machine_is_jocpu550() (machine_arch_type == MACH_TYPE_JOCPU550)
-#else
-# define machine_is_jocpu550() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_RUMI3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8X60_RUMI3
-# endif
-# define machine_is_msm8x60_rumi3() (machine_arch_type == MACH_TYPE_MSM8X60_RUMI3)
-#else
-# define machine_is_msm8x60_rumi3() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_FFA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8X60_FFA
-# endif
-# define machine_is_msm8x60_ffa() (machine_arch_type == MACH_TYPE_MSM8X60_FFA)
-#else
-# define machine_is_msm8x60_ffa() (0)
-#endif
-
-#ifdef CONFIG_MACH_YANOMAMI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_YANOMAMI
-# endif
-# define machine_is_yanomami() (machine_arch_type == MACH_TYPE_YANOMAMI)
-#else
-# define machine_is_yanomami() (0)
-#endif
-
-#ifdef CONFIG_MACH_GTA04
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GTA04
-# endif
-# define machine_is_gta04() (machine_arch_type == MACH_TYPE_GTA04)
-#else
-# define machine_is_gta04() (0)
-#endif
-
-#ifdef CONFIG_MACH_CM_A510
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CM_A510
-# endif
-# define machine_is_cm_a510() (machine_arch_type == MACH_TYPE_CM_A510)
-#else
-# define machine_is_cm_a510() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_RFS200
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3_RFS200
-# endif
-# define machine_is_omap3_rfs200() (machine_arch_type == MACH_TYPE_OMAP3_RFS200)
-#else
-# define machine_is_omap3_rfs200() (0)
-#endif
-
-#ifdef CONFIG_MACH_KX33XX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KX33XX
-# endif
-# define machine_is_kx33xx() (machine_arch_type == MACH_TYPE_KX33XX)
-#else
-# define machine_is_kx33xx() (0)
-#endif
-
-#ifdef CONFIG_MACH_PTX7510
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PTX7510
-# endif
-# define machine_is_ptx7510() (machine_arch_type == MACH_TYPE_PTX7510)
-#else
-# define machine_is_ptx7510() (0)
-#endif
-
-#ifdef CONFIG_MACH_TOP9000
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TOP9000
-# endif
-# define machine_is_top9000() (machine_arch_type == MACH_TYPE_TOP9000)
-#else
-# define machine_is_top9000() (0)
-#endif
-
-#ifdef CONFIG_MACH_TEENOTE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TEENOTE
-# endif
-# define machine_is_teenote() (machine_arch_type == MACH_TYPE_TEENOTE)
-#else
-# define machine_is_teenote() (0)
-#endif
-
-#ifdef CONFIG_MACH_TS3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TS3
-# endif
-# define machine_is_ts3() (machine_arch_type == MACH_TYPE_TS3)
-#else
-# define machine_is_ts3() (0)
-#endif
-
-#ifdef CONFIG_MACH_A0
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_A0
-# endif
-# define machine_is_a0() (machine_arch_type == MACH_TYPE_A0)
-#else
-# define machine_is_a0() (0)
-#endif
-
-#ifdef CONFIG_MACH_FSM9XXX_SURF
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FSM9XXX_SURF
-# endif
-# define machine_is_fsm9xxx_surf() (machine_arch_type == MACH_TYPE_FSM9XXX_SURF)
-#else
-# define machine_is_fsm9xxx_surf() (0)
-#endif
-
-#ifdef CONFIG_MACH_FSM9XXX_FFA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FSM9XXX_FFA
-# endif
-# define machine_is_fsm9xxx_ffa() (machine_arch_type == MACH_TYPE_FSM9XXX_FFA)
-#else
-# define machine_is_fsm9xxx_ffa() (0)
-#endif
-
-#ifdef CONFIG_MACH_FRRHWCDMA60W
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FRRHWCDMA60W
-# endif
-# define machine_is_frrhwcdma60w() (machine_arch_type == MACH_TYPE_FRRHWCDMA60W)
-#else
-# define machine_is_frrhwcdma60w() (0)
-#endif
-
-#ifdef CONFIG_MACH_REMUS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_REMUS
-# endif
-# define machine_is_remus() (machine_arch_type == MACH_TYPE_REMUS)
-#else
-# define machine_is_remus() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91CAP7XDK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91CAP7XDK
-# endif
-# define machine_is_at91cap7xdk() (machine_arch_type == MACH_TYPE_AT91CAP7XDK)
-#else
-# define machine_is_at91cap7xdk() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91CAP7STK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91CAP7STK
-# endif
-# define machine_is_at91cap7stk() (machine_arch_type == MACH_TYPE_AT91CAP7STK)
-#else
-# define machine_is_at91cap7stk() (0)
-#endif
-
-#ifdef CONFIG_MACH_KT_SBC_SAM9_1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KT_SBC_SAM9_1
-# endif
-# define machine_is_kt_sbc_sam9_1() (machine_arch_type == MACH_TYPE_KT_SBC_SAM9_1)
-#else
-# define machine_is_kt_sbc_sam9_1() (0)
-#endif
-
-#ifdef CONFIG_MACH_ARMADA_XP_DB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ARMADA_XP_DB
-# endif
-# define machine_is_armada_xp_db() (machine_arch_type == MACH_TYPE_ARMADA_XP_DB)
-#else
-# define machine_is_armada_xp_db() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPDM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPDM
-# endif
-# define machine_is_spdm() (machine_arch_type == MACH_TYPE_SPDM)
-#else
-# define machine_is_spdm() (0)
-#endif
-
-#ifdef CONFIG_MACH_GTIB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GTIB
-# endif
-# define machine_is_gtib() (machine_arch_type == MACH_TYPE_GTIB)
-#else
-# define machine_is_gtib() (0)
-#endif
-
-#ifdef CONFIG_MACH_DGM3240
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DGM3240
-# endif
-# define machine_is_dgm3240() (machine_arch_type == MACH_TYPE_DGM3240)
-#else
-# define machine_is_dgm3240() (0)
-#endif
-
-#ifdef CONFIG_MACH_HTCMEGA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HTCMEGA
-# endif
-# define machine_is_htcmega() (machine_arch_type == MACH_TYPE_HTCMEGA)
-#else
-# define machine_is_htcmega() (0)
-#endif
-
-#ifdef CONFIG_MACH_TRICORDER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TRICORDER
-# endif
-# define machine_is_tricorder() (machine_arch_type == MACH_TYPE_TRICORDER)
-#else
-# define machine_is_tricorder() (0)
-#endif
-
-#ifdef CONFIG_MACH_TX28
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TX28
-# endif
-# define machine_is_tx28() (machine_arch_type == MACH_TYPE_TX28)
-#else
-# define machine_is_tx28() (0)
-#endif
-
-#ifdef CONFIG_MACH_BSTBRD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BSTBRD
-# endif
-# define machine_is_bstbrd() (machine_arch_type == MACH_TYPE_BSTBRD)
-#else
-# define machine_is_bstbrd() (0)
-#endif
-
-#ifdef CONFIG_MACH_PWB3090
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PWB3090
-# endif
-# define machine_is_pwb3090() (machine_arch_type == MACH_TYPE_PWB3090)
-#else
-# define machine_is_pwb3090() (0)
-#endif
-
-#ifdef CONFIG_MACH_IDEA6410
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IDEA6410
-# endif
-# define machine_is_idea6410() (machine_arch_type == MACH_TYPE_IDEA6410)
-#else
-# define machine_is_idea6410() (0)
-#endif
-
-#ifdef CONFIG_MACH_QBC9263
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_QBC9263
-# endif
-# define machine_is_qbc9263() (machine_arch_type == MACH_TYPE_QBC9263)
-#else
-# define machine_is_qbc9263() (0)
-#endif
-
-#ifdef CONFIG_MACH_BORABORA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BORABORA
-# endif
-# define machine_is_borabora() (machine_arch_type == MACH_TYPE_BORABORA)
-#else
-# define machine_is_borabora() (0)
-#endif
-
-#ifdef CONFIG_MACH_VALDEZ
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VALDEZ
-# endif
-# define machine_is_valdez() (machine_arch_type == MACH_TYPE_VALDEZ)
-#else
-# define machine_is_valdez() (0)
-#endif
-
-#ifdef CONFIG_MACH_LS9G20
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LS9G20
-# endif
-# define machine_is_ls9g20() (machine_arch_type == MACH_TYPE_LS9G20)
-#else
-# define machine_is_ls9g20() (0)
-#endif
-
-#ifdef CONFIG_MACH_MIOS_V1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MIOS_V1
-# endif
-# define machine_is_mios_v1() (machine_arch_type == MACH_TYPE_MIOS_V1)
-#else
-# define machine_is_mios_v1() (0)
-#endif
-
-#ifdef CONFIG_MACH_S5PC110_CRESPO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_S5PC110_CRESPO
-# endif
-# define machine_is_s5pc110_crespo() (machine_arch_type == MACH_TYPE_S5PC110_CRESPO)
-#else
-# define machine_is_s5pc110_crespo() (0)
-#endif
-
-#ifdef CONFIG_MACH_CONTROLTEK9G20
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CONTROLTEK9G20
-# endif
-# define machine_is_controltek9g20() (machine_arch_type == MACH_TYPE_CONTROLTEK9G20)
-#else
-# define machine_is_controltek9g20() (0)
-#endif
-
-#ifdef CONFIG_MACH_TIN307
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TIN307
-# endif
-# define machine_is_tin307() (machine_arch_type == MACH_TYPE_TIN307)
-#else
-# define machine_is_tin307() (0)
-#endif
-
-#ifdef CONFIG_MACH_TIN510
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TIN510
-# endif
-# define machine_is_tin510() (machine_arch_type == MACH_TYPE_TIN510)
-#else
-# define machine_is_tin510() (0)
-#endif
-
-#ifdef CONFIG_MACH_BLUECHEESE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BLUECHEESE
-# endif
-# define machine_is_bluecheese() (machine_arch_type == MACH_TYPE_BLUECHEESE)
-#else
-# define machine_is_bluecheese() (0)
-#endif
-
-#ifdef CONFIG_MACH_TEM3X30
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TEM3X30
-# endif
-# define machine_is_tem3x30() (machine_arch_type == MACH_TYPE_TEM3X30)
-#else
-# define machine_is_tem3x30() (0)
-#endif
-
-#ifdef CONFIG_MACH_HARVEST_DESOTO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HARVEST_DESOTO
-# endif
-# define machine_is_harvest_desoto() (machine_arch_type == MACH_TYPE_HARVEST_DESOTO)
-#else
-# define machine_is_harvest_desoto() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_QRDC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8X60_QRDC
-# endif
-# define machine_is_msm8x60_qrdc() (machine_arch_type == MACH_TYPE_MSM8X60_QRDC)
-#else
-# define machine_is_msm8x60_qrdc() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPEAR900
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPEAR900
-# endif
-# define machine_is_spear900() (machine_arch_type == MACH_TYPE_SPEAR900)
-#else
-# define machine_is_spear900() (0)
-#endif
-
-#ifdef CONFIG_MACH_PCONTROL_G20
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PCONTROL_G20
-# endif
-# define machine_is_pcontrol_g20() (machine_arch_type == MACH_TYPE_PCONTROL_G20)
-#else
-# define machine_is_pcontrol_g20() (0)
-#endif
-
-#ifdef CONFIG_MACH_RDSTOR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RDSTOR
-# endif
-# define machine_is_rdstor() (machine_arch_type == MACH_TYPE_RDSTOR)
-#else
-# define machine_is_rdstor() (0)
-#endif
-
-#ifdef CONFIG_MACH_USDLOADER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_USDLOADER
-# endif
-# define machine_is_usdloader() (machine_arch_type == MACH_TYPE_USDLOADER)
-#else
-# define machine_is_usdloader() (0)
-#endif
-
-#ifdef CONFIG_MACH_TSOPLOADER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TSOPLOADER
-# endif
-# define machine_is_tsoploader() (machine_arch_type == MACH_TYPE_TSOPLOADER)
-#else
-# define machine_is_tsoploader() (0)
-#endif
-
-#ifdef CONFIG_MACH_KRONOS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KRONOS
-# endif
-# define machine_is_kronos() (machine_arch_type == MACH_TYPE_KRONOS)
-#else
-# define machine_is_kronos() (0)
-#endif
-
-#ifdef CONFIG_MACH_FFCORE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FFCORE
-# endif
-# define machine_is_ffcore() (machine_arch_type == MACH_TYPE_FFCORE)
-#else
-# define machine_is_ffcore() (0)
-#endif
-
-#ifdef CONFIG_MACH_MONE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MONE
-# endif
-# define machine_is_mone() (machine_arch_type == MACH_TYPE_MONE)
-#else
-# define machine_is_mone() (0)
-#endif
-
-#ifdef CONFIG_MACH_UNIT2S
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_UNIT2S
-# endif
-# define machine_is_unit2s() (machine_arch_type == MACH_TYPE_UNIT2S)
-#else
-# define machine_is_unit2s() (0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_A5
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ACER_A5
-# endif
-# define machine_is_acer_a5() (machine_arch_type == MACH_TYPE_ACER_A5)
-#else
-# define machine_is_acer_a5() (0)
-#endif
-
-#ifdef CONFIG_MACH_ETHERPRO_ISP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ETHERPRO_ISP
-# endif
-# define machine_is_etherpro_isp() (machine_arch_type == MACH_TYPE_ETHERPRO_ISP)
-#else
-# define machine_is_etherpro_isp() (0)
-#endif
-
-#ifdef CONFIG_MACH_STRETCHS7000
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_STRETCHS7000
-# endif
-# define machine_is_stretchs7000() (machine_arch_type == MACH_TYPE_STRETCHS7000)
-#else
-# define machine_is_stretchs7000() (0)
-#endif
-
-#ifdef CONFIG_MACH_P87_SMARTSIM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_P87_SMARTSIM
-# endif
-# define machine_is_p87_smartsim() (machine_arch_type == MACH_TYPE_P87_SMARTSIM)
-#else
-# define machine_is_p87_smartsim() (0)
-#endif
-
-#ifdef CONFIG_MACH_TULIP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TULIP
-# endif
-# define machine_is_tulip() (machine_arch_type == MACH_TYPE_TULIP)
-#else
-# define machine_is_tulip() (0)
-#endif
-
-#ifdef CONFIG_MACH_SUNFLOWER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SUNFLOWER
-# endif
-# define machine_is_sunflower() (machine_arch_type == MACH_TYPE_SUNFLOWER)
-#else
-# define machine_is_sunflower() (0)
-#endif
-
-#ifdef CONFIG_MACH_RIB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RIB
-# endif
-# define machine_is_rib() (machine_arch_type == MACH_TYPE_RIB)
-#else
-# define machine_is_rib() (0)
-#endif
-
-#ifdef CONFIG_MACH_CLOD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CLOD
-# endif
-# define machine_is_clod() (machine_arch_type == MACH_TYPE_CLOD)
-#else
-# define machine_is_clod() (0)
-#endif
-
-#ifdef CONFIG_MACH_RUMP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RUMP
-# endif
-# define machine_is_rump() (machine_arch_type == MACH_TYPE_RUMP)
-#else
-# define machine_is_rump() (0)
-#endif
-
-#ifdef CONFIG_MACH_TENDERLOIN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TENDERLOIN
-# endif
-# define machine_is_tenderloin() (machine_arch_type == MACH_TYPE_TENDERLOIN)
-#else
-# define machine_is_tenderloin() (0)
-#endif
-
-#ifdef CONFIG_MACH_SHORTLOIN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SHORTLOIN
-# endif
-# define machine_is_shortloin() (machine_arch_type == MACH_TYPE_SHORTLOIN)
-#else
-# define machine_is_shortloin() (0)
-#endif
-
-#ifdef CONFIG_MACH_ANTARES
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ANTARES
-# endif
-# define machine_is_antares() (machine_arch_type == MACH_TYPE_ANTARES)
-#else
-# define machine_is_antares() (0)
-#endif
-
-#ifdef CONFIG_MACH_WB40N
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WB40N
-# endif
-# define machine_is_wb40n() (machine_arch_type == MACH_TYPE_WB40N)
-#else
-# define machine_is_wb40n() (0)
-#endif
-
-#ifdef CONFIG_MACH_HERRING
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HERRING
-# endif
-# define machine_is_herring() (machine_arch_type == MACH_TYPE_HERRING)
-#else
-# define machine_is_herring() (0)
-#endif
-
-#ifdef CONFIG_MACH_NAXY400
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NAXY400
-# endif
-# define machine_is_naxy400() (machine_arch_type == MACH_TYPE_NAXY400)
-#else
-# define machine_is_naxy400() (0)
-#endif
-
-#ifdef CONFIG_MACH_NAXY1200
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NAXY1200
-# endif
-# define machine_is_naxy1200() (machine_arch_type == MACH_TYPE_NAXY1200)
-#else
-# define machine_is_naxy1200() (0)
-#endif
-
-#ifdef CONFIG_MACH_VPR200
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VPR200
-# endif
-# define machine_is_vpr200() (machine_arch_type == MACH_TYPE_VPR200)
-#else
-# define machine_is_vpr200() (0)
-#endif
-
-#ifdef CONFIG_MACH_BUG20
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BUG20
-# endif
-# define machine_is_bug20() (machine_arch_type == MACH_TYPE_BUG20)
-#else
-# define machine_is_bug20() (0)
-#endif
-
-#ifdef CONFIG_MACH_GOFLEXNET
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GOFLEXNET
-# endif
-# define machine_is_goflexnet() (machine_arch_type == MACH_TYPE_GOFLEXNET)
-#else
-# define machine_is_goflexnet() (0)
-#endif
-
-#ifdef CONFIG_MACH_TORBRECK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TORBRECK
-# endif
-# define machine_is_torbreck() (machine_arch_type == MACH_TYPE_TORBRECK)
-#else
-# define machine_is_torbreck() (0)
-#endif
-
-#ifdef CONFIG_MACH_SAARB_MG1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SAARB_MG1
-# endif
-# define machine_is_saarb_mg1() (machine_arch_type == MACH_TYPE_SAARB_MG1)
-#else
-# define machine_is_saarb_mg1() (0)
-#endif
-
-#ifdef CONFIG_MACH_CALLISTO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CALLISTO
-# endif
-# define machine_is_callisto() (machine_arch_type == MACH_TYPE_CALLISTO)
-#else
-# define machine_is_callisto() (0)
-#endif
-
-#ifdef CONFIG_MACH_MULTHSU
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MULTHSU
-# endif
-# define machine_is_multhsu() (machine_arch_type == MACH_TYPE_MULTHSU)
-#else
-# define machine_is_multhsu() (0)
-#endif
-
-#ifdef CONFIG_MACH_SALUDA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SALUDA
-# endif
-# define machine_is_saluda() (machine_arch_type == MACH_TYPE_SALUDA)
-#else
-# define machine_is_saluda() (0)
-#endif
-
-#ifdef CONFIG_MACH_PEMP_OMAP3_APOLLO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PEMP_OMAP3_APOLLO
-# endif
-# define machine_is_pemp_omap3_apollo() (machine_arch_type == MACH_TYPE_PEMP_OMAP3_APOLLO)
-#else
-# define machine_is_pemp_omap3_apollo() (0)
-#endif
-
-#ifdef CONFIG_MACH_VC0718
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VC0718
-# endif
-# define machine_is_vc0718() (machine_arch_type == MACH_TYPE_VC0718)
-#else
-# define machine_is_vc0718() (0)
-#endif
-
-#ifdef CONFIG_MACH_MVBLX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MVBLX
-# endif
-# define machine_is_mvblx() (machine_arch_type == MACH_TYPE_MVBLX)
-#else
-# define machine_is_mvblx() (0)
-#endif
-
-#ifdef CONFIG_MACH_INHAND_APEIRON
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_INHAND_APEIRON
-# endif
-# define machine_is_inhand_apeiron() (machine_arch_type == MACH_TYPE_INHAND_APEIRON)
-#else
-# define machine_is_inhand_apeiron() (0)
-#endif
-
-#ifdef CONFIG_MACH_INHAND_FURY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_INHAND_FURY
-# endif
-# define machine_is_inhand_fury() (machine_arch_type == MACH_TYPE_INHAND_FURY)
-#else
-# define machine_is_inhand_fury() (0)
-#endif
-
-#ifdef CONFIG_MACH_INHAND_SIREN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_INHAND_SIREN
-# endif
-# define machine_is_inhand_siren() (machine_arch_type == MACH_TYPE_INHAND_SIREN)
-#else
-# define machine_is_inhand_siren() (0)
-#endif
-
-#ifdef CONFIG_MACH_HDNVP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HDNVP
-# endif
-# define machine_is_hdnvp() (machine_arch_type == MACH_TYPE_HDNVP)
-#else
-# define machine_is_hdnvp() (0)
-#endif
-
-#ifdef CONFIG_MACH_SOFTWINNER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SOFTWINNER
-# endif
-# define machine_is_softwinner() (machine_arch_type == MACH_TYPE_SOFTWINNER)
-#else
-# define machine_is_softwinner() (0)
-#endif
-
-#ifdef CONFIG_MACH_PRIMA2_EVB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PRIMA2_EVB
-# endif
-# define machine_is_prima2_evb() (machine_arch_type == MACH_TYPE_PRIMA2_EVB)
-#else
-# define machine_is_prima2_evb() (0)
-#endif
-
-#ifdef CONFIG_MACH_NAS6210
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NAS6210
-# endif
-# define machine_is_nas6210() (machine_arch_type == MACH_TYPE_NAS6210)
-#else
-# define machine_is_nas6210() (0)
-#endif
-
-#ifdef CONFIG_MACH_UNISDEV
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_UNISDEV
-# endif
-# define machine_is_unisdev() (machine_arch_type == MACH_TYPE_UNISDEV)
-#else
-# define machine_is_unisdev() (0)
-#endif
-
-#ifdef CONFIG_MACH_SBCA11
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SBCA11
-# endif
-# define machine_is_sbca11() (machine_arch_type == MACH_TYPE_SBCA11)
-#else
-# define machine_is_sbca11() (0)
-#endif
-
-#ifdef CONFIG_MACH_SAGA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SAGA
-# endif
-# define machine_is_saga() (machine_arch_type == MACH_TYPE_SAGA)
-#else
-# define machine_is_saga() (0)
-#endif
-
-#ifdef CONFIG_MACH_NS_K330
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NS_K330
-# endif
-# define machine_is_ns_k330() (machine_arch_type == MACH_TYPE_NS_K330)
-#else
-# define machine_is_ns_k330() (0)
-#endif
-
-#ifdef CONFIG_MACH_TANNA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TANNA
-# endif
-# define machine_is_tanna() (machine_arch_type == MACH_TYPE_TANNA)
-#else
-# define machine_is_tanna() (0)
-#endif
-
-#ifdef CONFIG_MACH_IMATE8502
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IMATE8502
-# endif
-# define machine_is_imate8502() (machine_arch_type == MACH_TYPE_IMATE8502)
-#else
-# define machine_is_imate8502() (0)
-#endif
-
-#ifdef CONFIG_MACH_ASPEN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ASPEN
-# endif
-# define machine_is_aspen() (machine_arch_type == MACH_TYPE_ASPEN)
-#else
-# define machine_is_aspen() (0)
-#endif
-
-#ifdef CONFIG_MACH_DAINTREE_CWAC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DAINTREE_CWAC
-# endif
-# define machine_is_daintree_cwac() (machine_arch_type == MACH_TYPE_DAINTREE_CWAC)
-#else
-# define machine_is_daintree_cwac() (0)
-#endif
-
-#ifdef CONFIG_MACH_ZMX25
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ZMX25
-# endif
-# define machine_is_zmx25() (machine_arch_type == MACH_TYPE_ZMX25)
-#else
-# define machine_is_zmx25() (0)
-#endif
-
-#ifdef CONFIG_MACH_MAPLE1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MAPLE1
-# endif
-# define machine_is_maple1() (machine_arch_type == MACH_TYPE_MAPLE1)
-#else
-# define machine_is_maple1() (0)
-#endif
-
-#ifdef CONFIG_MACH_QSD8X72_SURF
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_QSD8X72_SURF
-# endif
-# define machine_is_qsd8x72_surf() (machine_arch_type == MACH_TYPE_QSD8X72_SURF)
-#else
-# define machine_is_qsd8x72_surf() (0)
-#endif
-
-#ifdef CONFIG_MACH_QSD8X72_FFA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_QSD8X72_FFA
-# endif
-# define machine_is_qsd8x72_ffa() (machine_arch_type == MACH_TYPE_QSD8X72_FFA)
-#else
-# define machine_is_qsd8x72_ffa() (0)
-#endif
-
-#ifdef CONFIG_MACH_ABILENE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ABILENE
-# endif
-# define machine_is_abilene() (machine_arch_type == MACH_TYPE_ABILENE)
-#else
-# define machine_is_abilene() (0)
-#endif
-
-#ifdef CONFIG_MACH_EIGEN_TTR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EIGEN_TTR
-# endif
-# define machine_is_eigen_ttr() (machine_arch_type == MACH_TYPE_EIGEN_TTR)
-#else
-# define machine_is_eigen_ttr() (0)
-#endif
-
-#ifdef CONFIG_MACH_IOMEGA_IX2_200
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IOMEGA_IX2_200
-# endif
-# define machine_is_iomega_ix2_200() (machine_arch_type == MACH_TYPE_IOMEGA_IX2_200)
-#else
-# define machine_is_iomega_ix2_200() (0)
-#endif
-
-#ifdef CONFIG_MACH_CORETEC_VCX7400
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CORETEC_VCX7400
-# endif
-# define machine_is_coretec_vcx7400() (machine_arch_type == MACH_TYPE_CORETEC_VCX7400)
-#else
-# define machine_is_coretec_vcx7400() (0)
-#endif
-
-#ifdef CONFIG_MACH_SANTIAGO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SANTIAGO
-# endif
-# define machine_is_santiago() (machine_arch_type == MACH_TYPE_SANTIAGO)
-#else
-# define machine_is_santiago() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX257SOL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX257SOL
-# endif
-# define machine_is_mx257sol() (machine_arch_type == MACH_TYPE_MX257SOL)
-#else
-# define machine_is_mx257sol() (0)
-#endif
-
-#ifdef CONFIG_MACH_STRASBOURG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_STRASBOURG
-# endif
-# define machine_is_strasbourg() (machine_arch_type == MACH_TYPE_STRASBOURG)
-#else
-# define machine_is_strasbourg() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_FLUID
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8X60_FLUID
-# endif
-# define machine_is_msm8x60_fluid() (machine_arch_type == MACH_TYPE_MSM8X60_FLUID)
-#else
-# define machine_is_msm8x60_fluid() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMARTQV5
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMARTQV5
-# endif
-# define machine_is_smartqv5() (machine_arch_type == MACH_TYPE_SMARTQV5)
-#else
-# define machine_is_smartqv5() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMARTQV3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMARTQV3
-# endif
-# define machine_is_smartqv3() (machine_arch_type == MACH_TYPE_SMARTQV3)
-#else
-# define machine_is_smartqv3() (0)
-#endif
-
-#ifdef CONFIG_MACH_SMARTQV7
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMARTQV7
-# endif
-# define machine_is_smartqv7() (machine_arch_type == MACH_TYPE_SMARTQV7)
-#else
-# define machine_is_smartqv7() (0)
-#endif
-
-#ifdef CONFIG_MACH_PAZ00
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PAZ00
-# endif
-# define machine_is_paz00() (machine_arch_type == MACH_TYPE_PAZ00)
-#else
-# define machine_is_paz00() (0)
-#endif
-
-#ifdef CONFIG_MACH_ACMENETUSFOXG20
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ACMENETUSFOXG20
-# endif
-# define machine_is_acmenetusfoxg20() (machine_arch_type == MACH_TYPE_ACMENETUSFOXG20)
-#else
-# define machine_is_acmenetusfoxg20() (0)
-#endif
-
-#ifdef CONFIG_MACH_FWBD_0404
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FWBD_0404
-# endif
-# define machine_is_fwbd_0404() (machine_arch_type == MACH_TYPE_FWBD_0404)
-#else
-# define machine_is_fwbd_0404() (0)
-#endif
-
-#ifdef CONFIG_MACH_HDGU
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HDGU
-# endif
-# define machine_is_hdgu() (machine_arch_type == MACH_TYPE_HDGU)
-#else
-# define machine_is_hdgu() (0)
-#endif
-
-#ifdef CONFIG_MACH_PYRAMID
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PYRAMID
-# endif
-# define machine_is_pyramid() (machine_arch_type == MACH_TYPE_PYRAMID)
-#else
-# define machine_is_pyramid() (0)
-#endif
-
-#ifdef CONFIG_MACH_EPIPHAN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EPIPHAN
-# endif
-# define machine_is_epiphan() (machine_arch_type == MACH_TYPE_EPIPHAN)
-#else
-# define machine_is_epiphan() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_BENDER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_BENDER
-# endif
-# define machine_is_omap_bender() (machine_arch_type == MACH_TYPE_OMAP_BENDER)
-#else
-# define machine_is_omap_bender() (0)
-#endif
-
-#ifdef CONFIG_MACH_GURNARD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GURNARD
-# endif
-# define machine_is_gurnard() (machine_arch_type == MACH_TYPE_GURNARD)
-#else
-# define machine_is_gurnard() (0)
-#endif
-
-#ifdef CONFIG_MACH_GTL_IT5100
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GTL_IT5100
-# endif
-# define machine_is_gtl_it5100() (machine_arch_type == MACH_TYPE_GTL_IT5100)
-#else
-# define machine_is_gtl_it5100() (0)
-#endif
-
-#ifdef CONFIG_MACH_BCM2708
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BCM2708
-# endif
-# define machine_is_bcm2708() (machine_arch_type == MACH_TYPE_BCM2708)
-#else
-# define machine_is_bcm2708() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_GGC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX51_GGC
-# endif
-# define machine_is_mx51_ggc() (machine_arch_type == MACH_TYPE_MX51_GGC)
-#else
-# define machine_is_mx51_ggc() (0)
-#endif
-
-#ifdef CONFIG_MACH_SHARESPACE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SHARESPACE
-# endif
-# define machine_is_sharespace() (machine_arch_type == MACH_TYPE_SHARESPACE)
-#else
-# define machine_is_sharespace() (0)
-#endif
-
-#ifdef CONFIG_MACH_HABA_KNX_EXPLORER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HABA_KNX_EXPLORER
-# endif
-# define machine_is_haba_knx_explorer() (machine_arch_type == MACH_TYPE_HABA_KNX_EXPLORER)
-#else
-# define machine_is_haba_knx_explorer() (0)
-#endif
-
-#ifdef CONFIG_MACH_SIMTEC_KIRKMOD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SIMTEC_KIRKMOD
-# endif
-# define machine_is_simtec_kirkmod() (machine_arch_type == MACH_TYPE_SIMTEC_KIRKMOD)
-#else
-# define machine_is_simtec_kirkmod() (0)
-#endif
-
-#ifdef CONFIG_MACH_CRUX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CRUX
-# endif
-# define machine_is_crux() (machine_arch_type == MACH_TYPE_CRUX)
-#else
-# define machine_is_crux() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_BRAVO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX51_BRAVO
-# endif
-# define machine_is_mx51_bravo() (machine_arch_type == MACH_TYPE_MX51_BRAVO)
-#else
-# define machine_is_mx51_bravo() (0)
-#endif
-
-#ifdef CONFIG_MACH_CHARON
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CHARON
-# endif
-# define machine_is_charon() (machine_arch_type == MACH_TYPE_CHARON)
-#else
-# define machine_is_charon() (0)
-#endif
-
-#ifdef CONFIG_MACH_PICOCOM3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PICOCOM3
-# endif
-# define machine_is_picocom3() (machine_arch_type == MACH_TYPE_PICOCOM3)
-#else
-# define machine_is_picocom3() (0)
-#endif
-
-#ifdef CONFIG_MACH_PICOCOM4
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PICOCOM4
-# endif
-# define machine_is_picocom4() (machine_arch_type == MACH_TYPE_PICOCOM4)
-#else
-# define machine_is_picocom4() (0)
-#endif
-
-#ifdef CONFIG_MACH_SERRANO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SERRANO
-# endif
-# define machine_is_serrano() (machine_arch_type == MACH_TYPE_SERRANO)
-#else
-# define machine_is_serrano() (0)
-#endif
-
-#ifdef CONFIG_MACH_DOUBLESHOT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DOUBLESHOT
-# endif
-# define machine_is_doubleshot() (machine_arch_type == MACH_TYPE_DOUBLESHOT)
-#else
-# define machine_is_doubleshot() (0)
-#endif
-
-#ifdef CONFIG_MACH_EVSY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EVSY
-# endif
-# define machine_is_evsy() (machine_arch_type == MACH_TYPE_EVSY)
-#else
-# define machine_is_evsy() (0)
-#endif
-
-#ifdef CONFIG_MACH_HUASHAN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HUASHAN
-# endif
-# define machine_is_huashan() (machine_arch_type == MACH_TYPE_HUASHAN)
-#else
-# define machine_is_huashan() (0)
-#endif
-
-#ifdef CONFIG_MACH_LAUSANNE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LAUSANNE
-# endif
-# define machine_is_lausanne() (machine_arch_type == MACH_TYPE_LAUSANNE)
-#else
-# define machine_is_lausanne() (0)
-#endif
-
-#ifdef CONFIG_MACH_EMERALD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EMERALD
-# endif
-# define machine_is_emerald() (machine_arch_type == MACH_TYPE_EMERALD)
-#else
-# define machine_is_emerald() (0)
-#endif
-
-#ifdef CONFIG_MACH_TQMA35
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TQMA35
-# endif
-# define machine_is_tqma35() (machine_arch_type == MACH_TYPE_TQMA35)
-#else
-# define machine_is_tqma35() (0)
-#endif
-
-#ifdef CONFIG_MACH_MARVEL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MARVEL
-# endif
-# define machine_is_marvel() (machine_arch_type == MACH_TYPE_MARVEL)
-#else
-# define machine_is_marvel() (0)
-#endif
-
-#ifdef CONFIG_MACH_MANUAE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MANUAE
-# endif
-# define machine_is_manuae() (machine_arch_type == MACH_TYPE_MANUAE)
-#else
-# define machine_is_manuae() (0)
-#endif
-
-#ifdef CONFIG_MACH_CHACHA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CHACHA
-# endif
-# define machine_is_chacha() (machine_arch_type == MACH_TYPE_CHACHA)
-#else
-# define machine_is_chacha() (0)
-#endif
-
-#ifdef CONFIG_MACH_LEMON
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LEMON
-# endif
-# define machine_is_lemon() (machine_arch_type == MACH_TYPE_LEMON)
-#else
-# define machine_is_lemon() (0)
-#endif
-
-#ifdef CONFIG_MACH_CSC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CSC
-# endif
-# define machine_is_csc() (machine_arch_type == MACH_TYPE_CSC)
-#else
-# define machine_is_csc() (0)
-#endif
-
-#ifdef CONFIG_MACH_GIRA_KNXIP_ROUTER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GIRA_KNXIP_ROUTER
-# endif
-# define machine_is_gira_knxip_router() (machine_arch_type == MACH_TYPE_GIRA_KNXIP_ROUTER)
-#else
-# define machine_is_gira_knxip_router() (0)
-#endif
-
-#ifdef CONFIG_MACH_T20
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_T20
-# endif
-# define machine_is_t20() (machine_arch_type == MACH_TYPE_T20)
-#else
-# define machine_is_t20() (0)
-#endif
-
-#ifdef CONFIG_MACH_HDMINI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HDMINI
-# endif
-# define machine_is_hdmini() (machine_arch_type == MACH_TYPE_HDMINI)
-#else
-# define machine_is_hdmini() (0)
-#endif
-
-#ifdef CONFIG_MACH_SCIPHONE_G2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SCIPHONE_G2
-# endif
-# define machine_is_sciphone_g2() (machine_arch_type == MACH_TYPE_SCIPHONE_G2)
-#else
-# define machine_is_sciphone_g2() (0)
-#endif
-
-#ifdef CONFIG_MACH_EXPRESS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EXPRESS
-# endif
-# define machine_is_express() (machine_arch_type == MACH_TYPE_EXPRESS)
-#else
-# define machine_is_express() (0)
-#endif
-
-#ifdef CONFIG_MACH_EXPRESS_KT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EXPRESS_KT
-# endif
-# define machine_is_express_kt() (machine_arch_type == MACH_TYPE_EXPRESS_KT)
-#else
-# define machine_is_express_kt() (0)
-#endif
-
-#ifdef CONFIG_MACH_MAXIMASP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MAXIMASP
-# endif
-# define machine_is_maximasp() (machine_arch_type == MACH_TYPE_MAXIMASP)
-#else
-# define machine_is_maximasp() (0)
-#endif
-
-#ifdef CONFIG_MACH_NITROGEN_IMX51
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NITROGEN_IMX51
-# endif
-# define machine_is_nitrogen_imx51() (machine_arch_type == MACH_TYPE_NITROGEN_IMX51)
-#else
-# define machine_is_nitrogen_imx51() (0)
-#endif
-
-#ifdef CONFIG_MACH_NITROGEN_IMX53
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NITROGEN_IMX53
-# endif
-# define machine_is_nitrogen_imx53() (machine_arch_type == MACH_TYPE_NITROGEN_IMX53)
-#else
-# define machine_is_nitrogen_imx53() (0)
-#endif
-
-#ifdef CONFIG_MACH_SUNFIRE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SUNFIRE
-# endif
-# define machine_is_sunfire() (machine_arch_type == MACH_TYPE_SUNFIRE)
-#else
-# define machine_is_sunfire() (0)
-#endif
-
-#ifdef CONFIG_MACH_AROWANA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AROWANA
-# endif
-# define machine_is_arowana() (machine_arch_type == MACH_TYPE_AROWANA)
-#else
-# define machine_is_arowana() (0)
-#endif
-
-#ifdef CONFIG_MACH_TEGRA_DAYTONA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TEGRA_DAYTONA
-# endif
-# define machine_is_tegra_daytona() (machine_arch_type == MACH_TYPE_TEGRA_DAYTONA)
-#else
-# define machine_is_tegra_daytona() (0)
-#endif
-
-#ifdef CONFIG_MACH_TEGRA_SWORDFISH
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TEGRA_SWORDFISH
-# endif
-# define machine_is_tegra_swordfish() (machine_arch_type == MACH_TYPE_TEGRA_SWORDFISH)
-#else
-# define machine_is_tegra_swordfish() (0)
-#endif
-
-#ifdef CONFIG_MACH_EDISON
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EDISON
-# endif
-# define machine_is_edison() (machine_arch_type == MACH_TYPE_EDISON)
-#else
-# define machine_is_edison() (0)
-#endif
-
-#ifdef CONFIG_MACH_SVP8500V1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SVP8500V1
-# endif
-# define machine_is_svp8500v1() (machine_arch_type == MACH_TYPE_SVP8500V1)
-#else
-# define machine_is_svp8500v1() (0)
-#endif
-
-#ifdef CONFIG_MACH_SVP8500V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SVP8500V2
-# endif
-# define machine_is_svp8500v2() (machine_arch_type == MACH_TYPE_SVP8500V2)
-#else
-# define machine_is_svp8500v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_SVP5500
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SVP5500
-# endif
-# define machine_is_svp5500() (machine_arch_type == MACH_TYPE_SVP5500)
-#else
-# define machine_is_svp5500() (0)
-#endif
-
-#ifdef CONFIG_MACH_B5500
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_B5500
-# endif
-# define machine_is_b5500() (machine_arch_type == MACH_TYPE_B5500)
-#else
-# define machine_is_b5500() (0)
-#endif
-
-#ifdef CONFIG_MACH_S5500
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_S5500
-# endif
-# define machine_is_s5500() (machine_arch_type == MACH_TYPE_S5500)
-#else
-# define machine_is_s5500() (0)
-#endif
-
-#ifdef CONFIG_MACH_ICON
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ICON
-# endif
-# define machine_is_icon() (machine_arch_type == MACH_TYPE_ICON)
-#else
-# define machine_is_icon() (0)
-#endif
-
-#ifdef CONFIG_MACH_ELEPHANT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ELEPHANT
-# endif
-# define machine_is_elephant() (machine_arch_type == MACH_TYPE_ELEPHANT)
-#else
-# define machine_is_elephant() (0)
-#endif
-
-#ifdef CONFIG_MACH_SHOOTER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SHOOTER
-# endif
-# define machine_is_shooter() (machine_arch_type == MACH_TYPE_SHOOTER)
-#else
-# define machine_is_shooter() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPADE_LTE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPADE_LTE
-# endif
-# define machine_is_spade_lte() (machine_arch_type == MACH_TYPE_SPADE_LTE)
-#else
-# define machine_is_spade_lte() (0)
-#endif
-
-#ifdef CONFIG_MACH_PHILHWANI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PHILHWANI
-# endif
-# define machine_is_philhwani() (machine_arch_type == MACH_TYPE_PHILHWANI)
-#else
-# define machine_is_philhwani() (0)
-#endif
-
-#ifdef CONFIG_MACH_GSNCOMM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GSNCOMM
-# endif
-# define machine_is_gsncomm() (machine_arch_type == MACH_TYPE_GSNCOMM)
-#else
-# define machine_is_gsncomm() (0)
-#endif
-
-#ifdef CONFIG_MACH_STRASBOURG_A2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_STRASBOURG_A2
-# endif
-# define machine_is_strasbourg_a2() (machine_arch_type == MACH_TYPE_STRASBOURG_A2)
-#else
-# define machine_is_strasbourg_a2() (0)
-#endif
-
-#ifdef CONFIG_MACH_MMM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MMM
-# endif
-# define machine_is_mmm() (machine_arch_type == MACH_TYPE_MMM)
-#else
-# define machine_is_mmm() (0)
-#endif
-
-#ifdef CONFIG_MACH_DAVINCI_DM365_BV
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DAVINCI_DM365_BV
-# endif
-# define machine_is_davinci_dm365_bv() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_BV)
-#else
-# define machine_is_davinci_dm365_bv() (0)
-#endif
-
-#ifdef CONFIG_MACH_AG5EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AG5EVM
-# endif
-# define machine_is_ag5evm() (machine_arch_type == MACH_TYPE_AG5EVM)
-#else
-# define machine_is_ag5evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_SC575PLC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SC575PLC
-# endif
-# define machine_is_sc575plc() (machine_arch_type == MACH_TYPE_SC575PLC)
-#else
-# define machine_is_sc575plc() (0)
-#endif
-
-#ifdef CONFIG_MACH_SC575IPC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SC575IPC
-# endif
-# define machine_is_sc575hmi() (machine_arch_type == MACH_TYPE_SC575IPC)
-#else
-# define machine_is_sc575hmi() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_TDM3730
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3_TDM3730
-# endif
-# define machine_is_omap3_tdm3730() (machine_arch_type == MACH_TYPE_OMAP3_TDM3730)
-#else
-# define machine_is_omap3_tdm3730() (0)
-#endif
-
-#ifdef CONFIG_MACH_TOP9000_EVAL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TOP9000_EVAL
-# endif
-# define machine_is_top9000_eval() (machine_arch_type == MACH_TYPE_TOP9000_EVAL)
-#else
-# define machine_is_top9000_eval() (0)
-#endif
-
-#ifdef CONFIG_MACH_TOP9000_SU
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TOP9000_SU
-# endif
-# define machine_is_top9000_su() (machine_arch_type == MACH_TYPE_TOP9000_SU)
-#else
-# define machine_is_top9000_su() (0)
-#endif
-
-#ifdef CONFIG_MACH_UTM300
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_UTM300
-# endif
-# define machine_is_utm300() (machine_arch_type == MACH_TYPE_UTM300)
-#else
-# define machine_is_utm300() (0)
-#endif
-
-#ifdef CONFIG_MACH_TSUNAGI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TSUNAGI
-# endif
-# define machine_is_tsunagi() (machine_arch_type == MACH_TYPE_TSUNAGI)
-#else
-# define machine_is_tsunagi() (0)
-#endif
-
-#ifdef CONFIG_MACH_TS75XX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TS75XX
-# endif
-# define machine_is_ts75xx() (machine_arch_type == MACH_TYPE_TS75XX)
-#else
-# define machine_is_ts75xx() (0)
-#endif
-
-#ifdef CONFIG_MACH_TS47XX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TS47XX
-# endif
-# define machine_is_ts47xx() (machine_arch_type == MACH_TYPE_TS47XX)
-#else
-# define machine_is_ts47xx() (0)
-#endif
-
-#ifdef CONFIG_MACH_DA850_K5
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DA850_K5
-# endif
-# define machine_is_da850_k5() (machine_arch_type == MACH_TYPE_DA850_K5)
-#else
-# define machine_is_da850_k5() (0)
-#endif
-
-#ifdef CONFIG_MACH_AX502
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AX502
-# endif
-# define machine_is_ax502() (machine_arch_type == MACH_TYPE_AX502)
-#else
-# define machine_is_ax502() (0)
-#endif
-
-#ifdef CONFIG_MACH_IGEP0032
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IGEP0032
-# endif
-# define machine_is_igep0032() (machine_arch_type == MACH_TYPE_IGEP0032)
-#else
-# define machine_is_igep0032() (0)
-#endif
-
-#ifdef CONFIG_MACH_ANTERO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ANTERO
-# endif
-# define machine_is_antero() (machine_arch_type == MACH_TYPE_ANTERO)
-#else
-# define machine_is_antero() (0)
-#endif
-
-#ifdef CONFIG_MACH_SYNERGY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SYNERGY
-# endif
-# define machine_is_synergy() (machine_arch_type == MACH_TYPE_SYNERGY)
-#else
-# define machine_is_synergy() (0)
-#endif
-
-#ifdef CONFIG_MACH_ICS_IF_VOIP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ICS_IF_VOIP
-# endif
-# define machine_is_ics_if_voip() (machine_arch_type == MACH_TYPE_ICS_IF_VOIP)
-#else
-# define machine_is_ics_if_voip() (0)
-#endif
-
-#ifdef CONFIG_MACH_WLF_CRAGG_6410
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WLF_CRAGG_6410
-# endif
-# define machine_is_wlf_cragg_6410() (machine_arch_type == MACH_TYPE_WLF_CRAGG_6410)
-#else
-# define machine_is_wlf_cragg_6410() (0)
-#endif
-
-#ifdef CONFIG_MACH_PUNICA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PUNICA
-# endif
-# define machine_is_punica() (machine_arch_type == MACH_TYPE_PUNICA)
-#else
-# define machine_is_punica() (0)
-#endif
-
-#ifdef CONFIG_MACH_TRIMSLICE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TRIMSLICE
-# endif
-# define machine_is_trimslice() (machine_arch_type == MACH_TYPE_TRIMSLICE)
-#else
-# define machine_is_trimslice() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX27_WMULTRA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX27_WMULTRA
-# endif
-# define machine_is_mx27_wmultra() (machine_arch_type == MACH_TYPE_MX27_WMULTRA)
-#else
-# define machine_is_mx27_wmultra() (0)
-#endif
-
-#ifdef CONFIG_MACH_MACKEREL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MACKEREL
-# endif
-# define machine_is_mackerel() (machine_arch_type == MACH_TYPE_MACKEREL)
-#else
-# define machine_is_mackerel() (0)
-#endif
-
-#ifdef CONFIG_MACH_FA9X27
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FA9X27
-# endif
-# define machine_is_fa9x27() (machine_arch_type == MACH_TYPE_FA9X27)
-#else
-# define machine_is_fa9x27() (0)
-#endif
-
-#ifdef CONFIG_MACH_NS2816TB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NS2816TB
-# endif
-# define machine_is_ns2816tb() (machine_arch_type == MACH_TYPE_NS2816TB)
-#else
-# define machine_is_ns2816tb() (0)
-#endif
-
-#ifdef CONFIG_MACH_NS2816_NTPAD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NS2816_NTPAD
-# endif
-# define machine_is_ns2816_ntpad() (machine_arch_type == MACH_TYPE_NS2816_NTPAD)
-#else
-# define machine_is_ns2816_ntpad() (0)
-#endif
-
-#ifdef CONFIG_MACH_NS2816_NTNB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NS2816_NTNB
-# endif
-# define machine_is_ns2816_ntnb() (machine_arch_type == MACH_TYPE_NS2816_NTNB)
-#else
-# define machine_is_ns2816_ntnb() (0)
-#endif
-
-#ifdef CONFIG_MACH_KAEN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KAEN
-# endif
-# define machine_is_kaen() (machine_arch_type == MACH_TYPE_KAEN)
-#else
-# define machine_is_kaen() (0)
-#endif
-
-#ifdef CONFIG_MACH_NV1000
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NV1000
-# endif
-# define machine_is_nv1000() (machine_arch_type == MACH_TYPE_NV1000)
-#else
-# define machine_is_nv1000() (0)
-#endif
-
-#ifdef CONFIG_MACH_NUC950TS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NUC950TS
-# endif
-# define machine_is_nuc950ts() (machine_arch_type == MACH_TYPE_NUC950TS)
-#else
-# define machine_is_nuc950ts() (0)
-#endif
-
-#ifdef CONFIG_MACH_NOKIA_RM680
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NOKIA_RM680
-# endif
-# define machine_is_nokia_rm680() (machine_arch_type == MACH_TYPE_NOKIA_RM680)
-#else
-# define machine_is_nokia_rm680() (0)
-#endif
-
-#ifdef CONFIG_MACH_AST2200
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AST2200
-# endif
-# define machine_is_ast2200() (machine_arch_type == MACH_TYPE_AST2200)
-#else
-# define machine_is_ast2200() (0)
-#endif
-
-#ifdef CONFIG_MACH_LEAD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LEAD
-# endif
-# define machine_is_lead() (machine_arch_type == MACH_TYPE_LEAD)
-#else
-# define machine_is_lead() (0)
-#endif
-
-#ifdef CONFIG_MACH_UNINO1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_UNINO1
-# endif
-# define machine_is_unino1() (machine_arch_type == MACH_TYPE_UNINO1)
-#else
-# define machine_is_unino1() (0)
-#endif
-
-#ifdef CONFIG_MACH_GREECO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GREECO
-# endif
-# define machine_is_greeco() (machine_arch_type == MACH_TYPE_GREECO)
-#else
-# define machine_is_greeco() (0)
-#endif
-
-#ifdef CONFIG_MACH_VERDI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VERDI
-# endif
-# define machine_is_verdi() (machine_arch_type == MACH_TYPE_VERDI)
-#else
-# define machine_is_verdi() (0)
-#endif
-
-#ifdef CONFIG_MACH_DM6446_ADBOX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DM6446_ADBOX
-# endif
-# define machine_is_dm6446_adbox() (machine_arch_type == MACH_TYPE_DM6446_ADBOX)
-#else
-# define machine_is_dm6446_adbox() (0)
-#endif
-
-#ifdef CONFIG_MACH_QUAD_SALSA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_QUAD_SALSA
-# endif
-# define machine_is_quad_salsa() (machine_arch_type == MACH_TYPE_QUAD_SALSA)
-#else
-# define machine_is_quad_salsa() (0)
-#endif
-
-#ifdef CONFIG_MACH_ABB_GMA_1_1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ABB_GMA_1_1
-# endif
-# define machine_is_abb_gma_1_1() (machine_arch_type == MACH_TYPE_ABB_GMA_1_1)
-#else
-# define machine_is_abb_gma_1_1() (0)
-#endif
-
-#ifdef CONFIG_MACH_SVCID
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SVCID
-# endif
-# define machine_is_svcid() (machine_arch_type == MACH_TYPE_SVCID)
-#else
-# define machine_is_svcid() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8960_SIM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8960_SIM
-# endif
-# define machine_is_msm8960_sim() (machine_arch_type == MACH_TYPE_MSM8960_SIM)
-#else
-# define machine_is_msm8960_sim() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8960_RUMI3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8960_RUMI3
-# endif
-# define machine_is_msm8960_rumi3() (machine_arch_type == MACH_TYPE_MSM8960_RUMI3)
-#else
-# define machine_is_msm8960_rumi3() (0)
-#endif
-
-#ifdef CONFIG_MACH_ICON_G
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ICON_G
-# endif
-# define machine_is_icon_g() (machine_arch_type == MACH_TYPE_ICON_G)
-#else
-# define machine_is_icon_g() (0)
-#endif
-
-#ifdef CONFIG_MACH_MB3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MB3
-# endif
-# define machine_is_mb3() (machine_arch_type == MACH_TYPE_MB3)
-#else
-# define machine_is_mb3() (0)
-#endif
-
-#ifdef CONFIG_MACH_GSIA18S
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GSIA18S
-# endif
-# define machine_is_gsia18s() (machine_arch_type == MACH_TYPE_GSIA18S)
-#else
-# define machine_is_gsia18s() (0)
-#endif
-
-#ifdef CONFIG_MACH_PIVICC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PIVICC
-# endif
-# define machine_is_pivicc() (machine_arch_type == MACH_TYPE_PIVICC)
-#else
-# define machine_is_pivicc() (0)
-#endif
-
-#ifdef CONFIG_MACH_PCM048
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PCM048
-# endif
-# define machine_is_pcm048() (machine_arch_type == MACH_TYPE_PCM048)
-#else
-# define machine_is_pcm048() (0)
-#endif
-
-#ifdef CONFIG_MACH_DDS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DDS
-# endif
-# define machine_is_dds() (machine_arch_type == MACH_TYPE_DDS)
-#else
-# define machine_is_dds() (0)
-#endif
-
-#ifdef CONFIG_MACH_CHALTEN_XA1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CHALTEN_XA1
-# endif
-# define machine_is_chalten_xa1() (machine_arch_type == MACH_TYPE_CHALTEN_XA1)
-#else
-# define machine_is_chalten_xa1() (0)
-#endif
-
-#ifdef CONFIG_MACH_TS48XX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TS48XX
-# endif
-# define machine_is_ts48xx() (machine_arch_type == MACH_TYPE_TS48XX)
-#else
-# define machine_is_ts48xx() (0)
-#endif
-
-#ifdef CONFIG_MACH_TONGA2_TFTTIMER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TONGA2_TFTTIMER
-# endif
-# define machine_is_tonga2_tfttimer() (machine_arch_type == MACH_TYPE_TONGA2_TFTTIMER)
-#else
-# define machine_is_tonga2_tfttimer() (0)
-#endif
-
-#ifdef CONFIG_MACH_WHISTLER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WHISTLER
-# endif
-# define machine_is_whistler() (machine_arch_type == MACH_TYPE_WHISTLER)
-#else
-# define machine_is_whistler() (0)
-#endif
-
-#ifdef CONFIG_MACH_ASL_PHOENIX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ASL_PHOENIX
-# endif
-# define machine_is_asl_phoenix() (machine_arch_type == MACH_TYPE_ASL_PHOENIX)
-#else
-# define machine_is_asl_phoenix() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9263OTLITE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91SAM9263OTLITE
-# endif
-# define machine_is_at91sam9263otlite() (machine_arch_type == MACH_TYPE_AT91SAM9263OTLITE)
-#else
-# define machine_is_at91sam9263otlite() (0)
-#endif
-
-#ifdef CONFIG_MACH_DDPLUG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DDPLUG
-# endif
-# define machine_is_ddplug() (machine_arch_type == MACH_TYPE_DDPLUG)
-#else
-# define machine_is_ddplug() (0)
-#endif
-
-#ifdef CONFIG_MACH_D2PLUG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_D2PLUG
-# endif
-# define machine_is_d2plug() (machine_arch_type == MACH_TYPE_D2PLUG)
-#else
-# define machine_is_d2plug() (0)
-#endif
-
-#ifdef CONFIG_MACH_KZM9D
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KZM9D
-# endif
-# define machine_is_kzm9d() (machine_arch_type == MACH_TYPE_KZM9D)
-#else
-# define machine_is_kzm9d() (0)
-#endif
-
-#ifdef CONFIG_MACH_VERDI_LTE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VERDI_LTE
-# endif
-# define machine_is_verdi_lte() (machine_arch_type == MACH_TYPE_VERDI_LTE)
-#else
-# define machine_is_verdi_lte() (0)
-#endif
-
-#ifdef CONFIG_MACH_NANOZOOM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NANOZOOM
-# endif
-# define machine_is_nanozoom() (machine_arch_type == MACH_TYPE_NANOZOOM)
-#else
-# define machine_is_nanozoom() (0)
-#endif
-
-#ifdef CONFIG_MACH_DM3730_SOM_LV
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DM3730_SOM_LV
-# endif
-# define machine_is_dm3730_som_lv() (machine_arch_type == MACH_TYPE_DM3730_SOM_LV)
-#else
-# define machine_is_dm3730_som_lv() (0)
-#endif
-
-#ifdef CONFIG_MACH_DM3730_TORPEDO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DM3730_TORPEDO
-# endif
-# define machine_is_dm3730_torpedo() (machine_arch_type == MACH_TYPE_DM3730_TORPEDO)
-#else
-# define machine_is_dm3730_torpedo() (0)
-#endif
-
-#ifdef CONFIG_MACH_ANCHOVY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ANCHOVY
-# endif
-# define machine_is_anchovy() (machine_arch_type == MACH_TYPE_ANCHOVY)
-#else
-# define machine_is_anchovy() (0)
-#endif
-
-#ifdef CONFIG_MACH_RE2REV20
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RE2REV20
-# endif
-# define machine_is_re2rev20() (machine_arch_type == MACH_TYPE_RE2REV20)
-#else
-# define machine_is_re2rev20() (0)
-#endif
-
-#ifdef CONFIG_MACH_RE2REV21
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RE2REV21
-# endif
-# define machine_is_re2rev21() (machine_arch_type == MACH_TYPE_RE2REV21)
-#else
-# define machine_is_re2rev21() (0)
-#endif
-
-#ifdef CONFIG_MACH_CNS21XX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CNS21XX
-# endif
-# define machine_is_cns21xx() (machine_arch_type == MACH_TYPE_CNS21XX)
-#else
-# define machine_is_cns21xx() (0)
-#endif
-
-#ifdef CONFIG_MACH_RIDER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RIDER
-# endif
-# define machine_is_rider() (machine_arch_type == MACH_TYPE_RIDER)
-#else
-# define machine_is_rider() (0)
-#endif
-
-#ifdef CONFIG_MACH_NSK330
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NSK330
-# endif
-# define machine_is_nsk330() (machine_arch_type == MACH_TYPE_NSK330)
-#else
-# define machine_is_nsk330() (0)
-#endif
-
-#ifdef CONFIG_MACH_CNS2133EVB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CNS2133EVB
-# endif
-# define machine_is_cns2133evb() (machine_arch_type == MACH_TYPE_CNS2133EVB)
-#else
-# define machine_is_cns2133evb() (0)
-#endif
-
-#ifdef CONFIG_MACH_Z3_816X_MOD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_Z3_816X_MOD
-# endif
-# define machine_is_z3_816x_mod() (machine_arch_type == MACH_TYPE_Z3_816X_MOD)
-#else
-# define machine_is_z3_816x_mod() (0)
-#endif
-
-#ifdef CONFIG_MACH_Z3_814X_MOD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_Z3_814X_MOD
-# endif
-# define machine_is_z3_814x_mod() (machine_arch_type == MACH_TYPE_Z3_814X_MOD)
-#else
-# define machine_is_z3_814x_mod() (0)
-#endif
-
-#ifdef CONFIG_MACH_BEECT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BEECT
-# endif
-# define machine_is_beect() (machine_arch_type == MACH_TYPE_BEECT)
-#else
-# define machine_is_beect() (0)
-#endif
-
-#ifdef CONFIG_MACH_DMA_THUNDERBUG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DMA_THUNDERBUG
-# endif
-# define machine_is_dma_thunderbug() (machine_arch_type == MACH_TYPE_DMA_THUNDERBUG)
-#else
-# define machine_is_dma_thunderbug() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMN_AT91SAM9G20
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMN_AT91SAM9G20
-# endif
-# define machine_is_omn_at91sam9g20() (machine_arch_type == MACH_TYPE_OMN_AT91SAM9G20)
-#else
-# define machine_is_omn_at91sam9g20() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX25_E2S_UC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX25_E2S_UC
-# endif
-# define machine_is_mx25_e2s_uc() (machine_arch_type == MACH_TYPE_MX25_E2S_UC)
-#else
-# define machine_is_mx25_e2s_uc() (0)
-#endif
-
-#ifdef CONFIG_MACH_MIONE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MIONE
-# endif
-# define machine_is_mione() (machine_arch_type == MACH_TYPE_MIONE)
-#else
-# define machine_is_mione() (0)
-#endif
-
-#ifdef CONFIG_MACH_TOP9000_TCU
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TOP9000_TCU
-# endif
-# define machine_is_top9000_tcu() (machine_arch_type == MACH_TYPE_TOP9000_TCU)
-#else
-# define machine_is_top9000_tcu() (0)
-#endif
-
-#ifdef CONFIG_MACH_TOP9000_BSL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TOP9000_BSL
-# endif
-# define machine_is_top9000_bsl() (machine_arch_type == MACH_TYPE_TOP9000_BSL)
-#else
-# define machine_is_top9000_bsl() (0)
-#endif
-
-#ifdef CONFIG_MACH_KINGDOM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KINGDOM
-# endif
-# define machine_is_kingdom() (machine_arch_type == MACH_TYPE_KINGDOM)
-#else
-# define machine_is_kingdom() (0)
-#endif
-
-#ifdef CONFIG_MACH_ARMADILLO460
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ARMADILLO460
-# endif
-# define machine_is_armadillo460() (machine_arch_type == MACH_TYPE_ARMADILLO460)
-#else
-# define machine_is_armadillo460() (0)
-#endif
-
-#ifdef CONFIG_MACH_LQ2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LQ2
-# endif
-# define machine_is_lq2() (machine_arch_type == MACH_TYPE_LQ2)
-#else
-# define machine_is_lq2() (0)
-#endif
-
-#ifdef CONFIG_MACH_SWEDA_TMS2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SWEDA_TMS2
-# endif
-# define machine_is_sweda_tms2() (machine_arch_type == MACH_TYPE_SWEDA_TMS2)
-#else
-# define machine_is_sweda_tms2() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX53_LOCO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX53_LOCO
-# endif
-# define machine_is_mx53_loco() (machine_arch_type == MACH_TYPE_MX53_LOCO)
-#else
-# define machine_is_mx53_loco() (0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_A8
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ACER_A8
-# endif
-# define machine_is_acer_a8() (machine_arch_type == MACH_TYPE_ACER_A8)
-#else
-# define machine_is_acer_a8() (0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_GAUGUIN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ACER_GAUGUIN
-# endif
-# define machine_is_acer_gauguin() (machine_arch_type == MACH_TYPE_ACER_GAUGUIN)
-#else
-# define machine_is_acer_gauguin() (0)
-#endif
-
-#ifdef CONFIG_MACH_GUPPY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GUPPY
-# endif
-# define machine_is_guppy() (machine_arch_type == MACH_TYPE_GUPPY)
-#else
-# define machine_is_guppy() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX61_ARD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX61_ARD
-# endif
-# define machine_is_mx61_ard() (machine_arch_type == MACH_TYPE_MX61_ARD)
-#else
-# define machine_is_mx61_ard() (0)
-#endif
-
-#ifdef CONFIG_MACH_TX53
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TX53
-# endif
-# define machine_is_tx53() (machine_arch_type == MACH_TYPE_TX53)
-#else
-# define machine_is_tx53() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAPL138_CASE_A3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAPL138_CASE_A3
-# endif
-# define machine_is_omapl138_case_a3() (machine_arch_type == MACH_TYPE_OMAPL138_CASE_A3)
-#else
-# define machine_is_omapl138_case_a3() (0)
-#endif
-
-#ifdef CONFIG_MACH_UEMD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_UEMD
-# endif
-# define machine_is_uemd() (machine_arch_type == MACH_TYPE_UEMD)
-#else
-# define machine_is_uemd() (0)
-#endif
-
-#ifdef CONFIG_MACH_CCWMX51MUT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CCWMX51MUT
-# endif
-# define machine_is_ccwmx51mut() (machine_arch_type == MACH_TYPE_CCWMX51MUT)
-#else
-# define machine_is_ccwmx51mut() (0)
-#endif
-
-#ifdef CONFIG_MACH_ROCKHOPPER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ROCKHOPPER
-# endif
-# define machine_is_rockhopper() (machine_arch_type == MACH_TYPE_ROCKHOPPER)
-#else
-# define machine_is_rockhopper() (0)
-#endif
-
-#ifdef CONFIG_MACH_ENCORE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ENCORE
-# endif
-# define machine_is_encore() (machine_arch_type == MACH_TYPE_ENCORE)
-#else
-# define machine_is_encore() (0)
-#endif
-
-#ifdef CONFIG_MACH_HKDKC100
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HKDKC100
-# endif
-# define machine_is_hkdkc100() (machine_arch_type == MACH_TYPE_HKDKC100)
-#else
-# define machine_is_hkdkc100() (0)
-#endif
-
-#ifdef CONFIG_MACH_TS42XX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TS42XX
-# endif
-# define machine_is_ts42xx() (machine_arch_type == MACH_TYPE_TS42XX)
-#else
-# define machine_is_ts42xx() (0)
-#endif
-
-#ifdef CONFIG_MACH_AEBL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AEBL
-# endif
-# define machine_is_aebl() (machine_arch_type == MACH_TYPE_AEBL)
-#else
-# define machine_is_aebl() (0)
-#endif
-
-#ifdef CONFIG_MACH_WARIO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WARIO
-# endif
-# define machine_is_wario() (machine_arch_type == MACH_TYPE_WARIO)
-#else
-# define machine_is_wario() (0)
-#endif
-
-#ifdef CONFIG_MACH_GFS_SPM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GFS_SPM
-# endif
-# define machine_is_gfs_spm() (machine_arch_type == MACH_TYPE_GFS_SPM)
-#else
-# define machine_is_gfs_spm() (0)
-#endif
-
-#ifdef CONFIG_MACH_CM_T3730
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CM_T3730
-# endif
-# define machine_is_cm_t3730() (machine_arch_type == MACH_TYPE_CM_T3730)
-#else
-# define machine_is_cm_t3730() (0)
-#endif
-
-#ifdef CONFIG_MACH_ISC3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ISC3
-# endif
-# define machine_is_isc3() (machine_arch_type == MACH_TYPE_ISC3)
-#else
-# define machine_is_isc3() (0)
-#endif
-
-#ifdef CONFIG_MACH_RASCAL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RASCAL
-# endif
-# define machine_is_rascal() (machine_arch_type == MACH_TYPE_RASCAL)
-#else
-# define machine_is_rascal() (0)
-#endif
-
-#ifdef CONFIG_MACH_HREFV60
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HREFV60
-# endif
-# define machine_is_hrefv60() (machine_arch_type == MACH_TYPE_HREFV60)
-#else
-# define machine_is_hrefv60() (0)
-#endif
-
-#ifdef CONFIG_MACH_TPT_2_0
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TPT_2_0
-# endif
-# define machine_is_tpt_2_0() (machine_arch_type == MACH_TYPE_TPT_2_0)
-#else
-# define machine_is_tpt_2_0() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPLENDOR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPLENDOR
-# endif
-# define machine_is_splendor() (machine_arch_type == MACH_TYPE_SPLENDOR)
-#else
-# define machine_is_splendor() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8X60_QT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8X60_QT
-# endif
-# define machine_is_msm8x60_qt() (machine_arch_type == MACH_TYPE_MSM8X60_QT)
-#else
-# define machine_is_msm8x60_qt() (0)
-#endif
-
-#ifdef CONFIG_MACH_HTC_HD_MINI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HTC_HD_MINI
-# endif
-# define machine_is_htc_hd_mini() (machine_arch_type == MACH_TYPE_HTC_HD_MINI)
-#else
-# define machine_is_htc_hd_mini() (0)
-#endif
-
-#ifdef CONFIG_MACH_ATHENE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ATHENE
-# endif
-# define machine_is_athene() (machine_arch_type == MACH_TYPE_ATHENE)
-#else
-# define machine_is_athene() (0)
-#endif
-
-#ifdef CONFIG_MACH_DEEP_R_EK_1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DEEP_R_EK_1
-# endif
-# define machine_is_deep_r_ek_1() (machine_arch_type == MACH_TYPE_DEEP_R_EK_1)
-#else
-# define machine_is_deep_r_ek_1() (0)
-#endif
-
-#ifdef CONFIG_MACH_VIVOW_CT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VIVOW_CT
-# endif
-# define machine_is_vivow_ct() (machine_arch_type == MACH_TYPE_VIVOW_CT)
-#else
-# define machine_is_vivow_ct() (0)
-#endif
-
-#ifdef CONFIG_MACH_NERY_1000
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NERY_1000
-# endif
-# define machine_is_nery_1000() (machine_arch_type == MACH_TYPE_NERY_1000)
-#else
-# define machine_is_nery_1000() (0)
-#endif
-
-#ifdef CONFIG_MACH_RFL109145_SSRV
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RFL109145_SSRV
-# endif
-# define machine_is_rfl109145_ssrv() (machine_arch_type == MACH_TYPE_RFL109145_SSRV)
-#else
-# define machine_is_rfl109145_ssrv() (0)
-#endif
-
-#ifdef CONFIG_MACH_NMH
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NMH
-# endif
-# define machine_is_nmh() (machine_arch_type == MACH_TYPE_NMH)
-#else
-# define machine_is_nmh() (0)
-#endif
-
-#ifdef CONFIG_MACH_WN802T
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WN802T
-# endif
-# define machine_is_wn802t() (machine_arch_type == MACH_TYPE_WN802T)
-#else
-# define machine_is_wn802t() (0)
-#endif
-
-#ifdef CONFIG_MACH_DRAGONET
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DRAGONET
-# endif
-# define machine_is_dragonet() (machine_arch_type == MACH_TYPE_DRAGONET)
-#else
-# define machine_is_dragonet() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9263DESK16L
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91SAM9263DESK16L
-# endif
-# define machine_is_at91sam9263desk16l() (machine_arch_type == MACH_TYPE_AT91SAM9263DESK16L)
-#else
-# define machine_is_at91sam9263desk16l() (0)
-#endif
-
-#ifdef CONFIG_MACH_BCMHANA_SV
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BCMHANA_SV
-# endif
-# define machine_is_bcmhana_sv() (machine_arch_type == MACH_TYPE_BCMHANA_SV)
-#else
-# define machine_is_bcmhana_sv() (0)
-#endif
-
-#ifdef CONFIG_MACH_BCMHANA_TABLET
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BCMHANA_TABLET
-# endif
-# define machine_is_bcmhana_tablet() (machine_arch_type == MACH_TYPE_BCMHANA_TABLET)
-#else
-# define machine_is_bcmhana_tablet() (0)
-#endif
-
-#ifdef CONFIG_MACH_KOI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KOI
-# endif
-# define machine_is_koi() (machine_arch_type == MACH_TYPE_KOI)
-#else
-# define machine_is_koi() (0)
-#endif
-
-#ifdef CONFIG_MACH_TS4800
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TS4800
-# endif
-# define machine_is_ts4800() (machine_arch_type == MACH_TYPE_TS4800)
-#else
-# define machine_is_ts4800() (0)
-#endif
-
-#ifdef CONFIG_MACH_TQMA9263
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TQMA9263
-# endif
-# define machine_is_tqma9263() (machine_arch_type == MACH_TYPE_TQMA9263)
-#else
-# define machine_is_tqma9263() (0)
-#endif
-
-#ifdef CONFIG_MACH_HOLIDAY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HOLIDAY
-# endif
-# define machine_is_holiday() (machine_arch_type == MACH_TYPE_HOLIDAY)
-#else
-# define machine_is_holiday() (0)
-#endif
-
-#ifdef CONFIG_MACH_DMA6410
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DMA6410
-# endif
-# define machine_is_dma_6410() (machine_arch_type == MACH_TYPE_DMA6410)
-#else
-# define machine_is_dma_6410() (0)
-#endif
-
-#ifdef CONFIG_MACH_PCATS_OVERLAY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PCATS_OVERLAY
-# endif
-# define machine_is_pcats_overlay() (machine_arch_type == MACH_TYPE_PCATS_OVERLAY)
-#else
-# define machine_is_pcats_overlay() (0)
-#endif
-
-#ifdef CONFIG_MACH_HWGW6410
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HWGW6410
-# endif
-# define machine_is_hwgw6410() (machine_arch_type == MACH_TYPE_HWGW6410)
-#else
-# define machine_is_hwgw6410() (0)
-#endif
-
-#ifdef CONFIG_MACH_SHENZHOU
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SHENZHOU
-# endif
-# define machine_is_shenzhou() (machine_arch_type == MACH_TYPE_SHENZHOU)
-#else
-# define machine_is_shenzhou() (0)
-#endif
-
-#ifdef CONFIG_MACH_CWME9210
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CWME9210
-# endif
-# define machine_is_cwme9210() (machine_arch_type == MACH_TYPE_CWME9210)
-#else
-# define machine_is_cwme9210() (0)
-#endif
-
-#ifdef CONFIG_MACH_CWME9210JS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CWME9210JS
-# endif
-# define machine_is_cwme9210js() (machine_arch_type == MACH_TYPE_CWME9210JS)
-#else
-# define machine_is_cwme9210js() (0)
-#endif
-
-#ifdef CONFIG_MACH_PGS_SITARA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PGS_SITARA
-# endif
-# define machine_is_pgs_v1() (machine_arch_type == MACH_TYPE_PGS_SITARA)
-#else
-# define machine_is_pgs_v1() (0)
-#endif
-
-#ifdef CONFIG_MACH_COLIBRI_T20
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_COLIBRI_T20
-# endif
-# define machine_is_colibri_t20() (machine_arch_type == MACH_TYPE_COLIBRI_T20)
-#else
-# define machine_is_colibri_t20() (0)
-#endif
-
-#ifdef CONFIG_MACH_W21
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_W21
-# endif
-# define machine_is_w21() (machine_arch_type == MACH_TYPE_W21)
-#else
-# define machine_is_w21() (0)
-#endif
-
-#ifdef CONFIG_MACH_POLYSAT1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_POLYSAT1
-# endif
-# define machine_is_polysat1() (machine_arch_type == MACH_TYPE_POLYSAT1)
-#else
-# define machine_is_polysat1() (0)
-#endif
-
-#ifdef CONFIG_MACH_DATAWAY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DATAWAY
-# endif
-# define machine_is_dataway() (machine_arch_type == MACH_TYPE_DATAWAY)
-#else
-# define machine_is_dataway() (0)
-#endif
-
-#ifdef CONFIG_MACH_COBRAL138
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_COBRAL138
-# endif
-# define machine_is_cobral138() (machine_arch_type == MACH_TYPE_COBRAL138)
-#else
-# define machine_is_cobral138() (0)
-#endif
-
-#ifdef CONFIG_MACH_ROVERPCS8
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ROVERPCS8
-# endif
-# define machine_is_roverpcs8() (machine_arch_type == MACH_TYPE_ROVERPCS8)
-#else
-# define machine_is_roverpcs8() (0)
-#endif
-
-#ifdef CONFIG_MACH_MARVELC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MARVELC
-# endif
-# define machine_is_marvelc() (machine_arch_type == MACH_TYPE_MARVELC)
-#else
-# define machine_is_marvelc() (0)
-#endif
-
-#ifdef CONFIG_MACH_NAVEFIHID
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NAVEFIHID
-# endif
-# define machine_is_navefihid() (machine_arch_type == MACH_TYPE_NAVEFIHID)
-#else
-# define machine_is_navefihid() (0)
-#endif
-
-#ifdef CONFIG_MACH_DM365_CV100
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DM365_CV100
-# endif
-# define machine_is_dm365_cv100() (machine_arch_type == MACH_TYPE_DM365_CV100)
-#else
-# define machine_is_dm365_cv100() (0)
-#endif
-
-#ifdef CONFIG_MACH_ABLE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ABLE
-# endif
-# define machine_is_able() (machine_arch_type == MACH_TYPE_ABLE)
-#else
-# define machine_is_able() (0)
-#endif
-
-#ifdef CONFIG_MACH_LEGACY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LEGACY
-# endif
-# define machine_is_legacy() (machine_arch_type == MACH_TYPE_LEGACY)
-#else
-# define machine_is_legacy() (0)
-#endif
-
-#ifdef CONFIG_MACH_ICONG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ICONG
-# endif
-# define machine_is_icong() (machine_arch_type == MACH_TYPE_ICONG)
-#else
-# define machine_is_icong() (0)
-#endif
-
-#ifdef CONFIG_MACH_ROVER_G8
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ROVER_G8
-# endif
-# define machine_is_rover_g8() (machine_arch_type == MACH_TYPE_ROVER_G8)
-#else
-# define machine_is_rover_g8() (0)
-#endif
-
-#ifdef CONFIG_MACH_T5388P
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_T5388P
-# endif
-# define machine_is_t5388p() (machine_arch_type == MACH_TYPE_T5388P)
-#else
-# define machine_is_t5388p() (0)
-#endif
-
-#ifdef CONFIG_MACH_DINGO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DINGO
-# endif
-# define machine_is_dingo() (machine_arch_type == MACH_TYPE_DINGO)
-#else
-# define machine_is_dingo() (0)
-#endif
-
-#ifdef CONFIG_MACH_GOFLEXHOME
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GOFLEXHOME
-# endif
-# define machine_is_goflexhome() (machine_arch_type == MACH_TYPE_GOFLEXHOME)
-#else
-# define machine_is_goflexhome() (0)
-#endif
-
-#ifdef CONFIG_MACH_LANREADYFN511
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LANREADYFN511
-# endif
-# define machine_is_lanreadyfn511() (machine_arch_type == MACH_TYPE_LANREADYFN511)
-#else
-# define machine_is_lanreadyfn511() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3_BAIA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3_BAIA
-# endif
-# define machine_is_omap3_baia() (machine_arch_type == MACH_TYPE_OMAP3_BAIA)
-#else
-# define machine_is_omap3_baia() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP3SMARTDISPLAY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP3SMARTDISPLAY
-# endif
-# define machine_is_omap3smartdisplay() (machine_arch_type == MACH_TYPE_OMAP3SMARTDISPLAY)
-#else
-# define machine_is_omap3smartdisplay() (0)
-#endif
-
-#ifdef CONFIG_MACH_XILINX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_XILINX
-# endif
-# define machine_is_xilinx() (machine_arch_type == MACH_TYPE_XILINX)
-#else
-# define machine_is_xilinx() (0)
-#endif
-
-#ifdef CONFIG_MACH_A2F
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_A2F
-# endif
-# define machine_is_a2f() (machine_arch_type == MACH_TYPE_A2F)
-#else
-# define machine_is_a2f() (0)
-#endif
-
-#ifdef CONFIG_MACH_SKY25
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SKY25
-# endif
-# define machine_is_sky25() (machine_arch_type == MACH_TYPE_SKY25)
-#else
-# define machine_is_sky25() (0)
-#endif
-
-#ifdef CONFIG_MACH_CCMX53
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CCMX53
-# endif
-# define machine_is_ccmx53() (machine_arch_type == MACH_TYPE_CCMX53)
-#else
-# define machine_is_ccmx53() (0)
-#endif
-
-#ifdef CONFIG_MACH_CCMX53JS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CCMX53JS
-# endif
-# define machine_is_ccmx53js() (machine_arch_type == MACH_TYPE_CCMX53JS)
-#else
-# define machine_is_ccmx53js() (0)
-#endif
-
-#ifdef CONFIG_MACH_CCWMX53
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CCWMX53
-# endif
-# define machine_is_ccwmx53() (machine_arch_type == MACH_TYPE_CCWMX53)
-#else
-# define machine_is_ccwmx53() (0)
-#endif
-
-#ifdef CONFIG_MACH_CCWMX53JS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CCWMX53JS
-# endif
-# define machine_is_ccwmx53js() (machine_arch_type == MACH_TYPE_CCWMX53JS)
-#else
-# define machine_is_ccwmx53js() (0)
-#endif
-
-#ifdef CONFIG_MACH_FRISMS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_FRISMS
-# endif
-# define machine_is_frisms() (machine_arch_type == MACH_TYPE_FRISMS)
-#else
-# define machine_is_frisms() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X27A_FFA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM7X27A_FFA
-# endif
-# define machine_is_msm7x27a_ffa() (machine_arch_type == MACH_TYPE_MSM7X27A_FFA)
-#else
-# define machine_is_msm7x27a_ffa() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X27A_SURF
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM7X27A_SURF
-# endif
-# define machine_is_msm7x27a_surf() (machine_arch_type == MACH_TYPE_MSM7X27A_SURF)
-#else
-# define machine_is_msm7x27a_surf() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM7X27A_RUMI3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM7X27A_RUMI3
-# endif
-# define machine_is_msm7x27a_rumi3() (machine_arch_type == MACH_TYPE_MSM7X27A_RUMI3)
-#else
-# define machine_is_msm7x27a_rumi3() (0)
-#endif
-
-#ifdef CONFIG_MACH_DIMMSAM9G20
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DIMMSAM9G20
-# endif
-# define machine_is_dimmsam9g20() (machine_arch_type == MACH_TYPE_DIMMSAM9G20)
-#else
-# define machine_is_dimmsam9g20() (0)
-#endif
-
-#ifdef CONFIG_MACH_DIMM_IMX28
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DIMM_IMX28
-# endif
-# define machine_is_dimm_imx28() (machine_arch_type == MACH_TYPE_DIMM_IMX28)
-#else
-# define machine_is_dimm_imx28() (0)
-#endif
-
-#ifdef CONFIG_MACH_AMK_A4
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AMK_A4
-# endif
-# define machine_is_amk_a4() (machine_arch_type == MACH_TYPE_AMK_A4)
-#else
-# define machine_is_amk_a4() (0)
-#endif
-
-#ifdef CONFIG_MACH_GNET_SGME
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GNET_SGME
-# endif
-# define machine_is_gnet_sgme() (machine_arch_type == MACH_TYPE_GNET_SGME)
-#else
-# define machine_is_gnet_sgme() (0)
-#endif
-
-#ifdef CONFIG_MACH_SHOOTER_U
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SHOOTER_U
-# endif
-# define machine_is_shooter_u() (machine_arch_type == MACH_TYPE_SHOOTER_U)
-#else
-# define machine_is_shooter_u() (0)
-#endif
-
-#ifdef CONFIG_MACH_VMX53
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VMX53
-# endif
-# define machine_is_vmx53() (machine_arch_type == MACH_TYPE_VMX53)
-#else
-# define machine_is_vmx53() (0)
-#endif
-
-#ifdef CONFIG_MACH_RHINO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RHINO
-# endif
-# define machine_is_rhino() (machine_arch_type == MACH_TYPE_RHINO)
-#else
-# define machine_is_rhino() (0)
-#endif
-
-#ifdef CONFIG_MACH_ARMLEX4210
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ARMLEX4210
-# endif
-# define machine_is_armlex4210() (machine_arch_type == MACH_TYPE_ARMLEX4210)
-#else
-# define machine_is_armlex4210() (0)
-#endif
-
-#ifdef CONFIG_MACH_SWARCOEXTMODEM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SWARCOEXTMODEM
-# endif
-# define machine_is_swarcoextmodem() (machine_arch_type == MACH_TYPE_SWARCOEXTMODEM)
-#else
-# define machine_is_swarcoextmodem() (0)
-#endif
-
-#ifdef CONFIG_MACH_PCM049
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PCM049
-# endif
-# define machine_is_pcm049() (machine_arch_type == MACH_TYPE_PCM049)
-#else
-# define machine_is_pcm049() (0)
-#endif
-
-#ifdef CONFIG_MACH_VIGOR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VIGOR
-# endif
-# define machine_is_vigor() (machine_arch_type == MACH_TYPE_VIGOR)
-#else
-# define machine_is_vigor() (0)
-#endif
-
-#ifdef CONFIG_MACH_OSLO_AMUNDSEN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OSLO_AMUNDSEN
-# endif
-# define machine_is_oslo_amundsen() (machine_arch_type == MACH_TYPE_OSLO_AMUNDSEN)
-#else
-# define machine_is_oslo_amundsen() (0)
-#endif
-
-#ifdef CONFIG_MACH_GSL_DIAMOND
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GSL_DIAMOND
-# endif
-# define machine_is_gsl_diamond() (machine_arch_type == MACH_TYPE_GSL_DIAMOND)
-#else
-# define machine_is_gsl_diamond() (0)
-#endif
-
-#ifdef CONFIG_MACH_CV2201
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CV2201
-# endif
-# define machine_is_cv2201() (machine_arch_type == MACH_TYPE_CV2201)
-#else
-# define machine_is_cv2201() (0)
-#endif
-
-#ifdef CONFIG_MACH_CV2202
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CV2202
-# endif
-# define machine_is_cv2202() (machine_arch_type == MACH_TYPE_CV2202)
-#else
-# define machine_is_cv2202() (0)
-#endif
-
-#ifdef CONFIG_MACH_CV2203
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CV2203
-# endif
-# define machine_is_cv2203() (machine_arch_type == MACH_TYPE_CV2203)
-#else
-# define machine_is_cv2203() (0)
-#endif
-
-#ifdef CONFIG_MACH_VIT_IBOX
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VIT_IBOX
-# endif
-# define machine_is_vit_ibox() (machine_arch_type == MACH_TYPE_VIT_IBOX)
-#else
-# define machine_is_vit_ibox() (0)
-#endif
-
-#ifdef CONFIG_MACH_DM6441_ESP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DM6441_ESP
-# endif
-# define machine_is_dm6441_esp() (machine_arch_type == MACH_TYPE_DM6441_ESP)
-#else
-# define machine_is_dm6441_esp() (0)
-#endif
-
-#ifdef CONFIG_MACH_AT91SAM9X5EK
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AT91SAM9X5EK
-# endif
-# define machine_is_at91sam9x5ek() (machine_arch_type == MACH_TYPE_AT91SAM9X5EK)
-#else
-# define machine_is_at91sam9x5ek() (0)
-#endif
-
-#ifdef CONFIG_MACH_LIBRA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_LIBRA
-# endif
-# define machine_is_libra() (machine_arch_type == MACH_TYPE_LIBRA)
-#else
-# define machine_is_libra() (0)
-#endif
-
-#ifdef CONFIG_MACH_EASYCRRH
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EASYCRRH
-# endif
-# define machine_is_easycrrh() (machine_arch_type == MACH_TYPE_EASYCRRH)
-#else
-# define machine_is_easycrrh() (0)
-#endif
-
-#ifdef CONFIG_MACH_TRIPEL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TRIPEL
-# endif
-# define machine_is_tripel() (machine_arch_type == MACH_TYPE_TRIPEL)
-#else
-# define machine_is_tripel() (0)
-#endif
-
-#ifdef CONFIG_MACH_ENDIAN_MINI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ENDIAN_MINI
-# endif
-# define machine_is_endian_mini() (machine_arch_type == MACH_TYPE_ENDIAN_MINI)
-#else
-# define machine_is_endian_mini() (0)
-#endif
-
-#ifdef CONFIG_MACH_XILINX_EP107
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_XILINX_EP107
-# endif
-# define machine_is_xilinx_ep107() (machine_arch_type == MACH_TYPE_XILINX_EP107)
-#else
-# define machine_is_xilinx_ep107() (0)
-#endif
-
-#ifdef CONFIG_MACH_NURI
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NURI
-# endif
-# define machine_is_nuri() (machine_arch_type == MACH_TYPE_NURI)
-#else
-# define machine_is_nuri() (0)
-#endif
-
-#ifdef CONFIG_MACH_JANUS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_JANUS
-# endif
-# define machine_is_janus() (machine_arch_type == MACH_TYPE_JANUS)
-#else
-# define machine_is_janus() (0)
-#endif
-
-#ifdef CONFIG_MACH_DDNAS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DDNAS
-# endif
-# define machine_is_ddnas() (machine_arch_type == MACH_TYPE_DDNAS)
-#else
-# define machine_is_ddnas() (0)
-#endif
-
-#ifdef CONFIG_MACH_TAG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TAG
-# endif
-# define machine_is_tag() (machine_arch_type == MACH_TYPE_TAG)
-#else
-# define machine_is_tag() (0)
-#endif
-
-#ifdef CONFIG_MACH_TAGW
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TAGW
-# endif
-# define machine_is_tagw() (machine_arch_type == MACH_TYPE_TAGW)
-#else
-# define machine_is_tagw() (0)
-#endif
-
-#ifdef CONFIG_MACH_NITROGEN_VM_IMX51
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NITROGEN_VM_IMX51
-# endif
-# define machine_is_nitrogen_vm_imx51() (machine_arch_type == MACH_TYPE_NITROGEN_VM_IMX51)
-#else
-# define machine_is_nitrogen_vm_imx51() (0)
-#endif
-
-#ifdef CONFIG_MACH_VIPRINET
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VIPRINET
-# endif
-# define machine_is_viprinet() (machine_arch_type == MACH_TYPE_VIPRINET)
-#else
-# define machine_is_viprinet() (0)
-#endif
-
-#ifdef CONFIG_MACH_BOCKW
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BOCKW
-# endif
-# define machine_is_bockw() (machine_arch_type == MACH_TYPE_BOCKW)
-#else
-# define machine_is_bockw() (0)
-#endif
-
-#ifdef CONFIG_MACH_EVA2000
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EVA2000
-# endif
-# define machine_is_eva2000() (machine_arch_type == MACH_TYPE_EVA2000)
-#else
-# define machine_is_eva2000() (0)
-#endif
-
-#ifdef CONFIG_MACH_STEELYARD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_STEELYARD
-# endif
-# define machine_is_steelyard() (machine_arch_type == MACH_TYPE_STEELYARD)
-#else
-# define machine_is_steelyard() (0)
-#endif
-
-#ifdef CONFIG_MACH_MACH_SDH001
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MACH_SDH001
-# endif
-# define machine_is_sdh001() (machine_arch_type == MACH_TYPE_MACH_SDH001)
-#else
-# define machine_is_sdh001() (0)
-#endif
-
-#ifdef CONFIG_MACH_NSSLSBOARD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NSSLSBOARD
-# endif
-# define machine_is_nsslsboard() (machine_arch_type == MACH_TYPE_NSSLSBOARD)
-#else
-# define machine_is_nsslsboard() (0)
-#endif
-
-#ifdef CONFIG_MACH_GENEVA_B5
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GENEVA_B5
-# endif
-# define machine_is_geneva_b5() (machine_arch_type == MACH_TYPE_GENEVA_B5)
-#else
-# define machine_is_geneva_b5() (0)
-#endif
-
-#ifdef CONFIG_MACH_SPEAR1340
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SPEAR1340
-# endif
-# define machine_is_spear1340() (machine_arch_type == MACH_TYPE_SPEAR1340)
-#else
-# define machine_is_spear1340() (0)
-#endif
-
-#ifdef CONFIG_MACH_REXMAS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_REXMAS
-# endif
-# define machine_is_rexmas() (machine_arch_type == MACH_TYPE_REXMAS)
-#else
-# define machine_is_rexmas() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8960_CDP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8960_CDP
-# endif
-# define machine_is_msm8960_cdp() (machine_arch_type == MACH_TYPE_MSM8960_CDP)
-#else
-# define machine_is_msm8960_cdp() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8960_MDP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8960_MDP
-# endif
-# define machine_is_msm8960_mdp() (machine_arch_type == MACH_TYPE_MSM8960_MDP)
-#else
-# define machine_is_msm8960_mdp() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8960_FLUID
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8960_FLUID
-# endif
-# define machine_is_msm8960_fluid() (machine_arch_type == MACH_TYPE_MSM8960_FLUID)
-#else
-# define machine_is_msm8960_fluid() (0)
-#endif
-
-#ifdef CONFIG_MACH_MSM8960_APQ
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MSM8960_APQ
-# endif
-# define machine_is_msm8960_apq() (machine_arch_type == MACH_TYPE_MSM8960_APQ)
-#else
-# define machine_is_msm8960_apq() (0)
-#endif
-
-#ifdef CONFIG_MACH_HELIOS_V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HELIOS_V2
-# endif
-# define machine_is_helios_v2() (machine_arch_type == MACH_TYPE_HELIOS_V2)
-#else
-# define machine_is_helios_v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_MIF10P
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MIF10P
-# endif
-# define machine_is_mif10p() (machine_arch_type == MACH_TYPE_MIF10P)
-#else
-# define machine_is_mif10p() (0)
-#endif
-
-#ifdef CONFIG_MACH_IAM28
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_IAM28
-# endif
-# define machine_is_iam28() (machine_arch_type == MACH_TYPE_IAM28)
-#else
-# define machine_is_iam28() (0)
-#endif
-
-#ifdef CONFIG_MACH_PICASSO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PICASSO
-# endif
-# define machine_is_picasso() (machine_arch_type == MACH_TYPE_PICASSO)
-#else
-# define machine_is_picasso() (0)
-#endif
-
-#ifdef CONFIG_MACH_MR301A
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MR301A
-# endif
-# define machine_is_mr301a() (machine_arch_type == MACH_TYPE_MR301A)
-#else
-# define machine_is_mr301a() (0)
-#endif
-
-#ifdef CONFIG_MACH_NOTLE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NOTLE
-# endif
-# define machine_is_notle() (machine_arch_type == MACH_TYPE_NOTLE)
-#else
-# define machine_is_notle() (0)
-#endif
-
-#ifdef CONFIG_MACH_EELX2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EELX2
-# endif
-# define machine_is_eelx2() (machine_arch_type == MACH_TYPE_EELX2)
-#else
-# define machine_is_eelx2() (0)
-#endif
-
-#ifdef CONFIG_MACH_MOON
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MOON
-# endif
-# define machine_is_moon() (machine_arch_type == MACH_TYPE_MOON)
-#else
-# define machine_is_moon() (0)
-#endif
-
-#ifdef CONFIG_MACH_RUBY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_RUBY
-# endif
-# define machine_is_ruby() (machine_arch_type == MACH_TYPE_RUBY)
-#else
-# define machine_is_ruby() (0)
-#endif
-
-#ifdef CONFIG_MACH_GOLDENGATE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GOLDENGATE
-# endif
-# define machine_is_goldengate() (machine_arch_type == MACH_TYPE_GOLDENGATE)
-#else
-# define machine_is_goldengate() (0)
-#endif
-
-#ifdef CONFIG_MACH_CTBU_GEN2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CTBU_GEN2
-# endif
-# define machine_is_ctbu_gen2() (machine_arch_type == MACH_TYPE_CTBU_GEN2)
-#else
-# define machine_is_ctbu_gen2() (0)
-#endif
-
-#ifdef CONFIG_MACH_KMP_AM17_01
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KMP_AM17_01
-# endif
-# define machine_is_kmp_am17_01() (machine_arch_type == MACH_TYPE_KMP_AM17_01)
-#else
-# define machine_is_kmp_am17_01() (0)
-#endif
-
-#ifdef CONFIG_MACH_WTPLUG
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WTPLUG
-# endif
-# define machine_is_wtplug() (machine_arch_type == MACH_TYPE_WTPLUG)
-#else
-# define machine_is_wtplug() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX27SU2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX27SU2
-# endif
-# define machine_is_mx27su2() (machine_arch_type == MACH_TYPE_MX27SU2)
-#else
-# define machine_is_mx27su2() (0)
-#endif
-
-#ifdef CONFIG_MACH_NB31
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NB31
-# endif
-# define machine_is_nb31() (machine_arch_type == MACH_TYPE_NB31)
-#else
-# define machine_is_nb31() (0)
-#endif
-
-#ifdef CONFIG_MACH_HJSDU
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HJSDU
-# endif
-# define machine_is_hjsdu() (machine_arch_type == MACH_TYPE_HJSDU)
-#else
-# define machine_is_hjsdu() (0)
-#endif
-
-#ifdef CONFIG_MACH_TD3_REV1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TD3_REV1
-# endif
-# define machine_is_td3_rev1() (machine_arch_type == MACH_TYPE_TD3_REV1)
-#else
-# define machine_is_td3_rev1() (0)
-#endif
-
-#ifdef CONFIG_MACH_EAG_CI4000
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EAG_CI4000
-# endif
-# define machine_is_eag_ci4000() (machine_arch_type == MACH_TYPE_EAG_CI4000)
-#else
-# define machine_is_eag_ci4000() (0)
-#endif
-
-#ifdef CONFIG_MACH_NET5BIG_NAND_V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NET5BIG_NAND_V2
-# endif
-# define machine_is_net5big_nand_v2() (machine_arch_type == MACH_TYPE_NET5BIG_NAND_V2)
-#else
-# define machine_is_net5big_nand_v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_CPX2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CPX2
-# endif
-# define machine_is_cpx2() (machine_arch_type == MACH_TYPE_CPX2)
-#else
-# define machine_is_cpx2() (0)
-#endif
-
-#ifdef CONFIG_MACH_NET2BIG_NAND_V2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NET2BIG_NAND_V2
-# endif
-# define machine_is_net2big_nand_v2() (machine_arch_type == MACH_TYPE_NET2BIG_NAND_V2)
-#else
-# define machine_is_net2big_nand_v2() (0)
-#endif
-
-#ifdef CONFIG_MACH_ECUV5
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ECUV5
-# endif
-# define machine_is_ecuv5() (machine_arch_type == MACH_TYPE_ECUV5)
-#else
-# define machine_is_ecuv5() (0)
-#endif
-
-#ifdef CONFIG_MACH_HSGX6D
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_HSGX6D
-# endif
-# define machine_is_hsgx6d() (machine_arch_type == MACH_TYPE_HSGX6D)
-#else
-# define machine_is_hsgx6d() (0)
-#endif
-
-#ifdef CONFIG_MACH_DAWAD7
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DAWAD7
-# endif
-# define machine_is_dawad7() (machine_arch_type == MACH_TYPE_DAWAD7)
-#else
-# define machine_is_dawad7() (0)
-#endif
-
-#ifdef CONFIG_MACH_SAM9REPEATER
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SAM9REPEATER
-# endif
-# define machine_is_sam9repeater() (machine_arch_type == MACH_TYPE_SAM9REPEATER)
-#else
-# define machine_is_sam9repeater() (0)
-#endif
-
-#ifdef CONFIG_MACH_GT_I5700
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_GT_I5700
-# endif
-# define machine_is_gt_i5700() (machine_arch_type == MACH_TYPE_GT_I5700)
-#else
-# define machine_is_gt_i5700() (0)
-#endif
-
-#ifdef CONFIG_MACH_CTERA_PLUG_C2
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CTERA_PLUG_C2
-# endif
-# define machine_is_ctera_plug_c2() (machine_arch_type == MACH_TYPE_CTERA_PLUG_C2)
-#else
-# define machine_is_ctera_plug_c2() (0)
-#endif
-
-#ifdef CONFIG_MACH_MARVELCT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MARVELCT
-# endif
-# define machine_is_marvelct() (machine_arch_type == MACH_TYPE_MARVELCT)
-#else
-# define machine_is_marvelct() (0)
-#endif
-
-#ifdef CONFIG_MACH_AG11005
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_AG11005
-# endif
-# define machine_is_ag11005() (machine_arch_type == MACH_TYPE_AG11005)
-#else
-# define machine_is_ag11005() (0)
-#endif
-
-#ifdef CONFIG_MACH_VANGOGH
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VANGOGH
-# endif
-# define machine_is_vangogh() (machine_arch_type == MACH_TYPE_VANGOGH)
-#else
-# define machine_is_vangogh() (0)
-#endif
-
-#ifdef CONFIG_MACH_MATRIX505
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MATRIX505
-# endif
-# define machine_is_matrix505() (machine_arch_type == MACH_TYPE_MATRIX505)
-#else
-# define machine_is_matrix505() (0)
-#endif
-
-#ifdef CONFIG_MACH_OCE_NIGMA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OCE_NIGMA
-# endif
-# define machine_is_oce_nigma() (machine_arch_type == MACH_TYPE_OCE_NIGMA)
-#else
-# define machine_is_oce_nigma() (0)
-#endif
-
-#ifdef CONFIG_MACH_T55
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_T55
-# endif
-# define machine_is_t55() (machine_arch_type == MACH_TYPE_T55)
-#else
-# define machine_is_t55() (0)
-#endif
-
-#ifdef CONFIG_MACH_BIO3K
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BIO3K
-# endif
-# define machine_is_bio3k() (machine_arch_type == MACH_TYPE_BIO3K)
-#else
-# define machine_is_bio3k() (0)
-#endif
-
-#ifdef CONFIG_MACH_EXPRESSCT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EXPRESSCT
-# endif
-# define machine_is_expressct() (machine_arch_type == MACH_TYPE_EXPRESSCT)
-#else
-# define machine_is_expressct() (0)
-#endif
-
-#ifdef CONFIG_MACH_CARDHU
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CARDHU
-# endif
-# define machine_is_cardhu() (machine_arch_type == MACH_TYPE_CARDHU)
-#else
-# define machine_is_cardhu() (0)
-#endif
-
-#ifdef CONFIG_MACH_ARUBA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ARUBA
-# endif
-# define machine_is_aruba() (machine_arch_type == MACH_TYPE_ARUBA)
-#else
-# define machine_is_aruba() (0)
-#endif
-
-#ifdef CONFIG_MACH_BONAIRE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BONAIRE
-# endif
-# define machine_is_bonaire() (machine_arch_type == MACH_TYPE_BONAIRE)
-#else
-# define machine_is_bonaire() (0)
-#endif
-
-#ifdef CONFIG_MACH_NUC700EVB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NUC700EVB
-# endif
-# define machine_is_nuc700evb() (machine_arch_type == MACH_TYPE_NUC700EVB)
-#else
-# define machine_is_nuc700evb() (0)
-#endif
-
-#ifdef CONFIG_MACH_NUC710EVB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NUC710EVB
-# endif
-# define machine_is_nuc710evb() (machine_arch_type == MACH_TYPE_NUC710EVB)
-#else
-# define machine_is_nuc710evb() (0)
-#endif
-
-#ifdef CONFIG_MACH_NUC740EVB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NUC740EVB
-# endif
-# define machine_is_nuc740evb() (machine_arch_type == MACH_TYPE_NUC740EVB)
-#else
-# define machine_is_nuc740evb() (0)
-#endif
-
-#ifdef CONFIG_MACH_NUC745EVB
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NUC745EVB
-# endif
-# define machine_is_nuc745evb() (machine_arch_type == MACH_TYPE_NUC745EVB)
-#else
-# define machine_is_nuc745evb() (0)
-#endif
-
-#ifdef CONFIG_MACH_TRANSCEDE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TRANSCEDE
-# endif
-# define machine_is_transcede() (machine_arch_type == MACH_TYPE_TRANSCEDE)
-#else
-# define machine_is_transcede() (0)
-#endif
-
-#ifdef CONFIG_MACH_MORA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MORA
-# endif
-# define machine_is_mora() (machine_arch_type == MACH_TYPE_MORA)
-#else
-# define machine_is_mora() (0)
-#endif
-
-#ifdef CONFIG_MACH_NDA_EVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_NDA_EVM
-# endif
-# define machine_is_nda_evm() (machine_arch_type == MACH_TYPE_NDA_EVM)
-#else
-# define machine_is_nda_evm() (0)
-#endif
-
-#ifdef CONFIG_MACH_TIMU
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TIMU
-# endif
-# define machine_is_timu() (machine_arch_type == MACH_TYPE_TIMU)
-#else
-# define machine_is_timu() (0)
-#endif
-
-#ifdef CONFIG_MACH_EXPRESSH
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EXPRESSH
-# endif
-# define machine_is_expressh() (machine_arch_type == MACH_TYPE_EXPRESSH)
-#else
-# define machine_is_expressh() (0)
-#endif
-
-#ifdef CONFIG_MACH_VERIDIS_A300
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_VERIDIS_A300
-# endif
-# define machine_is_veridis_a300() (machine_arch_type == MACH_TYPE_VERIDIS_A300)
-#else
-# define machine_is_veridis_a300() (0)
-#endif
-
-#ifdef CONFIG_MACH_DM368_LEOPARD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DM368_LEOPARD
-# endif
-# define machine_is_dm368_leopard() (machine_arch_type == MACH_TYPE_DM368_LEOPARD)
-#else
-# define machine_is_dm368_leopard() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP_MCOP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP_MCOP
-# endif
-# define machine_is_omap_mcop() (machine_arch_type == MACH_TYPE_OMAP_MCOP)
-#else
-# define machine_is_omap_mcop() (0)
-#endif
-
-#ifdef CONFIG_MACH_TRITIP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TRITIP
-# endif
-# define machine_is_tritip() (machine_arch_type == MACH_TYPE_TRITIP)
-#else
-# define machine_is_tritip() (0)
-#endif
-
-#ifdef CONFIG_MACH_SM1K
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SM1K
-# endif
-# define machine_is_sm1k() (machine_arch_type == MACH_TYPE_SM1K)
-#else
-# define machine_is_sm1k() (0)
-#endif
-
-#ifdef CONFIG_MACH_MONCH
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MONCH
-# endif
-# define machine_is_monch() (machine_arch_type == MACH_TYPE_MONCH)
-#else
-# define machine_is_monch() (0)
-#endif
-
-#ifdef CONFIG_MACH_CURACAO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CURACAO
-# endif
-# define machine_is_curacao() (machine_arch_type == MACH_TYPE_CURACAO)
-#else
-# define machine_is_curacao() (0)
-#endif
-
-#ifdef CONFIG_MACH_ORIGEN
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ORIGEN
-# endif
-# define machine_is_origen() (machine_arch_type == MACH_TYPE_ORIGEN)
-#else
-# define machine_is_origen() (0)
-#endif
-
-#ifdef CONFIG_MACH_EPC10
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EPC10
-# endif
-# define machine_is_epc10() (machine_arch_type == MACH_TYPE_EPC10)
-#else
-# define machine_is_epc10() (0)
-#endif
-
-#ifdef CONFIG_MACH_SGH_I740
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SGH_I740
-# endif
-# define machine_is_sgh_i740() (machine_arch_type == MACH_TYPE_SGH_I740)
-#else
-# define machine_is_sgh_i740() (0)
-#endif
-
-#ifdef CONFIG_MACH_TUNA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TUNA
-# endif
-# define machine_is_tuna() (machine_arch_type == MACH_TYPE_TUNA)
-#else
-# define machine_is_tuna() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_TULIP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX51_TULIP
-# endif
-# define machine_is_mx51_tulip() (machine_arch_type == MACH_TYPE_MX51_TULIP)
-#else
-# define machine_is_mx51_tulip() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_ASTER7
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX51_ASTER7
-# endif
-# define machine_is_mx51_aster7() (machine_arch_type == MACH_TYPE_MX51_ASTER7)
-#else
-# define machine_is_mx51_aster7() (0)
-#endif
-
-#ifdef CONFIG_MACH_ACRO37XBRD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ACRO37XBRD
-# endif
-# define machine_is_acro37xbrd() (machine_arch_type == MACH_TYPE_ACRO37XBRD)
-#else
-# define machine_is_acro37xbrd() (0)
-#endif
-
-#ifdef CONFIG_MACH_ELKE
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ELKE
-# endif
-# define machine_is_elke() (machine_arch_type == MACH_TYPE_ELKE)
-#else
-# define machine_is_elke() (0)
-#endif
-
-#ifdef CONFIG_MACH_SBC6000X
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SBC6000X
-# endif
-# define machine_is_sbc6000x() (machine_arch_type == MACH_TYPE_SBC6000X)
-#else
-# define machine_is_sbc6000x() (0)
-#endif
-
-#ifdef CONFIG_MACH_R1801E
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_R1801E
-# endif
-# define machine_is_r1801e() (machine_arch_type == MACH_TYPE_R1801E)
-#else
-# define machine_is_r1801e() (0)
-#endif
-
-#ifdef CONFIG_MACH_H1600
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_H1600
-# endif
-# define machine_is_h1600() (machine_arch_type == MACH_TYPE_H1600)
-#else
-# define machine_is_h1600() (0)
-#endif
-
-#ifdef CONFIG_MACH_MINI210
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MINI210
-# endif
-# define machine_is_mini210() (machine_arch_type == MACH_TYPE_MINI210)
-#else
-# define machine_is_mini210() (0)
-#endif
-
-#ifdef CONFIG_MACH_MINI8168
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MINI8168
-# endif
-# define machine_is_mini8168() (machine_arch_type == MACH_TYPE_MINI8168)
-#else
-# define machine_is_mini8168() (0)
-#endif
-
-#ifdef CONFIG_MACH_PC7308
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PC7308
-# endif
-# define machine_is_pc7308() (machine_arch_type == MACH_TYPE_PC7308)
-#else
-# define machine_is_pc7308() (0)
-#endif
-
-#ifdef CONFIG_MACH_KMM2M01
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KMM2M01
-# endif
-# define machine_is_kmm2m01() (machine_arch_type == MACH_TYPE_KMM2M01)
-#else
-# define machine_is_kmm2m01() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX51EREBUS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX51EREBUS
-# endif
-# define machine_is_mx51erebus() (machine_arch_type == MACH_TYPE_MX51EREBUS)
-#else
-# define machine_is_mx51erebus() (0)
-#endif
-
-#ifdef CONFIG_MACH_WM8650REFBOARD
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_WM8650REFBOARD
-# endif
-# define machine_is_wm8650refboard() (machine_arch_type == MACH_TYPE_WM8650REFBOARD)
-#else
-# define machine_is_wm8650refboard() (0)
-#endif
-
-#ifdef CONFIG_MACH_TUXRAIL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_TUXRAIL
-# endif
-# define machine_is_tuxrail() (machine_arch_type == MACH_TYPE_TUXRAIL)
-#else
-# define machine_is_tuxrail() (0)
-#endif
-
-#ifdef CONFIG_MACH_ARTHUR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ARTHUR
-# endif
-# define machine_is_arthur() (machine_arch_type == MACH_TYPE_ARTHUR)
-#else
-# define machine_is_arthur() (0)
-#endif
-
-#ifdef CONFIG_MACH_DOORBOY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DOORBOY
-# endif
-# define machine_is_doorboy() (machine_arch_type == MACH_TYPE_DOORBOY)
-#else
-# define machine_is_doorboy() (0)
-#endif
-
-#ifdef CONFIG_MACH_XARINA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_XARINA
-# endif
-# define machine_is_xarina() (machine_arch_type == MACH_TYPE_XARINA)
-#else
-# define machine_is_xarina() (0)
-#endif
-
-#ifdef CONFIG_MACH_ROVERX7
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ROVERX7
-# endif
-# define machine_is_roverx7() (machine_arch_type == MACH_TYPE_ROVERX7)
-#else
-# define machine_is_roverx7() (0)
-#endif
-
-#ifdef CONFIG_MACH_SDVR
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SDVR
-# endif
-# define machine_is_sdvr() (machine_arch_type == MACH_TYPE_SDVR)
-#else
-# define machine_is_sdvr() (0)
-#endif
-
-#ifdef CONFIG_MACH_ACER_MAYA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ACER_MAYA
-# endif
-# define machine_is_acer_maya() (machine_arch_type == MACH_TYPE_ACER_MAYA)
-#else
-# define machine_is_acer_maya() (0)
-#endif
-
-#ifdef CONFIG_MACH_PICO
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_PICO
-# endif
-# define machine_is_pico() (machine_arch_type == MACH_TYPE_PICO)
-#else
-# define machine_is_pico() (0)
-#endif
-
-#ifdef CONFIG_MACH_CWMX233
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CWMX233
-# endif
-# define machine_is_cwmx233() (machine_arch_type == MACH_TYPE_CWMX233)
-#else
-# define machine_is_cwmx233() (0)
-#endif
-
-#ifdef CONFIG_MACH_CWAM1808
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CWAM1808
-# endif
-# define machine_is_cwam1808() (machine_arch_type == MACH_TYPE_CWAM1808)
-#else
-# define machine_is_cwam1808() (0)
-#endif
-
-#ifdef CONFIG_MACH_CWDM365
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CWDM365
-# endif
-# define machine_is_cwdm365() (machine_arch_type == MACH_TYPE_CWDM365)
-#else
-# define machine_is_cwdm365() (0)
-#endif
-
-#ifdef CONFIG_MACH_MX51_MORAY
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_MX51_MORAY
-# endif
-# define machine_is_mx51_moray() (machine_arch_type == MACH_TYPE_MX51_MORAY)
-#else
-# define machine_is_mx51_moray() (0)
-#endif
-
-#ifdef CONFIG_MACH_THALES_CBC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_THALES_CBC
-# endif
-# define machine_is_thales_cbc() (machine_arch_type == MACH_TYPE_THALES_CBC)
-#else
-# define machine_is_thales_cbc() (0)
-#endif
-
-#ifdef CONFIG_MACH_BLUEPOINT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BLUEPOINT
-# endif
-# define machine_is_bluepoint() (machine_arch_type == MACH_TYPE_BLUEPOINT)
-#else
-# define machine_is_bluepoint() (0)
-#endif
-
-#ifdef CONFIG_MACH_DIR665
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_DIR665
-# endif
-# define machine_is_dir665() (machine_arch_type == MACH_TYPE_DIR665)
-#else
-# define machine_is_dir665() (0)
-#endif
-
-#ifdef CONFIG_MACH_ACMEROVER1
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ACMEROVER1
-# endif
-# define machine_is_acmerover1() (machine_arch_type == MACH_TYPE_ACMEROVER1)
-#else
-# define machine_is_acmerover1() (0)
-#endif
-
-#ifdef CONFIG_MACH_SHOOTER_CT
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SHOOTER_CT
-# endif
-# define machine_is_shooter_ct() (machine_arch_type == MACH_TYPE_SHOOTER_CT)
-#else
-# define machine_is_shooter_ct() (0)
-#endif
-
-#ifdef CONFIG_MACH_BLISS
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BLISS
-# endif
-# define machine_is_bliss() (machine_arch_type == MACH_TYPE_BLISS)
-#else
-# define machine_is_bliss() (0)
-#endif
-
-#ifdef CONFIG_MACH_BLISSC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BLISSC
-# endif
-# define machine_is_blissc() (machine_arch_type == MACH_TYPE_BLISSC)
-#else
-# define machine_is_blissc() (0)
-#endif
-
-#ifdef CONFIG_MACH_THALES_ADC
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_THALES_ADC
-# endif
-# define machine_is_thales_adc() (machine_arch_type == MACH_TYPE_THALES_ADC)
-#else
-# define machine_is_thales_adc() (0)
-#endif
-
-#ifdef CONFIG_MACH_UBISYS_P9D_EVP
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_UBISYS_P9D_EVP
-# endif
-# define machine_is_ubisys_p9d_evp() (machine_arch_type == MACH_TYPE_UBISYS_P9D_EVP)
-#else
-# define machine_is_ubisys_p9d_evp() (0)
-#endif
-
-#ifdef CONFIG_MACH_ATDGP318
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ATDGP318
-# endif
-# define machine_is_atdgp318() (machine_arch_type == MACH_TYPE_ATDGP318)
-#else
-# define machine_is_atdgp318() (0)
-#endif
-
-#ifdef CONFIG_MACH_OMAP5_SEVM
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_OMAP5_SEVM
-# endif
-# define machine_is_omap5_sevm() (machine_arch_type == MACH_TYPE_OMAP5_SEVM)
-#else
-# define machine_is_omap5_sevm() (0)
-#endif
-
-#ifdef CONFIG_MACH_ARMADILLO800EVA
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ARMADILLO800EVA
-# endif
-# define machine_is_armadillo800eva() (machine_arch_type == MACH_TYPE_ARMADILLO800EVA)
-#else
-# define machine_is_armadillo800eva() (0)
-#endif
-
-#ifdef CONFIG_MACH_KZM9G
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_KZM9G
-# endif
-# define machine_is_kzm9g() (machine_arch_type == MACH_TYPE_KZM9G)
-#else
-# define machine_is_kzm9g() (0)
-#endif
-
-#ifdef CONFIG_MACH_COLIBRI_T30
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_COLIBRI_T30
-# endif
-# define machine_is_colibri_t30() (machine_arch_type == MACH_TYPE_COLIBRI_T30)
-#else
-# define machine_is_colibri_t30() (0)
-#endif
-
-#ifdef CONFIG_MACH_APALIS_T30
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_APALIS_T30
-# endif
-# define machine_is_apalis_t30() (machine_arch_type == MACH_TYPE_APALIS_T30)
-#else
-# define machine_is_apalis_t30() (0)
-#endif
-
-/*
- * These have not yet been registered
- */
-
-#ifndef machine_arch_type
-#define machine_arch_type __machine_arch_type
-#endif
+#define MACH_TYPE_ARMSTONEA9 4515
+#define MACH_TYPE_OMAP_BLAZETABLET 4516
+#define MACH_TYPE_AR6MXQ 4517
+#define MACH_TYPE_AR6MXS 4518
+#define MACH_TYPE_GWVENTANA 4520
+#define MACH_TYPE_IGEP0033 4521
+#define MACH_TYPE_H52C1_CONCERTO 4524
+#define MACH_TYPE_FCMBRD 4525
+#define MACH_TYPE_PCAAXS1 4526
+#define MACH_TYPE_LS_ORCA 4527
+#define MACH_TYPE_PCM051LB 4528
+#define MACH_TYPE_MX6S_LP507_GVCI 4529
+#define MACH_TYPE_DIDO 4530
+#define MACH_TYPE_SWARCO_ITC3_9G20 4531
+#define MACH_TYPE_ROBO_ROADY 4532
+#define MACH_TYPE_RSKRZA1 4533
+#define MACH_TYPE_SWARCO_SID 4534
+#define MACH_TYPE_MX6_IWG15S_SBC 4535
+#define MACH_TYPE_MX6Q_CAMARO 4536
+#define MACH_TYPE_HB6MXS 4537
+#define MACH_TYPE_LAGER 4538
+#define MACH_TYPE_LP8X4X 4539
+#define MACH_TYPE_TEGRATAB7 4540
+#define MACH_TYPE_ANDROMEDA 4541
+#define MACH_TYPE_BOOTES 4542
+#define MACH_TYPE_NETHMI 4543
+#define MACH_TYPE_TEGRATAB 4544
+#define MACH_TYPE_SOM5_EVB 4545
+#define MACH_TYPE_VENATICORUM 4546
+#define MACH_TYPE_STM_B2110 4547
+#define MACH_TYPE_ELUX_HATHOR 4548
+#define MACH_TYPE_HELIOS_V7 4549
+#define MACH_TYPE_XC10V1 4550
+#define MACH_TYPE_CP2U 4551
+#define MACH_TYPE_IAP_F 4552
+#define MACH_TYPE_IAP_G 4553
+#define MACH_TYPE_AAE 4554
+#define MACH_TYPE_PEGASUS 4555
+#define MACH_TYPE_CYGNUS 4556
+#define MACH_TYPE_CENTAURUS 4557
+#define MACH_TYPE_MSM8930_QRD8930 4558
+#define MACH_TYPE_QUBY_TIM 4559
+#define MACH_TYPE_ZEDI3250A 4560
+#define MACH_TYPE_GRUS 4561
+#define MACH_TYPE_APOLLO3 4562
+#define MACH_TYPE_COWON_R7 4563
+#define MACH_TYPE_TONGA3 4564
+#define MACH_TYPE_P535 4565
+#define MACH_TYPE_SA3874I 4566
+#define MACH_TYPE_MX6_NAVICO_COM 4567
+#define MACH_TYPE_PROXMOBIL2 4568
+#define MACH_TYPE_UBINUX1 4569
+#define MACH_TYPE_ISTOS 4570
+#define MACH_TYPE_BENVOLIO4 4571
+#define MACH_TYPE_ECO5_BX2 4572
+#define MACH_TYPE_EUKREA_CPUIMX28SD 4573
+#define MACH_TYPE_DOMOTAB 4574
+#define MACH_TYPE_PFLA03 4575
#endif
# for C files, just apend -marm, which will override previous -mthumb*
+ifndef CONFIG_ARM64
CFLAGS_cache.o := -marm
CFLAGS_cache-cp15.o := -marm
+endif
# For .S, drop -mthumb* and other thumb-related options.
# CFLAGS_REMOVE_* would not have an effet, so AFLAGS_REMOVE_*
* use it here.
*/
#include <asm/arch/boot0.h>
-ARM_SOC_BOOT0_HOOK
#endif
/*
{ pinmux(9), 1, 1 } /* USB0_DRVVBUS */
};
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
/* MMC0 pin muxer settings */
const struct pinmux_config mmc0_pins_8bit[] = {
{ pinmux(15), 2, 7 }, /* MMCSD0_CLK */
/* Boot config */
struct davinci_syscfg_regs {
dv_reg revid;
- dv_reg rsvd[13];
+ dv_reg rsvd[7];
+ dv_reg bootcfg;
+ dv_reg chiprevidr;
+ dv_reg rsvd2[4];
dv_reg kick0;
dv_reg kick1;
dv_reg rsvd1[52];
dv_reg mstpri[3];
- dv_reg rsvd2;
+ dv_reg rsvd3;
dv_reg pinmux[20];
dv_reg suspsrc;
dv_reg chipsig;
#define davinci_syscfg_regs \
((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
+enum {
+ DAVINCI_NAND8_BOOT = 0b001110,
+ DAVINCI_NAND16_BOOT = 0b010000,
+ DAVINCI_SD_OR_MMC_BOOT = 0b011100,
+ DAVINCI_MMC_ONLY_BOOT = 0b111100,
+ DAVINCI_SPI0_FLASH_BOOT = 0b001010,
+ DAVINCI_SPI1_FLASH_BOOT = 0b001100,
+};
+
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
/* Emulation suspend bits */
u32 spl_boot_device(void)
{
-#ifdef CONFIG_SPL_NAND_SIMPLE
- return BOOT_DEVICE_NAND;
-#elif defined(CONFIG_SPL_SPI_LOAD)
- return BOOT_DEVICE_SPI;
-#elif defined(CONFIG_SPL_MMC_LOAD)
- return BOOT_DEVICE_MMC1;
-#else
- puts("Unknown boot device\n");
- hang();
+ switch (davinci_syscfg_regs->bootcfg) {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+ case DAVINCI_NAND8_BOOT:
+ case DAVINCI_NAND16_BOOT:
+ return BOOT_DEVICE_NAND;
#endif
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ case DAVINCI_SD_OR_MMC_BOOT:
+ case DAVINCI_MMC_ONLY_BOOT:
+ return BOOT_DEVICE_MMC1;
+#endif
+
+#ifdef CONFIG_SPL_SPI_FLASH_SUPPORT
+ case DAVINCI_SPI0_FLASH_BOOT:
+ case DAVINCI_SPI1_FLASH_BOOT:
+ return BOOT_DEVICE_SPI;
+#endif
+
+ default:
+ puts("Unknown boot device\n");
+ hang();
+ }
}
point address depending on the device type
(secure/non-secure), boot media (xip/non-xip) and
image headers.
- default 0x402F4000
+ default 0x402F4000 if AM43XX
+ default 0x402F0400 if AM33XX
config PUB_ROM_DATA_SIZE
hex "Size in bytes of the L3 SRAM reserved by ROM to store data"
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
#endif
-#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC_OMAP_HS) && !defined(CONFIG_SPL_BUILD)
int cpu_mmc_init(bd_t *bis)
{
int ret;
ret = uclass_first_device(UCLASS_MISC, &dev);
if (ret || !dev)
return ret;
+
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
+ ret = usb_ether_init();
+ if (ret) {
+ error("USB ether init failed\n");
+ return ret;
+ }
+#endif
#endif
return 0;
}
u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
- debug("image entry point: 0x%X\n", spl_image->entry_point);
+ debug("image entry point: 0x%lX\n", spl_image->entry_point);
/* Pass the saved boot_params from rom code */
image_entry((u32 *)boot_params);
}
#
# SPDX-License-Identifier: GPL-2.0+
#
-quiet_cmd_mkomapsecimg = MKIMAGE $@
+quiet_cmd_mkomapsecimg = SECURE $@
ifneq ($(TI_SECURE_DEV_PKG),)
ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),)
ifneq ($(CONFIG_SPL_BUILD),)
else
cmd_mkomapsecimg = echo "WARNING:" \
"$(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh not found." \
- "$@ was NOT created!"
+ "$@ was NOT secured!"; cp $< $@
endif
else
cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
- "variable must be defined for TI secure devices. $@ was NOT created!"
+ "variable must be defined for TI secure devices. \
+ $@ was NOT secured!"; cp $< $@
endif
ifdef CONFIG_SPL_LOAD_FIT
else
cmd_omapsecureimg = echo "WARNING:" \
"$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh not found." \
- "$@ was NOT created!"; cp $< $@
+ "$@ was NOT secured!"; cp $< $@
endif
else
cmd_omapsecureimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
"variable must be defined for TI secure devices." \
- "$@ was NOT created!"; cp $< $@
+ "$@ was NOT secured!"; cp $< $@
endif
endif
# Standard X-LOADER target (QPSI, NOR flash)
-u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin
+u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkomapsecimg)
# For MLO targets (SD card boot) the final file name that is copied to the SD
# card FAT partition must be MLO, so we make a copy of the output file to a new
# file with that name
-u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin
+u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkomapsecimg)
@if [ -f $@ ]; then \
cp -f $@ MLO; \
fi
# Standard 2ND target (certain peripheral boot modes)
-u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin
+u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkomapsecimg)
# Standard ULO target (certain peripheral boot modes)
-u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin
+u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkomapsecimg)
# Standard ISSW target (certain devices, various boot modes)
-u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin
+u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkomapsecimg)
# For SPI flash on AM335x and AM43xx, these require special byte swap handling
# so we use the SPI_X-LOADER target instead of X-LOADER and let the
# create-boot-image.sh script handle that
-u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin
+u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkomapsecimg)
# For supporting single stage XiP QSPI on AM43xx, the image is a full u-boot
# file, not an SPL. In this case the mkomapsecimg command looks for a
# u-boot-HS_* prefix
-u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin
+u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin FORCE
$(call if_changed,mkomapsecimg)
# For supporting the SPL loading and interpreting of FIT images whose
MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
- $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
+ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
$(OF_LIST_TARGETS): dtbs
-%_HS.dtb: %.dtb
+%.dtb_HS: %.dtb FORCE
$(call if_changed,omapsecureimg)
- $(Q)if [ -f $@ ]; then \
- cp -f $@ $<; \
- fi
-u-boot-nodtb_HS.bin: u-boot-nodtb.bin
+u-boot-nodtb_HS.bin: u-boot-nodtb.bin FORCE
$(call if_changed,omapsecureimg)
-u-boot_HS.img: u-boot-nodtb_HS.bin u-boot.img $(patsubst %.dtb,%_HS.dtb,$(OF_LIST_TARGETS))
+u-boot_HS.img: u-boot-nodtb_HS.bin u-boot.img $(patsubst %.dtb,%.dtb_HS,$(OF_LIST_TARGETS)) FORCE
$(call if_changed,mkimage)
$(Q)if [ -f $@ ]; then \
cp -f $@ u-boot.img; \
#include <spl.h>
/* Index for signature verify ROM API */
+#ifdef CONFIG_AM33XX
+#define API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX (0x0000000C)
+#else
#define API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX (0x0000000E)
+#endif
static uint32_t secure_rom_call_args[5] __aligned(ARCH_DMA_MINALIGN);
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
#include <asm/arch/pmu_rk3288.h>
+#include <asm/arch/qos_rk3288.h>
#include <asm/arch/boot_mode.h>
#include <asm/gpio.h>
#include <dm/pinctrl.h>
return 0;
}
+int rk3288_qos_init(void)
+{
+ int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
+ /* set vop qos to higher priority */
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
+
+ if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+ "rockchip,rk3288-miniarm"))
+ {
+ /* set isp qos to higher priority */
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
+ }
+ return 0;
+}
+
int board_late_init(void)
{
setup_boot_mode();
+ rk3288_qos_init();
return rk_board_late_init();
}
config TARGET_CHROMEBOOK_MINNIE
bool "Google/Rockchip Veyron-Minnie Chromebook"
help
- Jerry is a RK3288-based convertible clamshell device with 2 USB 3.0
+ Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS
EC (Cortex-M3) to provide access to the keyboard and battery
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3399.h>
-int rockchip_get_clk(struct udevice **devp)
+static int rockchip_get_cruclk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
- DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp);
+ DM_GET_DRIVER(clk_rk3399), devp);
}
void *rockchip_get_cru(void)
struct udevice *dev;
int ret;
- ret = rockchip_get_clk(&dev);
+ ret = rockchip_get_cruclk(&dev);
if (ret)
return ERR_PTR(ret);
obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o
obj-$(CONFIG_MACH_SUN8I_H3) += dram_sun8i_h3.o
obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o
+obj-$(CONFIG_MACH_SUN50I) += dram_sun8i_h3.o
endif
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
static int spl_board_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+#if !defined(CONFIG_MACH_SUN8I_H3) && !defined(CONFIG_MACH_SUN50I)
struct sunxi_prcm_reg * const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
+#endif
clock_set_pll1(408000000);
writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
- writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
+ if (IS_ENABLED(CONFIG_MACH_SUN6I))
+ writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
}
#endif
}
#endif
-#ifdef CONFIG_MACH_SUN8I_A33
+#if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN50I)
void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (sigma_delta_enable)
- writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
+ writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0);
writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
(sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
+#include <asm/arch/cpu.h>
#include <linux/kconfig.h>
+/*
+ * The delay parameters below allow to allegedly specify delay times of some
+ * unknown unit for each individual bit trace in each of the four data bytes
+ * the 32-bit wide access consists of. Also three control signals can be
+ * adjusted individually.
+ */
+#define BITS_PER_BYTE 8
+#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
+/* The eight data lines (DQn) plus DM, DQS and DQSN */
+#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3)
struct dram_para {
- u32 read_delays;
- u32 write_delays;
u16 page_size;
u8 bus_width;
u8 dual_rank;
u8 row_bits;
+ const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
+ const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
+ const u8 ac_delays[31];
};
static inline int ns_to_t(int nanoseconds)
return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
}
-static u32 bin_to_mgray(int val)
-{
- static const u8 lookup_table[32] = {
- 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
- 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
- 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
- 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
- };
-
- return lookup_table[clamp(val, 0, 31)];
-}
-
-static int mgray_to_bin(u32 val)
-{
- static const u8 lookup_table[32] = {
- 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
- 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
- 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
- 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
- };
-
- return lookup_table[val & 0x1f];
-}
-
static void mctl_phy_init(u32 val)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
}
-static void mctl_dq_delay(u32 read, u32 write)
+static void mctl_set_bit_delays(struct dram_para *para)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
int i, j;
- u32 val;
-
- for (i = 0; i < 4; i++) {
- val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
- DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
-
- for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++)
- writel(val, &mctl_ctl->datx[i].iocr[j]);
- }
clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
- for (i = 0; i < 4; i++) {
- val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
- DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
+ for (i = 0; i < NR_OF_BYTE_LANES; i++)
+ for (j = 0; j < LINES_PER_BYTE_LANE; j++)
+ writel(DXBDLR_WRITE_DELAY(para->dx_write_delays[i][j]) |
+ DXBDLR_READ_DELAY(para->dx_read_delays[i][j]),
+ &mctl_ctl->dx[i].bdlr[j]);
- writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]);
- writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]);
- }
+ for (i = 0; i < 31; i++)
+ writel(ACBDLR_WRITE_DELAY(para->ac_delays[i]),
+ &mctl_ctl->acbdlr[i]);
setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
+}
- udelay(1);
+enum {
+ MBUS_PORT_CPU = 0,
+ MBUS_PORT_GPU = 1,
+ MBUS_PORT_UNUSED = 2,
+ MBUS_PORT_DMA = 3,
+ MBUS_PORT_VE = 4,
+ MBUS_PORT_CSI = 5,
+ MBUS_PORT_NAND = 6,
+ MBUS_PORT_SS = 7,
+ MBUS_PORT_TS = 8,
+ MBUS_PORT_DI = 9,
+ MBUS_PORT_DE = 10,
+ MBUS_PORT_DE_CFD = 11,
+};
+
+enum {
+ MBUS_QOS_LOWEST = 0,
+ MBUS_QOS_LOW,
+ MBUS_QOS_HIGH,
+ MBUS_QOS_HIGHEST
+};
+
+inline void mbus_configure_port(u8 port,
+ bool bwlimit,
+ bool priority,
+ u8 qos, /* MBUS_QOS_LOWEST .. MBUS_QOS_HIGEST */
+ u8 waittime, /* 0 .. 0xf */
+ u8 acs, /* 0 .. 0xff */
+ u16 bwl0, /* 0 .. 0xffff, bandwidth limit in MB/s */
+ u16 bwl1,
+ u16 bwl2)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
+ | (priority ? (1 << 1) : 0)
+ | ((qos & 0x3) << 2)
+ | ((waittime & 0xf) << 4)
+ | ((acs & 0xff) << 8)
+ | (bwl0 << 16) );
+ const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
+
+ debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
+ writel(cfg0, &mctl_com->mcr[port][0]);
+ writel(cfg1, &mctl_com->mcr[port][1]);
}
-static void mctl_set_master_priority(void)
+#define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
+ mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
+ MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
+
+static void mctl_set_master_priority_h3(void)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
/* enable bandwidth limit windows and set windows size 1us */
- writel(0x00010190, &mctl_com->bwcr);
+ writel((1 << 16) | (400 << 0), &mctl_com->bwcr);
/* set cpu high priority */
writel(0x00000001, &mctl_com->mapr);
- writel(0x0200000d, &mctl_com->mcr[0][0]);
- writel(0x00800100, &mctl_com->mcr[0][1]);
- writel(0x06000009, &mctl_com->mcr[1][0]);
- writel(0x01000400, &mctl_com->mcr[1][1]);
- writel(0x0200000d, &mctl_com->mcr[2][0]);
- writel(0x00600100, &mctl_com->mcr[2][1]);
- writel(0x0100000d, &mctl_com->mcr[3][0]);
- writel(0x00200080, &mctl_com->mcr[3][1]);
- writel(0x07000009, &mctl_com->mcr[4][0]);
- writel(0x01000640, &mctl_com->mcr[4][1]);
- writel(0x0100000d, &mctl_com->mcr[5][0]);
- writel(0x00200080, &mctl_com->mcr[5][1]);
- writel(0x01000009, &mctl_com->mcr[6][0]);
- writel(0x00400080, &mctl_com->mcr[6][1]);
- writel(0x0100000d, &mctl_com->mcr[7][0]);
- writel(0x00400080, &mctl_com->mcr[7][1]);
- writel(0x0100000d, &mctl_com->mcr[8][0]);
- writel(0x00400080, &mctl_com->mcr[8][1]);
- writel(0x04000009, &mctl_com->mcr[9][0]);
- writel(0x00400100, &mctl_com->mcr[9][1]);
- writel(0x2000030d, &mctl_com->mcr[10][0]);
- writel(0x04001800, &mctl_com->mcr[10][1]);
- writel(0x04000009, &mctl_com->mcr[11][0]);
- writel(0x00400120, &mctl_com->mcr[11][1]);
+ MBUS_CONF( CPU, true, HIGHEST, 0, 512, 256, 128);
+ MBUS_CONF( GPU, true, HIGH, 0, 1536, 1024, 256);
+ MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
+ MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32);
+ MBUS_CONF( VE, true, HIGH, 0, 1792, 1600, 256);
+ MBUS_CONF( CSI, true, HIGHEST, 0, 256, 128, 32);
+ MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
+ MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
+ MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
+ MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
+ MBUS_CONF( DE, true, HIGHEST, 3, 8192, 6120, 1024);
+ MBUS_CONF(DE_CFD, true, HIGH, 0, 1024, 288, 64);
}
-static void mctl_set_timing_params(struct dram_para *para)
+static void mctl_set_master_priority_a64(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ /* enable bandwidth limit windows and set windows size 1us */
+ writel(399, &mctl_com->tmr);
+ writel((1 << 16), &mctl_com->bwcr);
+
+ /* Port 2 is reserved per Allwinner's linux-3.10 source, yet they
+ * initialise it */
+ MBUS_CONF( CPU, true, HIGHEST, 0, 160, 100, 80);
+ MBUS_CONF( GPU, false, HIGH, 0, 1536, 1400, 256);
+ MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
+ MBUS_CONF( DMA, true, HIGH, 0, 256, 80, 100);
+ MBUS_CONF( VE, true, HIGH, 0, 1792, 1600, 256);
+ MBUS_CONF( CSI, true, HIGH, 0, 256, 128, 0);
+ MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
+ MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
+ MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
+ MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
+ MBUS_CONF( DE, true, HIGH, 2, 8192, 6144, 2048);
+ MBUS_CONF(DE_CFD, true, HIGH, 0, 1280, 144, 64);
+
+ writel(0x81000004, &mctl_com->mdfs_bwlr[2]);
+}
+
+static void mctl_set_master_priority(uint16_t socid)
+{
+ switch (socid) {
+ case SOCID_H3:
+ mctl_set_master_priority_h3();
+ return;
+ case SOCID_A64:
+ mctl_set_master_priority_a64();
+ return;
+ }
+}
+
+static void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
}
-static void mctl_zq_calibration(struct dram_para *para)
+static u32 bin_to_mgray(int val)
+{
+ static const u8 lookup_table[32] = {
+ 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
+ 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
+ 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
+ 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
+ };
+
+ return lookup_table[clamp(val, 0, 31)];
+}
+
+static int mgray_to_bin(u32 val)
+{
+ static const u8 lookup_table[32] = {
+ 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
+ 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
+ 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
+ 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
+ };
+
+ return lookup_table[val & 0x1f];
+}
+
+static void mctl_h3_zq_calibration_quirk(struct dram_para *para)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
}
-static void mctl_sys_init(struct dram_para *para)
+static void mctl_sys_init(uint16_t socid, struct dram_para *para)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
+ if (socid == SOCID_A64)
+ clrbits_le32(&ccm->pll11_cfg, CCM_PLL11_CTRL_EN);
udelay(10);
clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
udelay(1000);
- clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
- clrsetbits_le32(&ccm->dram_clk_cfg,
- CCM_DRAMCLK_CFG_DIV_MASK | CCM_DRAMCLK_CFG_SRC_MASK,
- CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5 |
- CCM_DRAMCLK_CFG_UPD);
+ if (socid == SOCID_A64) {
+ clock_set_pll11(CONFIG_DRAM_CLK * 2 * 1000000, false);
+ clrsetbits_le32(&ccm->dram_clk_cfg,
+ CCM_DRAMCLK_CFG_DIV_MASK |
+ CCM_DRAMCLK_CFG_SRC_MASK,
+ CCM_DRAMCLK_CFG_DIV(1) |
+ CCM_DRAMCLK_CFG_SRC_PLL11 |
+ CCM_DRAMCLK_CFG_UPD);
+ } else if (socid == SOCID_H3) {
+ clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
+ clrsetbits_le32(&ccm->dram_clk_cfg,
+ CCM_DRAMCLK_CFG_DIV_MASK |
+ CCM_DRAMCLK_CFG_SRC_MASK,
+ CCM_DRAMCLK_CFG_DIV(1) |
+ CCM_DRAMCLK_CFG_SRC_PLL5 |
+ CCM_DRAMCLK_CFG_UPD);
+ }
mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
udelay(500);
}
-static int mctl_channel_init(struct dram_para *para)
+/* These are more guessed based on some Allwinner code. */
+#define DX_GCR_ODT_DYNAMIC (0x0 << 4)
+#define DX_GCR_ODT_ALWAYS_ON (0x1 << 4)
+#define DX_GCR_ODT_OFF (0x2 << 4)
+
+static int mctl_channel_init(uint16_t socid, struct dram_para *para)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
unsigned int i;
mctl_set_cr(para);
- mctl_set_timing_params(para);
- mctl_set_master_priority();
+ mctl_set_timing_params(socid, para);
+ mctl_set_master_priority(socid);
/* setting VTC, default disable all VT */
clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
/* set dramc odt */
for (i = 0; i < 4; i++)
- clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) |
+ clrsetbits_le32(&mctl_ctl->dx[i].gcr, (0x3 << 4) |
(0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
(0x3 << 14),
- IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
+ IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
+ DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF);
/* AC PDR should always ON */
setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
/* set DQS auto gating PD mode */
setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
- /* dx ddr_clk & hdr_clk dynamic mode */
- clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
-
- /* dphy & aphy phase select 270 degree */
- clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
- (0x1 << 10) | (0x2 << 8));
+ if (socid == SOCID_H3) {
+ /* dx ddr_clk & hdr_clk dynamic mode */
+ clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
+
+ /* dphy & aphy phase select 270 degree */
+ clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
+ (0x1 << 10) | (0x2 << 8));
+ } else if (socid == SOCID_A64) {
+ /* dphy & aphy phase select ? */
+ clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
+ (0x0 << 10) | (0x3 << 8));
+ }
/* set half DQ */
if (para->bus_width != 32) {
- writel(0x0, &mctl_ctl->datx[2].gcr);
- writel(0x0, &mctl_ctl->datx[3].gcr);
+ writel(0x0, &mctl_ctl->dx[2].gcr);
+ writel(0x0, &mctl_ctl->dx[3].gcr);
}
/* data training configuration */
clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
(para->dual_rank ? 0x3 : 0x1) << 24);
+ mctl_set_bit_delays(para);
+ udelay(50);
- if (para->read_delays || para->write_delays) {
- mctl_dq_delay(para->read_delays, para->write_delays);
- udelay(50);
- }
+ if (socid == SOCID_H3) {
+ mctl_h3_zq_calibration_quirk(para);
- mctl_zq_calibration(para);
+ mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
+ PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
+ } else if (socid == SOCID_A64) {
+ clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);
- mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST |
- PIR_DRAMINIT | PIR_QSGATE);
+ mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
+ PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
+ }
/* detect ranks and bus width */
if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
/* only one rank */
- if (((readl(&mctl_ctl->datx[0].gsr[0]) >> 24) & 0x2) ||
- ((readl(&mctl_ctl->datx[1].gsr[0]) >> 24) & 0x2)) {
+ if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2) ||
+ ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2)) {
clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
para->dual_rank = 0;
}
/* only half DQ width */
- if (((readl(&mctl_ctl->datx[2].gsr[0]) >> 24) & 0x1) ||
- ((readl(&mctl_ctl->datx[3].gsr[0]) >> 24) & 0x1)) {
- writel(0x0, &mctl_ctl->datx[2].gcr);
- writel(0x0, &mctl_ctl->datx[3].gcr);
+ if (((readl(&mctl_ctl->dx[2].gsr[0]) >> 24) & 0x1) ||
+ ((readl(&mctl_ctl->dx[3].gsr[0]) >> 24) & 0x1)) {
+ writel(0x0, &mctl_ctl->dx[2].gcr);
+ writel(0x0, &mctl_ctl->dx[3].gcr);
para->bus_width = 16;
}
udelay(10);
/* set PGCR3, CKE polarity */
- writel(0x00aa0060, &mctl_ctl->pgcr[3]);
+ if (socid == SOCID_H3)
+ writel(0x00aa0060, &mctl_ctl->pgcr[3]);
+ else if (socid == SOCID_A64)
+ writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
/* power down zq calibration module for power save */
setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN);
break;
}
+/*
+ * The actual values used here are taken from Allwinner provided boot0
+ * binaries, though they are probably board specific, so would likely benefit
+ * from invidual tuning for each board. Apparently a lot of boards copy from
+ * some Allwinner reference design, so we go with those generic values for now
+ * in the hope that they are reasonable for most (all?) boards.
+ */
+#define SUN8I_H3_DX_READ_DELAYS \
+ {{ 18, 18, 18, 18, 18, 18, 18, 18, 18, 0, 0 }, \
+ { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
+ { 18, 18, 18, 18, 18, 18, 18, 18, 18, 0, 0 }, \
+ { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }}
+#define SUN8I_H3_DX_WRITE_DELAYS \
+ {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 6 }}
+#define SUN8I_H3_AC_DELAYS \
+ { 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0 }
+
+#define SUN50I_A64_DX_READ_DELAYS \
+ {{ 16, 16, 16, 16, 17, 16, 16, 17, 16, 1, 0 }, \
+ { 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 0 }, \
+ { 16, 17, 17, 16, 16, 16, 16, 16, 16, 0, 0 }, \
+ { 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 0 }}
+#define SUN50I_A64_DX_WRITE_DELAYS \
+ {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 15 }, \
+ { 0, 0, 0, 0, 1, 1, 1, 1, 0, 10, 10 }, \
+ { 1, 0, 1, 1, 1, 1, 1, 1, 0, 11, 11 }, \
+ { 1, 0, 0, 1, 1, 1, 1, 1, 0, 12, 12 }}
+#define SUN50I_A64_AC_DELAYS \
+ { 5, 5, 13, 10, 2, 5, 3, 3, \
+ 0, 3, 3, 3, 1, 0, 0, 0, \
+ 3, 4, 0, 3, 4, 1, 4, 0, \
+ 1, 1, 0, 1, 13, 5, 4 }
+
unsigned long sunxi_dram_init(void)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
struct dram_para para = {
- .read_delays = 0x00007979, /* dram_tpr12 */
- .write_delays = 0x6aaa0000, /* dram_tpr11 */
.dual_rank = 0,
.bus_width = 32,
.row_bits = 15,
.page_size = 4096,
- };
- mctl_sys_init(¶);
- if (mctl_channel_init(¶))
+#if defined(CONFIG_MACH_SUN8I_H3)
+ .dx_read_delays = SUN8I_H3_DX_READ_DELAYS,
+ .dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS,
+ .ac_delays = SUN8I_H3_AC_DELAYS,
+#elif defined(CONFIG_MACH_SUN50I)
+ .dx_read_delays = SUN50I_A64_DX_READ_DELAYS,
+ .dx_write_delays = SUN50I_A64_DX_WRITE_DELAYS,
+ .ac_delays = SUN50I_A64_AC_DELAYS,
+#endif
+ };
+/*
+ * Let the compiler optimize alternatives away by passing this value into
+ * the static functions. This saves us #ifdefs, but still keeps the binary
+ * small.
+ */
+#if defined(CONFIG_MACH_SUN8I_H3)
+ uint16_t socid = SOCID_H3;
+#elif defined(CONFIG_MACH_SUN50I)
+ uint16_t socid = SOCID_A64;
+#endif
+
+ mctl_sys_init(socid, ¶);
+ if (mctl_channel_init(socid, ¶))
return 0;
if (para.dual_rank)
udelay(1);
/* odt delay */
- writel(0x0c000400, &mctl_ctl->odtcfg);
+ if (socid == SOCID_H3)
+ writel(0x0c000400, &mctl_ctl->odtcfg);
+
+ if (socid == SOCID_A64) {
+ setbits_le32(&mctl_ctl->vtfcr, 2 << 8);
+ clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13));
+ }
/* clear credit value */
setbits_le32(&mctl_com->cccr, 1 << 31);
mctl_auto_detect_dram_size(¶);
mctl_set_cr(¶);
- return (1 << (para.row_bits + 3)) * para.page_size *
+ return (1UL << (para.row_bits + 3)) * para.page_size *
(para.dual_rank ? 2 : 1);
}
--- /dev/null
+@
+@ ARMv8 RMR reset sequence on Allwinner SoCs.
+@
+@ All 64-bit capable Allwinner SoCs reset in AArch32 (and continue to
+@ exectute the Boot ROM in this state), so we need to switch to AArch64
+@ at some point.
+@ Section G6.2.133 of the ARMv8 ARM describes the Reset Management Register
+@ (RMR), which triggers a warm-reset of a core and can request to switch
+@ into a different execution state (AArch32 or AArch64).
+@ The address at which execution starts after the reset is held in the
+@ RVBAR system register, which is architecturally read-only.
+@ Allwinner provides a writable alias of this register in MMIO space, so
+@ we can easily set the start address of AArch64 code.
+@ This code below switches to AArch64 and starts execution at the specified
+@ start address. It needs to be assembled by an ARM(32) assembler and
+@ the machine code must be inserted as verbatim .word statements into the
+@ beginning of the AArch64 U-Boot code.
+@ To get the encoded bytes, use:
+@ ${CROSS_COMPILE}gcc -c -o rmr_switch.o rmr_switch.S
+@ ${CROSS_COMPILE}objdump -d rmr_switch.o
+@
+@ The resulting words should be inserted into the U-Boot file at
+@ arch/arm/include/asm/arch-sunxi/boot0.h.
+@
+@ This file is not build by the U-Boot build system, but provided only as a
+@ reference and to be able to regenerate a (probably fixed) version of this
+@ code found in encoded form in boot0.h.
+
+.text
+
+ ldr r1, =0x017000a0 @ MMIO mapped RVBAR[0] register
+ ldr r0, =0x57aA7add @ start address, to be replaced
+ str r0, [r1]
+ dsb sy
+ isb sy
+ mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
+ orr r0, r0, #3 @ request reset in AArch64
+ mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register
+ isb sy
+1: wfi
+ b 1b
pin_mux_spi();
#endif
-#ifdef CONFIG_TEGRA_MMC
+#ifdef CONFIG_MMC_SDHCI_TEGRA
pin_mux_mmc();
#endif
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
- debug("image entry point: 0x%X\n", spl_image->entry_point);
+ debug("image entry point: 0x%lX\n", spl_image->entry_point);
start_cpu((u32)spl_image->entry_point);
halt_avp();
extern unsigned long nvtboot_boot_x0;
+static int set_fdt_addr(void)
+{
+ int ret;
+
+ ret = setenv_hex("fdt_addr", nvtboot_boot_x0);
+ if (ret) {
+ printf("Failed to set fdt_addr to point at DTB: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
/*
* Attempt to use /chosen/nvidia,ether-mac in the nvtboot DTB to U-Boot's
* ethaddr environment variable if possible.
int tegra_soc_board_init_late(void)
{
+ /*
+ * Ignore errors here; the value may not be used depending on
+ * extlinux.conf or boot script content.
+ */
+ set_fdt_addr();
/* Ignore errors here; not all cases care about Ethernet addresses */
set_ethaddr_from_nvtboot();
ifdef CONFIG_SPL_BUILD
-obj-y += init/ bcu/ memconf/
-obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
+obj-y += spl_board_init.o
+obj-y += memconf.o
+obj-y += bcu/
else
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-y += reset.o
+obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ micro-support-card.o
+obj-y += pinctrl-glue.o
+
endif
obj-y += boards.o
obj-y += boot-mode/
obj-y += clk/
obj-y += dram/
-obj-y += pinctrl-glue.o
-obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/
obj-$(CONFIG_CPU_V7) += arm32/
/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
-int uniphier_ld4_bcu_init(const struct uniphier_board_data *bd)
+void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd)
{
int shift;
shift -= 32;
writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
-
- return 0;
}
/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
-int uniphier_sld3_bcu_init(const struct uniphier_board_data *bd)
+void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd)
{
int shift;
shift -= 32;
writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
-
- return 0;
}
writel(tmp, 0x55000090);
}
-static void uniphier_nand_pin_init(bool cs2)
+#ifdef CONFIG_ARCH_UNIPHIER_LD11
+static void uniphier_ld11_misc_init(void)
{
-#ifdef CONFIG_NAND_DENALI
- if (uniphier_pin_init(cs2 ? "nand2cs_grp" : "nand_grp"))
- pr_err("failed to init NAND pins\n");
-#endif
+ sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
+ sg_set_iectrl(149);
+ sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
+ sg_set_iectrl(153);
}
+#endif
-int board_init(void)
+#ifdef CONFIG_ARCH_UNIPHIER_LD20
+static void uniphier_ld20_misc_init(void)
{
- const struct uniphier_board_data *bd;
+ sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
+ sg_set_iectrl(149);
+ sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
+ sg_set_iectrl(153);
+
+ /* ES1 errata: increase VDD09 supply to suppress VBO noise */
+ if (uniphier_get_soc_revision() == 1) {
+ writel(0x00000003, 0x6184e004);
+ writel(0x00000100, 0x6184e040);
+ writel(0x0000b500, 0x6184e024);
+ writel(0x00000001, 0x6184e000);
+ }
- led_puts("U0");
+ cci500_init(2);
+}
+#endif
- bd = uniphier_get_board_param();
- if (!bd)
- return -ENODEV;
+struct uniphier_initdata {
+ enum uniphier_soc_id soc_id;
+ bool nand_2cs;
+ void (*sbc_init)(void);
+ void (*pll_init)(void);
+ void (*clk_init)(void);
+ void (*misc_init)(void);
+};
- switch (uniphier_get_soc_type()) {
+struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
- case SOC_UNIPHIER_SLD3:
- uniphier_nand_pin_init(true);
- led_puts("U1");
- uniphier_sld3_pll_init();
- uniphier_ld4_clk_init();
- break;
+ {
+ .soc_id = SOC_UNIPHIER_SLD3,
+ .nand_2cs = true,
+ .sbc_init = uniphier_sbc_init_admulti,
+ .pll_init = uniphier_sld3_pll_init,
+ .clk_init = uniphier_ld4_clk_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
- case SOC_UNIPHIER_LD4:
- uniphier_nand_pin_init(true);
- led_puts("U1");
- uniphier_ld4_pll_init();
- uniphier_ld4_clk_init();
- break;
+ {
+ .soc_id = SOC_UNIPHIER_LD4,
+ .nand_2cs = true,
+ .sbc_init = uniphier_ld4_sbc_init,
+ .pll_init = uniphier_ld4_pll_init,
+ .clk_init = uniphier_ld4_clk_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
- case SOC_UNIPHIER_PRO4:
- uniphier_nand_pin_init(false);
- led_puts("U1");
- uniphier_pro4_pll_init();
- uniphier_pro4_clk_init();
- break;
+ {
+ .soc_id = SOC_UNIPHIER_PRO4,
+ .nand_2cs = false,
+ .sbc_init = uniphier_sbc_init_savepin,
+ .pll_init = uniphier_pro4_pll_init,
+ .clk_init = uniphier_pro4_clk_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
- case SOC_UNIPHIER_SLD8:
- uniphier_nand_pin_init(true);
- led_puts("U1");
- uniphier_ld4_pll_init();
- uniphier_ld4_clk_init();
- break;
+ {
+ .soc_id = SOC_UNIPHIER_SLD8,
+ .nand_2cs = true,
+ .sbc_init = uniphier_ld4_sbc_init,
+ .pll_init = uniphier_ld4_pll_init,
+ .clk_init = uniphier_ld4_clk_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
- case SOC_UNIPHIER_PRO5:
- uniphier_nand_pin_init(true);
- led_puts("U1");
- uniphier_pro5_clk_init();
- break;
+ {
+ .soc_id = SOC_UNIPHIER_PRO5,
+ .nand_2cs = true,
+ .sbc_init = uniphier_sbc_init_savepin,
+ .clk_init = uniphier_pro5_clk_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
- case SOC_UNIPHIER_PXS2:
- uniphier_nand_pin_init(true);
- led_puts("U1");
- uniphier_pxs2_clk_init();
- break;
+ {
+ .soc_id = SOC_UNIPHIER_PXS2,
+ .nand_2cs = true,
+ .sbc_init = uniphier_pxs2_sbc_init,
+ .clk_init = uniphier_pxs2_clk_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
- case SOC_UNIPHIER_LD6B:
- uniphier_nand_pin_init(true);
- led_puts("U1");
- uniphier_pxs2_clk_init();
- break;
+ {
+ .soc_id = SOC_UNIPHIER_LD6B,
+ .nand_2cs = true,
+ .sbc_init = uniphier_pxs2_sbc_init,
+ .clk_init = uniphier_pxs2_clk_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
- case SOC_UNIPHIER_LD11:
- uniphier_nand_pin_init(false);
- sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
- sg_set_iectrl(149);
- sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
- sg_set_iectrl(153);
- led_puts("U1");
- uniphier_ld11_pll_init();
- uniphier_ld11_clk_init();
- break;
+ {
+ .soc_id = SOC_UNIPHIER_LD11,
+ .nand_2cs = false,
+ .sbc_init = uniphier_ld11_sbc_init,
+ .pll_init = uniphier_ld11_pll_init,
+ .clk_init = uniphier_ld11_clk_init,
+ .misc_init = uniphier_ld11_misc_init,
+ },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
- case SOC_UNIPHIER_LD20:
- /* ES1 errata: increase VDD09 supply to suppress VBO noise */
- if (uniphier_get_soc_revision() == 1) {
- writel(0x00000003, 0x6184e004);
- writel(0x00000100, 0x6184e040);
- writel(0x0000b500, 0x6184e024);
- writel(0x00000001, 0x6184e000);
- }
- uniphier_nand_pin_init(false);
- sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
- sg_set_iectrl(149);
- sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
- sg_set_iectrl(153);
- led_puts("U1");
- uniphier_ld20_pll_init(bd);
- uniphier_ld20_clk_init();
- cci500_init(2);
- break;
+ {
+ .soc_id = SOC_UNIPHIER_LD20,
+ .nand_2cs = false,
+ .sbc_init = uniphier_ld11_sbc_init,
+ .pll_init = uniphier_ld20_pll_init,
+ .misc_init = uniphier_ld20_misc_init,
+ },
#endif
- default:
- break;
+};
+
+static struct uniphier_initdata *uniphier_get_initdata(
+ enum uniphier_soc_id soc_id)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(uniphier_initdata); i++) {
+ if (uniphier_initdata[i].soc_id == soc_id)
+ return &uniphier_initdata[i];
}
- uniphier_setup_xirq();
+ return NULL;
+}
+
+int board_init(void)
+{
+ struct uniphier_initdata *initdata;
+ enum uniphier_soc_id soc_id;
+ int ret;
+
+ led_puts("U0");
+
+ soc_id = uniphier_get_soc_type();
+ initdata = uniphier_get_initdata(soc_id);
+ if (!initdata) {
+ pr_err("unsupported board\n");
+ return -EINVAL;
+ }
+
+ initdata->sbc_init();
+
+ support_card_init();
+
+ led_puts("U0");
+
+ if (IS_ENABLED(CONFIG_NAND_DENALI)) {
+ ret = uniphier_pin_init(initdata->nand_2cs ?
+ "nand2cs_grp" : "nand_grp");
+ if (ret)
+ pr_err("failed to init NAND pins\n");
+ }
+
+ led_puts("U1");
+
+ if (initdata->pll_init)
+ initdata->pll_init();
led_puts("U2");
- support_card_late_init();
+ if (initdata->clk_init)
+ initdata->clk_init();
led_puts("U3");
+ if (initdata->misc_init)
+ initdata->misc_init();
+
+ led_puts("U4");
+
+ uniphier_setup_xirq();
+
+ led_puts("U5");
+
+ support_card_late_init();
+
+ led_puts("U6");
+
#ifdef CONFIG_ARM64
uniphier_smp_kick_all_cpus();
#endif
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-clk-ld4.o dpll-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD4) += early-clk-ld4.o dpll-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += early-clk-ld4.o dpll-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o dpll-sld8.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o dpll-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o dpll-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-early-sld3.o clk-dram-sld3.o dpll-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-sld3.o clk-dram-sld3.o dpll-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-sld3.o clk-dram-sld3.o dpll-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-sld3.o clk-dram-sld3.o dpll-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-sld3.o clk-dram-pro5.o dpll-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-early-ld11.o clk-dram-ld11.o dpll-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-early-ld11.o clk-dram-ld20.o dpll-ld20.o
else
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-ld20.o
endif
/*
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016-2017 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "../sc64-regs.h"
-int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd)
+void uniphier_ld11_dram_clk_init(void)
{
u32 tmp;
writel(tmp, SC_RSTCTRL7);
/* provide clocks */
- tmp = readl(SC_CLKCTRL4);
- tmp |= SC_CLKCTRL4_PERI;
- writel(tmp, SC_CLKCTRL4);
-
tmp = readl(SC_CLKCTRL7);
tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30;
writel(tmp, SC_CLKCTRL7);
-
- return 0;
}
/*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016-2017 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "../sc64-regs.h"
-int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd)
+void uniphier_ld20_dram_clk_init(void)
{
u32 tmp;
writel(tmp, SC_RSTCTRL7);
/* provide clocks */
- tmp = readl(SC_CLKCTRL4);
- tmp |= SC_CLKCTRL4_PERI;
- writel(tmp, SC_CLKCTRL4);
-
tmp = readl(SC_CLKCTRL7);
tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 |
SC_CLKCTRL7_UMC30;
writel(tmp, SC_CLKCTRL7);
-
- return 0;
}
/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "../sc-regs.h"
-int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd)
+void uniphier_pro5_dram_clk_init(void)
{
u32 tmp;
SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
writel(tmp, SC_RSTCTRL4);
- readl(SC_RSTCTRL); /* dummy read */
+ readl(SC_RSTCTRL4); /* dummy read */
/* provide clocks */
- tmp = readl(SC_CLKCTRL);
- tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
- writel(tmp, SC_CLKCTRL);
tmp = readl(SC_CLKCTRL4);
tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
SC_CLKCTRL4_CEN_UMC0;
writel(tmp, SC_CLKCTRL4);
readl(SC_CLKCTRL4); /* dummy read */
-
- return 0;
}
/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016-2017 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "../sc-regs.h"
-int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd)
+void uniphier_pxs2_dram_clk_init(void)
{
u32 tmp;
/* deassert reset */
- if (spl_boot_device() != BOOT_DEVICE_NAND) {
- tmp = readl(SC_RSTCTRL);
- tmp &= ~SC_RSTCTRL_NRST_NAND;
- writel(tmp, SC_RSTCTRL);
- };
-
tmp = readl(SC_RSTCTRL4);
tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
readl(SC_RSTCTRL4); /* dummy read */
/* provide clocks */
- tmp = readl(SC_CLKCTRL);
- tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
- writel(tmp, SC_CLKCTRL);
-
tmp = readl(SC_CLKCTRL4);
tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 |
SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0;
writel(tmp, SC_CLKCTRL4);
readl(SC_CLKCTRL4); /* dummy read */
-
- return 0;
}
/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2017 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "../sc-regs.h"
-int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd)
+void uniphier_sld3_dram_clk_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL);
-
tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
- if (spl_boot_device() != BOOT_DEVICE_NAND)
- tmp &= ~SC_RSTCTRL_NRST_NAND;
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
/* provide clocks */
tmp = readl(SC_CLKCTRL);
- tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+ tmp |= SC_CLKCTRL_CEN_UMC;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
-
- return 0;
}
--- /dev/null
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+
+void uniphier_ld11_early_clk_init(void)
+{
+ u32 tmp;
+
+ /* provide clocks */
+ tmp = readl(SC_CLKCTRL4);
+ tmp |= SC_CLKCTRL4_PERI;
+ writel(tmp, SC_CLKCTRL4);
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2017 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+
+void uniphier_sld3_early_clk_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ if (spl_boot_device() != BOOT_DEVICE_NAND) {
+ tmp = readl(SC_RSTCTRL);
+ tmp &= ~SC_RSTCTRL_NRST_NAND;
+ writel(tmp, SC_RSTCTRL);
+ };
+
+ /* provide clocks */
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
+++ /dev/null
-/*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc64-regs.h"
-
-void uniphier_ld20_clk_init(void)
-{
-}
--- /dev/null
+#include "../init.h"
+
+int uniphier_pro5_dpll_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
--- /dev/null
+#include "../init.h"
+
+int uniphier_pxs2_dpll_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
#include "../sc64-regs.h"
#include "pll.h"
-int uniphier_ld20_pll_init(const struct uniphier_board_data *bd)
+void uniphier_ld20_pll_init(void)
{
uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
/* do nothing for SPLL */
uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
uniphier_ld20_dspll_init(SC_A2PLLCTRL);
-
- return 0;
}
ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += umc-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \
ddrphy-training.o ddrphy-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += umc-pro4.o \
ddrphy-training.o ddrphy-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \
ddrphy-training.o ddrphy-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += umc-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += umc-ld11.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "../init.h"
+
+int uniphier_pro5_umc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
--- /dev/null
+#include "../init.h"
+
+int uniphier_sld3_umc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
int uniphier_ld20_init(const struct uniphier_board_data *bd);
#if defined(CONFIG_MICRO_SUPPORT_CARD)
-int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd);
-int uniphier_sbc_init_savepin(const struct uniphier_board_data *bd);
-int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd);
-int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd);
+void uniphier_sbc_init_admulti(void);
+void uniphier_sbc_init_savepin(void);
+void uniphier_ld4_sbc_init(void);
+void uniphier_pxs2_sbc_init(void);
+void uniphier_ld11_sbc_init(void);
#else
-static inline int uniphier_sbc_init_admulti(
- const struct uniphier_board_data *bd)
+static inline void uniphier_sbc_init_admulti(void)
{
- return 0;
}
-static inline int uniphier_sbc_init_savepin(
- const struct uniphier_board_data *bd)
+static inline void uniphier_sbc_init_savepin(void)
{
- return 0;
}
-static inline int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd)
+static inline void uniphier_ld4_sbc_init(void)
{
- return 0;
}
-static inline int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd)
+static inline void uniphier_pxs2_sbc_init(void)
+{
+}
+
+static inline void uniphier_ld11_sbc_init(void)
{
- return 0;
}
#endif
-int uniphier_sld3_bcu_init(const struct uniphier_board_data *bd);
-int uniphier_ld4_bcu_init(const struct uniphier_board_data *bd);
+void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd);
+void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd);
-int memconf_init(const struct uniphier_board_data *bd);
-int uniphier_sld3_memconf_init(const struct uniphier_board_data *bd);
-int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd);
+int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd);
+int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd);
+int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd);
int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd);
int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd);
int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd);
int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd);
+int uniphier_pro5_dpll_init(const struct uniphier_board_data *bd);
+int uniphier_pxs2_dpll_init(const struct uniphier_board_data *bd);
int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd);
int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd);
-int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
-int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd);
-int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd);
-int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd);
-int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
+void uniphier_sld3_early_clk_init(void);
+void uniphier_ld11_early_clk_init(void);
+
+void uniphier_sld3_dram_clk_init(void);
+void uniphier_pro5_dram_clk_init(void);
+void uniphier_pxs2_dram_clk_init(void);
+void uniphier_ld11_dram_clk_init(void);
+void uniphier_ld20_dram_clk_init(void);
+int uniphier_sld3_umc_init(const struct uniphier_board_data *bd);
int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
+int uniphier_pro5_umc_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);
void uniphier_ld4_pll_init(void);
void uniphier_pro4_pll_init(void);
void uniphier_ld11_pll_init(void);
-int uniphier_ld20_pll_init(const struct uniphier_board_data *bd);
+void uniphier_ld20_pll_init(void);
void uniphier_ld4_clk_init(void);
void uniphier_pro4_clk_init(void);
void uniphier_pro5_clk_init(void);
void uniphier_pxs2_clk_init(void);
void uniphier_ld11_clk_init(void);
-void uniphier_ld20_clk_init(void);
int uniphier_pin_init(const char *pinconfig_name);
void uniphier_smp_kick_all_cpus(void);
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += init.o
-
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += init-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD4) += init-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += init-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += init-sld8.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += init-pro5.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += init-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += init-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11) += init-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += init-ld20.o
+++ /dev/null
-/*
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../micro-support-card.h"
-
-int uniphier_ld11_init(const struct uniphier_board_data *bd)
-{
- uniphier_sbc_init_savepin(bd);
- uniphier_pxs2_sbc_init(bd);
- /* pins for NAND and System Bus are multiplexed */
- if (spl_boot_device() != BOOT_DEVICE_NAND)
- uniphier_pin_init("system_bus_grp");
-
- support_card_reset();
-
- support_card_init();
-
- led_puts("L0");
-
- memconf_init(bd);
-
- led_puts("L1");
-
- uniphier_ld11_early_clk_init(bd);
-
- led_puts("L2");
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_puts("L3");
-
- uniphier_ld11_dpll_init(bd);
-
- led_puts("L4");
-
- {
- int res;
-
- res = uniphier_ld11_umc_init(bd);
- if (res < 0) {
- while (1)
- ;
- }
- }
-
- led_puts("L5");
-
- dcache_disable();
-
- led_puts("L6");
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../micro-support-card.h"
-
-int uniphier_ld20_init(const struct uniphier_board_data *bd)
-{
- uniphier_sbc_init_savepin(bd);
- uniphier_pxs2_sbc_init(bd);
- /* pins for NAND and System Bus are multiplexed */
- if (spl_boot_device() != BOOT_DEVICE_NAND)
- uniphier_pin_init("system_bus_grp");
-
- support_card_reset();
-
- support_card_init();
-
- led_puts("L0");
-
- memconf_init(bd);
- uniphier_pxs2_memconf_init(bd);
-
- led_puts("L1");
-
- uniphier_ld20_early_clk_init(bd);
-
- led_puts("L2");
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_puts("L3");
-
- uniphier_ld20_dpll_init(bd);
-
- led_puts("L4");
-
- {
- int res;
-
- res = uniphier_ld20_umc_init(bd);
- if (res < 0) {
- while (1)
- ;
- }
- }
-
- led_puts("L5");
-
- dcache_disable();
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2013-2015 Panasonic Corporation
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../micro-support-card.h"
-
-int uniphier_ld4_init(const struct uniphier_board_data *bd)
-{
- uniphier_ld4_bcu_init(bd);
-
- uniphier_sbc_init_savepin(bd);
- uniphier_ld4_sbc_init(bd);
-
- support_card_reset();
-
- uniphier_ld4_dpll_init(bd);
-
- support_card_init();
-
- led_puts("L0");
-
- memconf_init(bd);
-
- led_puts("L1");
-
- uniphier_ld4_early_clk_init(bd);
-
- led_puts("L2");
-
- led_puts("L3");
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_puts("L4");
-
- {
- int res;
-
- res = uniphier_ld4_umc_init(bd);
- if (res < 0) {
- while (1)
- ;
- }
- }
-
- led_puts("L5");
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2013-2015 Panasonic Corporation
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../micro-support-card.h"
-
-int uniphier_pro4_init(const struct uniphier_board_data *bd)
-{
- uniphier_sbc_init_savepin(bd);
-
- support_card_reset();
-
- uniphier_pro4_dpll_init(bd);
-
- support_card_init();
-
- led_puts("L0");
-
- memconf_init(bd);
-
- led_puts("L1");
-
- uniphier_ld4_early_clk_init(bd);
-
- led_puts("L2");
-
- led_puts("L3");
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_puts("L4");
-
- {
- int res;
-
- res = uniphier_pro4_umc_init(bd);
- if (res < 0) {
- while (1)
- ;
- }
- }
-
- led_puts("L5");
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../micro-support-card.h"
-
-int uniphier_pro5_init(const struct uniphier_board_data *bd)
-{
- uniphier_sbc_init_savepin(bd);
-
- support_card_reset();
-
- support_card_init();
-
- led_puts("L0");
-
- memconf_init(bd);
-
- led_puts("L1");
-
- uniphier_pro5_early_clk_init(bd);
-
- led_puts("L2");
-
- led_puts("L3");
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_puts("L4");
-
- led_puts("L5");
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../micro-support-card.h"
-
-int uniphier_pxs2_init(const struct uniphier_board_data *bd)
-{
- int ret;
-
- uniphier_sbc_init_savepin(bd);
- uniphier_pxs2_sbc_init(bd);
-
- support_card_reset();
-
- support_card_init();
-
- led_puts("L0");
-
- memconf_init(bd);
- uniphier_pxs2_memconf_init(bd);
-
- led_puts("L1");
-
- uniphier_pxs2_early_clk_init(bd);
-
- led_puts("L2");
-
- led_puts("L3");
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_puts("L4");
-
- ret = uniphier_pxs2_umc_init(bd);
- if (ret)
- return ret;
-
- led_puts("L5");
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2013-2015 Panasonic Corporation
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../micro-support-card.h"
-
-int uniphier_sld3_init(const struct uniphier_board_data *bd)
-{
- uniphier_sld3_bcu_init(bd);
-
- uniphier_sbc_init_admulti(bd);
-
- support_card_reset();
-
- uniphier_sld3_dpll_init(bd);
-
- support_card_init();
-
- led_puts("L0");
-
- memconf_init(bd);
- uniphier_sld3_memconf_init(bd);
-
- led_puts("L1");
-
- uniphier_ld4_early_clk_init(bd);
-
- led_puts("L2");
-
- led_puts("L3");
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_puts("L4");
-
- led_puts("L5");
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2013-2015 Panasonic Corporation
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../micro-support-card.h"
-
-int uniphier_sld8_init(const struct uniphier_board_data *bd)
-{
- uniphier_ld4_bcu_init(bd);
-
- uniphier_sbc_init_savepin(bd);
- uniphier_ld4_sbc_init(bd);
-
- support_card_reset();
-
- uniphier_sld8_dpll_init(bd);
-
- support_card_init();
-
- led_puts("L0");
-
- memconf_init(bd);
-
- led_puts("L1");
-
- uniphier_ld4_early_clk_init(bd);
-
- led_puts("L2");
-
- led_puts("L3");
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_puts("L4");
-
- {
- int res;
-
- res = uniphier_sld8_umc_init(bd);
- if (res < 0) {
- while (1)
- ;
- }
- }
-
- led_puts("L5");
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <spl.h>
-
-#include "../init.h"
-#include "../soc-info.h"
-
-void spl_board_init(void)
-{
- const struct uniphier_board_data *param;
-
-#ifdef CONFIG_DEBUG_UART
- debug_uart_init();
-#endif
-
- param = uniphier_get_board_param();
- if (!param)
- hang();
-
- switch (uniphier_get_soc_type()) {
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
- case SOC_UNIPHIER_SLD3:
- uniphier_sld3_init(param);
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD4)
- case SOC_UNIPHIER_LD4:
- uniphier_ld4_init(param);
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
- case SOC_UNIPHIER_PRO4:
- uniphier_pro4_init(param);
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
- case SOC_UNIPHIER_SLD8:
- uniphier_sld8_init(param);
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
- case SOC_UNIPHIER_PRO5:
- uniphier_pro5_init(param);
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
- case SOC_UNIPHIER_PXS2:
- case SOC_UNIPHIER_LD6B:
- uniphier_pxs2_init(param);
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD11)
- case SOC_UNIPHIER_LD11:
- uniphier_ld11_init(param);
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
- case SOC_UNIPHIER_LD20:
- uniphier_ld20_init(param);
- break;
-#endif
- default:
- break;
- }
-}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "sg-regs.h"
+#include "init.h"
+
+static int __uniphier_memconf_init(const struct uniphier_board_data *bd,
+ int have_ch2, int have_ch2_disable_bit)
+{
+ u32 val = 0;
+ unsigned long size_per_word;
+
+ /* set up ch0 */
+ switch (bd->dram_ch[0].width) {
+ case 16:
+ val |= SG_MEMCONF_CH0_NUM_1;
+ size_per_word = bd->dram_ch[0].size;
+ break;
+ case 32:
+ val |= SG_MEMCONF_CH0_NUM_2;
+ size_per_word = bd->dram_ch[0].size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM ch0 width\n");
+ return -EINVAL;
+ }
+
+ switch (size_per_word) {
+ case SZ_64M:
+ val |= SG_MEMCONF_CH0_SZ_64M;
+ break;
+ case SZ_128M:
+ val |= SG_MEMCONF_CH0_SZ_128M;
+ break;
+ case SZ_256M:
+ val |= SG_MEMCONF_CH0_SZ_256M;
+ break;
+ case SZ_512M:
+ val |= SG_MEMCONF_CH0_SZ_512M;
+ break;
+ case SZ_1G:
+ val |= SG_MEMCONF_CH0_SZ_1G;
+ break;
+ default:
+ pr_err("error: unsupported DRAM ch0 size\n");
+ return -EINVAL;
+ }
+
+ /* set up ch1 */
+ switch (bd->dram_ch[1].width) {
+ case 16:
+ val |= SG_MEMCONF_CH1_NUM_1;
+ size_per_word = bd->dram_ch[1].size;
+ break;
+ case 32:
+ val |= SG_MEMCONF_CH1_NUM_2;
+ size_per_word = bd->dram_ch[1].size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM ch1 width\n");
+ return -EINVAL;
+ }
+
+ switch (size_per_word) {
+ case SZ_64M:
+ val |= SG_MEMCONF_CH1_SZ_64M;
+ break;
+ case SZ_128M:
+ val |= SG_MEMCONF_CH1_SZ_128M;
+ break;
+ case SZ_256M:
+ val |= SG_MEMCONF_CH1_SZ_256M;
+ break;
+ case SZ_512M:
+ val |= SG_MEMCONF_CH1_SZ_512M;
+ break;
+ case SZ_1G:
+ val |= SG_MEMCONF_CH1_SZ_1G;
+ break;
+ default:
+ pr_err("error: unsupported DRAM ch1 size\n");
+ return -EINVAL;
+ }
+
+ /* is sparse mem? */
+ if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
+ val |= SG_MEMCONF_SPARSEMEM;
+
+ if (!have_ch2)
+ goto out;
+
+ if (!bd->dram_ch[2].size) {
+ if (have_ch2_disable_bit)
+ val |= SG_MEMCONF_CH2_DISABLE;
+ goto out;
+ }
+
+ /* set up ch2 */
+ switch (bd->dram_ch[2].width) {
+ case 16:
+ val |= SG_MEMCONF_CH2_NUM_1;
+ size_per_word = bd->dram_ch[2].size;
+ break;
+ case 32:
+ val |= SG_MEMCONF_CH2_NUM_2;
+ size_per_word = bd->dram_ch[2].size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM ch2 width\n");
+ return -EINVAL;
+ }
+
+ switch (size_per_word) {
+ case SZ_64M:
+ val |= SG_MEMCONF_CH2_SZ_64M;
+ break;
+ case SZ_128M:
+ val |= SG_MEMCONF_CH2_SZ_128M;
+ break;
+ case SZ_256M:
+ val |= SG_MEMCONF_CH2_SZ_256M;
+ break;
+ case SZ_512M:
+ val |= SG_MEMCONF_CH2_SZ_512M;
+ break;
+ case SZ_1G:
+ val |= SG_MEMCONF_CH2_SZ_1G;
+ break;
+ default:
+ pr_err("error: unsupported DRAM ch2 size\n");
+ return -EINVAL;
+ }
+
+out:
+ writel(val, SG_MEMCONF);
+
+ return 0;
+}
+
+int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd)
+{
+ return __uniphier_memconf_init(bd, 0, 0);
+}
+
+int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd)
+{
+ return __uniphier_memconf_init(bd, 1, 0);
+}
+
+int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd)
+{
+ return __uniphier_memconf_init(bd, 1, 1);
+}
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += memconf.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += memconf-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += memconf-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += memconf-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += memconf-pxs2.o
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd)
-{
- u32 tmp;
- unsigned long size_per_word;
-
- tmp = readl(SG_MEMCONF);
-
- tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
-
- switch (bd->dram_ch[2].width) {
- case 16:
- tmp |= SG_MEMCONF_CH2_NUM_1;
- size_per_word = bd->dram_ch[2].size;
- break;
- case 32:
- tmp |= SG_MEMCONF_CH2_NUM_2;
- size_per_word = bd->dram_ch[2].size >> 1;
- break;
- default:
- pr_err("error: unsupported DRAM Ch2 width\n");
- return -EINVAL;
- }
-
- /* Set DDR size */
- switch (size_per_word) {
- case SZ_64M:
- tmp |= SG_MEMCONF_CH2_SZ_64M;
- break;
- case SZ_128M:
- tmp |= SG_MEMCONF_CH2_SZ_128M;
- break;
- case SZ_256M:
- tmp |= SG_MEMCONF_CH2_SZ_256M;
- break;
- case SZ_512M:
- tmp |= SG_MEMCONF_CH2_SZ_512M;
- break;
- case SZ_1G:
- tmp |= SG_MEMCONF_CH2_SZ_1G;
- break;
- default:
- pr_err("error: unsupported DRAM Ch2 size\n");
- return -EINVAL;
- }
-
- if (size_per_word)
- tmp &= ~SG_MEMCONF_CH2_DISABLE;
- else
- tmp |= SG_MEMCONF_CH2_DISABLE;
-
- writel(tmp, SG_MEMCONF);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int uniphier_sld3_memconf_init(const struct uniphier_board_data *bd)
-{
- u32 tmp;
- unsigned long size_per_word;
-
- tmp = readl(SG_MEMCONF);
-
- tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
-
- switch (bd->dram_ch[2].width) {
- case 16:
- tmp |= SG_MEMCONF_CH2_NUM_1;
- size_per_word = bd->dram_ch[2].size;
- break;
- case 32:
- tmp |= SG_MEMCONF_CH2_NUM_2;
- size_per_word = bd->dram_ch[2].size >> 1;
- break;
- default:
- pr_err("error: unsupported DRAM Ch2 width\n");
- return -EINVAL;
- }
-
- /* Set DDR size */
- switch (size_per_word) {
- case SZ_64M:
- tmp |= SG_MEMCONF_CH2_SZ_64M;
- break;
- case SZ_128M:
- tmp |= SG_MEMCONF_CH2_SZ_128M;
- break;
- case SZ_256M:
- tmp |= SG_MEMCONF_CH2_SZ_256M;
- break;
- case SZ_512M:
- tmp |= SG_MEMCONF_CH2_SZ_512M;
- break;
- default:
- pr_err("error: unsupported DRAM Ch2 size\n");
- return -EINVAL;
- }
-
- writel(tmp, SG_MEMCONF);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int memconf_init(const struct uniphier_board_data *bd)
-{
- u32 tmp;
- unsigned long size_per_word;
-
- tmp = readl(SG_MEMCONF);
-
- tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);
-
- switch (bd->dram_ch[0].width) {
- case 16:
- tmp |= SG_MEMCONF_CH0_NUM_1;
- size_per_word = bd->dram_ch[0].size;
- break;
- case 32:
- tmp |= SG_MEMCONF_CH0_NUM_2;
- size_per_word = bd->dram_ch[0].size >> 1;
- break;
- default:
- pr_err("error: unsupported DRAM Ch0 width\n");
- return -EINVAL;
- }
-
- /* Set DDR size */
- switch (size_per_word) {
- case SZ_64M:
- tmp |= SG_MEMCONF_CH0_SZ_64M;
- break;
- case SZ_128M:
- tmp |= SG_MEMCONF_CH0_SZ_128M;
- break;
- case SZ_256M:
- tmp |= SG_MEMCONF_CH0_SZ_256M;
- break;
- case SZ_512M:
- tmp |= SG_MEMCONF_CH0_SZ_512M;
- break;
- case SZ_1G:
- tmp |= SG_MEMCONF_CH0_SZ_1G;
- break;
- default:
- pr_err("error: unsupported DRAM Ch0 size\n");
- return -EINVAL;
- }
-
- tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);
-
- switch (bd->dram_ch[1].width) {
- case 16:
- tmp |= SG_MEMCONF_CH1_NUM_1;
- size_per_word = bd->dram_ch[1].size;
- break;
- case 32:
- tmp |= SG_MEMCONF_CH1_NUM_2;
- size_per_word = bd->dram_ch[1].size >> 1;
- break;
- default:
- pr_err("error: unsupported DRAM Ch1 width\n");
- return -EINVAL;
- }
-
- switch (size_per_word) {
- case SZ_64M:
- tmp |= SG_MEMCONF_CH1_SZ_64M;
- break;
- case SZ_128M:
- tmp |= SG_MEMCONF_CH1_SZ_128M;
- break;
- case SZ_256M:
- tmp |= SG_MEMCONF_CH1_SZ_256M;
- break;
- case SZ_512M:
- tmp |= SG_MEMCONF_CH1_SZ_512M;
- break;
- case SZ_1G:
- tmp |= SG_MEMCONF_CH1_SZ_1G;
- break;
- default:
- pr_err("error: unsupported DRAM Ch1 size\n");
- return -EINVAL;
- }
-
- if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
- tmp |= SG_MEMCONF_SPARSEMEM;
- else
- tmp &= ~SG_MEMCONF_SPARSEMEM;
-
- writel(tmp, SG_MEMCONF);
-
- return 0;
-}
* bit[0]: LAN, I2C, LED
* bit[1]: UART
*/
-void support_card_reset_deassert(void)
+static void support_card_reset_deassert(void)
{
writel(0x00010000, MICRO_SUPPORT_CARD_RESET);
}
-void support_card_reset(void)
+static void support_card_reset(void)
{
writel(0x00020003, MICRO_SUPPORT_CARD_RESET);
}
void support_card_init(void)
{
+ support_card_reset();
/*
* After power on, we need to keep the LAN controller in reset state
* for a while. (200 usec)
debug("number of flash banks: %d\n", cfi_flash_num_flash_banks);
}
#else /* CONFIG_SYS_NO_FLASH */
-void detect_num_flash_banks(void)
+static void detect_num_flash_banks(void)
{
};
#endif /* CONFIG_SYS_NO_FLASH */
#define MICRO_SUPPORT_CARD_H
#if defined(CONFIG_MICRO_SUPPORT_CARD)
-void support_card_reset(void);
void support_card_init(void);
void support_card_late_init(void);
void led_puts(const char *s);
#else
-static inline void support_card_reset(void)
-{
-}
-
static inline void support_card_init(void)
{
}
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += sbc-admulti.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD4) += sbc-savepin.o sbc-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += sbc-savepin.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-savepin.o sbc-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-savepin.o sbc-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o sbc-pxs2.o
+obj-y += sbc.o
+
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += sbc-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-ld11.o
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-#include "sbc-regs.h"
-
-#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
-#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
-#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
-
-#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
-#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
-#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
-
-int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd)
-{
- /*
- * Only CS1 is connected to support card.
- * BKSZ[1:0] should be set to "01".
- */
- writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
-
- if (boot_is_swapped()) {
- /*
- * Boot Swap On: boot from external NOR/SRAM
- * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
- *
- * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
- * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
- */
- writel(0x0000bc01, SBBASE0);
- } else {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x40000000-0x41ffffff: mask ROM
- * 0x42000000-0x43efffff: memory bank (31MB)
- * 0x43f00000-0x43ffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- }
-
- return 0;
-}
--- /dev/null
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "sbc-regs.h"
+
+void uniphier_ld11_sbc_init(void)
+{
+ uniphier_sbc_init_savepin();
+
+ /* necessary for ROM boot ?? */
+ /* system bus output enable */
+ writel(0x17, PC0CTRL);
+
+ /* pins for NAND and System Bus are multiplexed */
+ if (spl_boot_device() != BOOT_DEVICE_NAND)
+ uniphier_pin_init("system_bus_grp");
+}
/*
- * Copyright (C) 2011-2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015-2017 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "sbc-regs.h"
-int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd)
+void uniphier_ld4_sbc_init(void)
{
u32 tmp;
+ uniphier_sbc_init_savepin();
+
/* system bus output enable */
tmp = readl(PC0CTRL);
tmp &= 0xfffffcff;
writel(tmp, PC0CTRL);
-
- return 0;
}
/*
- * Copyright (C) 2015-2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2016-2017 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "sbc-regs.h"
-int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd)
+void uniphier_pxs2_sbc_init(void)
{
+ uniphier_sbc_init_savepin();
+
/* necessary for ROM boot ?? */
/* system bus output enable */
writel(0x17, PC0CTRL);
-
- return 0;
}
/*
- * Copyright (C) 2011-2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "sbc-regs.h"
+#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
+#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
+#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
+
+#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
+#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
+#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
+
/* slower but LED works */
#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
-int uniphier_sbc_init_savepin(const struct uniphier_board_data *bd)
+static void __uniphier_sbc_init(int savepin)
{
/*
* Only CS1 is connected to support card.
* BKSZ[1:0] should be set to "01".
*/
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
+ if (savepin) {
+ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
+ writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
+ writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
+ writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
+ } else {
+ writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
+ writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
+ writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
+ }
if (boot_is_swapped()) {
/*
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
}
+}
- return 0;
+void uniphier_sbc_init_admulti(void)
+{
+ __uniphier_sbc_init(0);
+}
+
+void uniphier_sbc_init_savepin(void)
+{
+ __uniphier_sbc_init(1);
}
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <spl.h>
+
+#include "init.h"
+#include "micro-support-card.h"
+#include "soc-info.h"
+
+struct uniphier_spl_initdata {
+ enum uniphier_soc_id soc_id;
+ void (*bcu_init)(const struct uniphier_board_data *bd);
+ void (*early_clk_init)(void);
+ int (*dpll_init)(const struct uniphier_board_data *bd);
+ int (*memconf_init)(const struct uniphier_board_data *bd);
+ void (*dram_clk_init)(void);
+ int (*umc_init)(const struct uniphier_board_data *bd);
+};
+
+static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
+ {
+ .soc_id = SOC_UNIPHIER_SLD3,
+ .bcu_init = uniphier_sld3_bcu_init,
+ .early_clk_init = uniphier_sld3_early_clk_init,
+ .dpll_init = uniphier_sld3_dpll_init,
+ .memconf_init = uniphier_memconf_3ch_no_disbit_init,
+ .dram_clk_init = uniphier_sld3_dram_clk_init,
+ .umc_init = uniphier_sld3_umc_init,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD4)
+ {
+ .soc_id = SOC_UNIPHIER_LD4,
+ .bcu_init = uniphier_ld4_bcu_init,
+ .early_clk_init = uniphier_sld3_early_clk_init,
+ .dpll_init = uniphier_ld4_dpll_init,
+ .memconf_init = uniphier_memconf_2ch_init,
+ .dram_clk_init = uniphier_sld3_dram_clk_init,
+ .umc_init = uniphier_ld4_umc_init,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
+ {
+ .soc_id = SOC_UNIPHIER_PRO4,
+ .early_clk_init = uniphier_sld3_early_clk_init,
+ .dpll_init = uniphier_pro4_dpll_init,
+ .memconf_init = uniphier_memconf_2ch_init,
+ .dram_clk_init = uniphier_sld3_dram_clk_init,
+ .umc_init = uniphier_pro4_umc_init,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
+ {
+ .soc_id = SOC_UNIPHIER_SLD8,
+ .bcu_init = uniphier_ld4_bcu_init,
+ .early_clk_init = uniphier_sld3_early_clk_init,
+ .dpll_init = uniphier_sld8_dpll_init,
+ .memconf_init = uniphier_memconf_2ch_init,
+ .dram_clk_init = uniphier_sld3_dram_clk_init,
+ .umc_init = uniphier_sld8_umc_init,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+ {
+ .soc_id = SOC_UNIPHIER_PRO5,
+ .early_clk_init = uniphier_sld3_early_clk_init,
+ .dpll_init = uniphier_pro5_dpll_init,
+ .memconf_init = uniphier_memconf_2ch_init,
+ .dram_clk_init = uniphier_pro5_dram_clk_init,
+ .umc_init = uniphier_pro5_umc_init,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
+ {
+ .soc_id = SOC_UNIPHIER_PXS2,
+ .early_clk_init = uniphier_sld3_early_clk_init,
+ .dpll_init = uniphier_pxs2_dpll_init,
+ .memconf_init = uniphier_memconf_3ch_init,
+ .dram_clk_init = uniphier_pxs2_dram_clk_init,
+ .umc_init = uniphier_pxs2_umc_init,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
+ {
+ .soc_id = SOC_UNIPHIER_LD6B,
+ .early_clk_init = uniphier_sld3_early_clk_init,
+ .dpll_init = uniphier_pxs2_dpll_init,
+ .memconf_init = uniphier_memconf_3ch_init,
+ .dram_clk_init = uniphier_pxs2_dram_clk_init,
+ .umc_init = uniphier_pxs2_umc_init,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+ {
+ .soc_id = SOC_UNIPHIER_LD11,
+ .early_clk_init = uniphier_ld11_early_clk_init,
+ .dpll_init = uniphier_ld11_dpll_init,
+ .memconf_init = uniphier_memconf_2ch_init,
+ .dram_clk_init = uniphier_ld11_dram_clk_init,
+ .umc_init = uniphier_ld11_umc_init,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+ {
+ .soc_id = SOC_UNIPHIER_LD20,
+ .early_clk_init = uniphier_ld11_early_clk_init,
+ .dpll_init = uniphier_ld20_dpll_init,
+ .memconf_init = uniphier_memconf_3ch_init,
+ .dram_clk_init = uniphier_ld20_dram_clk_init,
+ .umc_init = uniphier_ld20_umc_init,
+ },
+#endif
+};
+
+static const struct uniphier_spl_initdata *uniphier_get_spl_initdata(
+ enum uniphier_soc_id soc_id)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(uniphier_spl_initdata); i++) {
+ if (uniphier_spl_initdata[i].soc_id == soc_id)
+ return &uniphier_spl_initdata[i];
+ }
+
+ return NULL;
+}
+
+void spl_board_init(void)
+{
+ const struct uniphier_board_data *bd;
+ const struct uniphier_spl_initdata *initdata;
+ enum uniphier_soc_id soc_id;
+ int ret;
+
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+
+ bd = uniphier_get_board_param();
+ if (!bd)
+ hang();
+
+ soc_id = uniphier_get_soc_type();
+ initdata = uniphier_get_spl_initdata(soc_id);
+ if (!initdata)
+ hang();
+
+ if (initdata->bcu_init)
+ initdata->bcu_init(bd);
+
+
+ initdata->early_clk_init();
+
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ ret = initdata->dpll_init(bd);
+ if (ret) {
+ pr_err("failed to init DPLL\n");
+ hang();
+ }
+
+ ret = initdata->memconf_init(bd);
+ if (ret) {
+ pr_err("failed to init MEMCONF\n");
+ hang();
+ }
+
+ initdata->dram_clk_init();
+
+ ret = initdata->umc_init(bd);
+ if (ret) {
+ pr_err("failed to init DRAM\n");
+ hang();
+ }
+}
}
#endif /* CONFIG_CMD_NET */
-#if defined(CONFIG_CF_QSPI)
-
-/* Configure PIOs for SIN, SOUT, and SCK */
-void cfspi_port_conf(void)
-{
- mbar_writeByte(MCF_GPIO_PAR_QSPI,
- MCF_GPIO_PAR_QSPI_SIN_SIN |
- MCF_GPIO_PAR_QSPI_SOUT_SOUT |
- MCF_GPIO_PAR_QSPI_SCK_SCK);
-}
-#endif /* CONFIG_CF_QSPI */
-
#endif /* CONFIG_M5271 */
#if defined(CONFIG_M5272)
*/
#ifdef __ASSEMBLY__
-#define _AC(X,Y) X
#define _AT(T,X) X
#else
-#define __AC(X,Y) (X##Y)
-#define _AC(X,Y) __AC(X,Y)
#define _AT(T,X) ((T)(X))
#endif
config MPC83xx
bool "MPC83xx"
select CREATE_ARCH_SYMLINK
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
config MPC85xx
bool "MPC85xx"
select CREATE_ARCH_SYMLINK
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_BE
config MPC86xx
bool "MPC86xx"
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_BE
config 8xx
bool "MPC8xx"
config TARGET_MPC8308RDB
bool "Support MPC8308RDB"
+ select SYS_FSL_ERRATUM_ESDHC111
config TARGET_MPC8313ERDB
bool "Support MPC8313ERDB"
config TARGET_MPC8349EMDS
bool "Support MPC8349EMDS"
+ select SYS_FSL_DDR
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_DDR_BE
config TARGET_MPC8349ITX
bool "Support MPC8349ITX"
config TARGET_HRCON
bool "Support hrcon"
+ select SYS_FSL_ERRATUM_ESDHC111
config TARGET_STRIDER
bool "Support strider"
+ select SYS_FSL_ERRATUM_ESDHC111
endchoice
config TARGET_MPC8536DS
bool "Support MPC8536DS"
select ARCH_MPC8536
+# Use DDR3 controller with DDR2 DIMMs on this board
+ select SYS_FSL_DDRC_GEN3
config TARGET_MPC8540ADS
bool "Support MPC8540ADS"
config TARGET_MPC8572DS
bool "Support MPC8572DS"
select ARCH_MPC8572
+# Use DDR3 controller with DDR2 DIMMs on this board
+ select SYS_FSL_DDRC_GEN3
config TARGET_P1010RDB_PA
bool "Support P1010RDB_PA"
config TARGET_XPEDITE537X
bool "Support xpedite537x"
select ARCH_MPC8572
+# Use DDR3 controller with DDR2 DIMMs on this board
+ select SYS_FSL_DDRC_GEN3
config TARGET_XPEDITE550X
bool "Support xpedite550x"
config ARCH_B4420
bool
+ select E500MC
+ select E6500
select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A005871
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006384
+ select SYS_FSL_ERRATUM_A006475
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007075
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
config ARCH_B4860
bool
+ select E500MC
+ select E6500
select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A005871
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006384
+ select SYS_FSL_ERRATUM_A006475
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007075
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
config ARCH_BSC9131
bool
select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_BSC9132
bool
select FSL_LAW
+ select SYS_FSL_DDR_VER_46
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_A005434
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_IFC_A002769
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_C29X
bool
select FSL_LAW
+ select SYS_FSL_DDR_VER_46
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_6
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8536
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8540
bool
select FSL_LAW
+ select SYS_FSL_HAS_DDR1
config ARCH_MPC8541
bool
select FSL_LAW
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8544
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8548
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_NMG_DDR120
+ select SYS_FSL_ERRATUM_NMG_LBC103
+ select SYS_FSL_ERRATUM_NMG_ETSEC129
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8555
bool
select FSL_LAW
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8560
bool
select FSL_LAW
+ select SYS_FSL_HAS_DDR1
config ARCH_MPC8568
bool
select FSL_LAW
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8569
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8572
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_DDR_115
+ select SYS_FSL_ERRATUM_DDR111_DDR134
+ select SYS_FSL_HAS_DDR2
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1010
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_A007075
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_IFC_A002769
+ select SYS_FSL_ERRATUM_P1010_A003549
+ select SYS_FSL_ERRATUM_SEC_A003571
+ select SYS_FSL_ERRATUM_IFC_A003399
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1011
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1020
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1021
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1022
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_SATA_A001
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1023
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_P1024
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1025
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2020
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004477
+ select SYS_FSL_ERRATUM_A004508
+ select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_ESDHC_A001
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_2
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2041
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A004849
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_CPU_A003999
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_NMG_CPU_A011
+ select SYS_FSL_ERRATUM_SRIO_A004034
+ select SYS_FSL_ERRATUM_USB14
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_P3041
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A004849
+ select SYS_FSL_ERRATUM_A005812
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_CPU_A003999
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_NMG_CPU_A011
+ select SYS_FSL_ERRATUM_SRIO_A004034
+ select SYS_FSL_ERRATUM_USB14
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_P4080
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A004580
+ select SYS_FSL_ERRATUM_A004849
+ select SYS_FSL_ERRATUM_A005812
+ select SYS_FSL_ERRATUM_A007075
+ select SYS_FSL_ERRATUM_CPC_A002
+ select SYS_FSL_ERRATUM_CPC_A003
+ select SYS_FSL_ERRATUM_CPU_A003999
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ELBC_A001
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_ESDHC13
+ select SYS_FSL_ERRATUM_ESDHC135
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_NMG_CPU_A011
+ select SYS_FSL_ERRATUM_SRIO_A004034
+ select SYS_P4080_ERRATUM_CPU22
+ select SYS_P4080_ERRATUM_PCIE_A003
+ select SYS_P4080_ERRATUM_SERDES8
+ select SYS_P4080_ERRATUM_SERDES9
+ select SYS_P4080_ERRATUM_SERDES_A001
+ select SYS_P4080_ERRATUM_SERDES_A005
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_P5020
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_I2C_A004447
+ select SYS_FSL_ERRATUM_SRIO_A004034
+ select SYS_FSL_ERRATUM_USB14
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
config ARCH_P5040
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_44
+ select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A004699
+ select SYS_FSL_ERRATUM_A005812
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_DDR_A003
+ select SYS_FSL_ERRATUM_DDR_A003474
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_USB14
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
config ARCH_QEMU_E500
bool
config ARCH_T1023
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_5
config ARCH_T1024
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_5
config ARCH_T1040
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008044
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_5
config ARCH_T1042
bool
+ select E500MC
select FSL_LAW
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008044
+ select SYS_FSL_ERRATUM_A008378
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_5
config ARCH_T2080
bool
+ select E500MC
+ select E6500
select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
config ARCH_T2081
bool
+ select E500MC
+ select E6500
select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007212
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
config ARCH_T4160
bool
+ select E500MC
+ select E6500
select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A004468
+ select SYS_FSL_ERRATUM_A005871
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007798
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
config ARCH_T4240
bool
+ select E500MC
+ select E6500
select FSL_LAW
+ select SYS_FSL_DDR_VER_47
+ select SYS_FSL_ERRATUM_A004468
+ select SYS_FSL_ERRATUM_A005871
+ select SYS_FSL_ERRATUM_A006261
+ select SYS_FSL_ERRATUM_A006379
+ select SYS_FSL_ERRATUM_A006593
+ select SYS_FSL_ERRATUM_A007186
+ select SYS_FSL_ERRATUM_A007798
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_SEC_BE
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_PPC64
+
+config BOOKE
+ bool
+ default y
+
+config E500
+ bool
+ default y
+ help
+ Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
+
+config E500MC
+ bool
+ help
+ Enble PowerPC E500MC core
+
+config E6500
+ bool
+ help
+ Enable PowerPC E6500 core
config FSL_LAW
bool
ARCH_P1025 || \
ARCH_P2020 || \
ARCH_P5020 || \
- ARCH_T1020 || \
- ARCH_T1022 || \
ARCH_T1023 || \
ARCH_T1024
default 1
ARCH_P4080 || \
ARCH_P5020 || \
ARCH_P5040 || \
- ARCH_T1013 || \
- ARCH_T1014 || \
- ARCH_T1020 || \
- ARCH_T1022 || \
ARCH_T1023 || \
ARCH_T1024 || \
ARCH_T1040 || \
if changed by pre-boot regime. The value here must match
the current value in SoC. If not sure, do not change.
+config SYS_FSL_ERRATUM_A004468
+ bool
+
+config SYS_FSL_ERRATUM_A004477
+ bool
+
+config SYS_FSL_ERRATUM_A004508
+ bool
+
+config SYS_FSL_ERRATUM_A004580
+ bool
+
+config SYS_FSL_ERRATUM_A004699
+ bool
+
+config SYS_FSL_ERRATUM_A004849
+ bool
+
+config SYS_FSL_ERRATUM_A004510
+ bool
+
+config SYS_FSL_ERRATUM_A004510_SVR_REV
+ hex
+ depends on SYS_FSL_ERRATUM_A004510
+ default 0x20 if ARCH_P4080
+ default 0x10
+
+config SYS_FSL_ERRATUM_A004510_SVR_REV2
+ hex
+ depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
+ default 0x11
+
+config SYS_FSL_ERRATUM_A005125
+ bool
+
+config SYS_FSL_ERRATUM_A005434
+ bool
+
+config SYS_FSL_ERRATUM_A005812
+ bool
+
+config SYS_FSL_ERRATUM_A005871
+ bool
+
+config SYS_FSL_ERRATUM_A006261
+ bool
+
+config SYS_FSL_ERRATUM_A006379
+ bool
+
+config SYS_FSL_ERRATUM_A006384
+ bool
+
+config SYS_FSL_ERRATUM_A006475
+ bool
+
+config SYS_FSL_ERRATUM_A006593
+ bool
+
+config SYS_FSL_ERRATUM_A007075
+ bool
+
+config SYS_FSL_ERRATUM_A007186
+ bool
+
+config SYS_FSL_ERRATUM_A007212
+ bool
+
+config SYS_FSL_ERRATUM_A007798
+ bool
+
+config SYS_FSL_ERRATUM_A008044
+ bool
+
+config SYS_FSL_ERRATUM_CPC_A002
+ bool
+
+config SYS_FSL_ERRATUM_CPC_A003
+ bool
+
+config SYS_FSL_ERRATUM_CPU_A003999
+ bool
+
+config SYS_FSL_ERRATUM_ELBC_A001
+ bool
+
+config SYS_FSL_ERRATUM_I2C_A004447
+ bool
+
+config SYS_FSL_A004447_SVR_REV
+ hex
+ depends on SYS_FSL_ERRATUM_I2C_A004447
+ default 0x00 if ARCH_MPC8548
+ default 0x10 if ARCH_P1010
+ default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
+ default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
+
+config SYS_FSL_ERRATUM_IFC_A002769
+ bool
+
+config SYS_FSL_ERRATUM_IFC_A003399
+ bool
+
+config SYS_FSL_ERRATUM_NMG_CPU_A011
+ bool
+
+config SYS_FSL_ERRATUM_NMG_ETSEC129
+ bool
+
+config SYS_FSL_ERRATUM_NMG_LBC103
+ bool
+
+config SYS_FSL_ERRATUM_P1010_A003549
+ bool
+
+config SYS_FSL_ERRATUM_SATA_A001
+ bool
+
+config SYS_FSL_ERRATUM_SEC_A003571
+ bool
+
+config SYS_FSL_ERRATUM_SRIO_A004034
+ bool
+
+config SYS_FSL_ERRATUM_USB14
+ bool
+
+config SYS_P4080_ERRATUM_CPU22
+ bool
+
+config SYS_P4080_ERRATUM_PCIE_A003
+ bool
+
+config SYS_P4080_ERRATUM_SERDES8
+ bool
+
+config SYS_P4080_ERRATUM_SERDES9
+ bool
+
+config SYS_P4080_ERRATUM_SERDES_A001
+ bool
+
+config SYS_P4080_ERRATUM_SERDES_A005
+ bool
+
+config SYS_FSL_QORIQ_CHASSIS1
+ bool
+
+config SYS_FSL_QORIQ_CHASSIS2
+ bool
+
config SYS_FSL_NUM_LAWS
int "Number of local access windows"
depends on FSL_LAW
ARCH_T2081 || \
ARCH_T4160 || \
ARCH_T4240
- default 16 if ARCH_T1013 || \
- ARCH_T1014 || \
- ARCH_T1020 || \
- ARCH_T1022 || \
- ARCH_T1023 || \
+ default 16 if ARCH_T1023 || \
ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042
Number of local access windows. This is fixed per SoC.
If not sure, do not change.
+config SYS_FSL_THREADS_PER_CORE
+ int
+ default 2 if E6500
+ default 1
+
+config SYS_NUM_TLBCAMS
+ int "Number of TLB CAM entries"
+ default 64 if E500MC
+ default 16
+ help
+ Number of TLB CAM entries for Book-E chips. 64 for E500MC,
+ 16 for other E500 SoCs.
+
+config SYS_PPC64
+ bool
+
+config SYS_PPC_E500_USE_DEBUG_TLB
+ bool
+
+config SYS_PPC_E500_DEBUG_TLB
+ int "Temporary TLB entry for external debugger"
+ depends on SYS_PPC_E500_USE_DEBUG_TLB
+ default 0 if ARCH_MPC8544 || ARCH_MPC8548
+ default 1 if ARCH_MPC8536
+ default 2 if ARCH_MPC8572 || \
+ ARCH_P1011 || \
+ ARCH_P1020 || \
+ ARCH_P1021 || \
+ ARCH_P1022 || \
+ ARCH_P1024 || \
+ ARCH_P1025 || \
+ ARCH_P2020
+ default 3 if ARCH_P1010 || \
+ ARCH_BSC9132 || \
+ ARCH_C29X
+ help
+ Select a temporary TLB entry to be used during boot to work
+ around limitations in e500v1 and e500v2 external debugger
+ support. This reduces the portions of the boot code where
+ breakpoints and single stepping do not work. The value of this
+ symbol should be set to the TLB1 entry to be used for this
+ purpose. If unsure, do not change.
+
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
obj-$(CONFIG_ARCH_T1040) += t1040_ids.o
obj-$(CONFIG_ARCH_T1042) += t1040_ids.o
-obj-$(CONFIG_PPC_T1020) += t1040_ids.o
-obj-$(CONFIG_PPC_T1022) += t1040_ids.o
obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
obj-$(CONFIG_ARCH_T1040) += t1040_serdes.o
obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o
-obj-$(CONFIG_PPC_T1020) += t1040_serdes.o
-obj-$(CONFIG_PPC_T1022) += t1040_serdes.o
obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
#endif
__maybe_unused u32 svr = get_svr();
-#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
+#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
if (IS_SVR_REV(svr, 1, 0)) {
switch (SVR_SOC_VER(svr)) {
case SVR_P1013:
int i, j, k, m;
u8 *p_8;
u32 *p_32;
- struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+ struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
generic_spd_eeprom_t
- spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
+ spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
puts("SPD data of all dimms (zero value is omitted)...\n");
puts("Byte (hex) ");
k = 1;
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
printf("Dimm%d ", k++);
}
for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
m = 0;
printf("%3d (0x%02x) ", k, k);
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
p_8 = (u8 *) &spd[i][j];
if (p_8[k]) {
puts("\r");
}
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
switch (i) {
case 0:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
printf("DDR registers dump for all controllers "
"(zero value is omitted)...\n");
puts("Offset (hex) ");
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
puts("\n");
for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
m = 0;
printf("%6d (0x%04x)", k * 4, k * 4);
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
p_32 = (u32 *) ddr[i];
if (p_32[k]) {
printf(" 0x%08x", p_32[k]);
u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
#endif
ddr_pll_ratio >>= 1;
setbits_be32(plldadcr1, 0x02000001);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
setbits_be32(plldadcr2, 0x02000001);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
setbits_be32(plldadcr3, 0x02000001);
#endif
#endif
setbits_be32(dpdovrcr4, 0xe0000000);
out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
#endif
#endif
udelay(100);
clrbits_be32(plldadcr1, 0x02000001);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
clrbits_be32(plldadcr2, 0x02000001);
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
clrbits_be32(plldadcr3, 0x02000001);
#endif
#endif
#endif
#endif
-#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
+#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
/*
* For P1022/1013 Rev1.0 silicon, after power on SATA host
* controller is configured in legacy mode instead of the
config ARCH_MPC8610
bool
select FSL_LAW
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_DDR2
config ARCH_MPC8641
bool
select FSL_LAW
+ select SYS_FSL_HAS_DDR1
+ select SYS_FSL_HAS_DDR2
config FSL_LAW
bool
#ifdef CONFIG_MPC85xx
#include <asm/config_mpc85xx.h>
-#define CONFIG_SYS_FSL_DDR
#endif
#ifdef CONFIG_MPC86xx
#include <asm/config_mpc86xx.h>
-#define CONFIG_SYS_FSL_DDR
#endif
#ifdef CONFIG_MPC83xx
-#define CONFIG_SYS_FSL_DDR
#endif
#ifndef HWCONFIG_BUFFER_SIZE
#endif
#endif
-/*
- * SEC (crypto unit) major compatible version determination
- */
-#if defined(CONFIG_MPC83xx)
-#define CONFIG_SYS_FSL_SEC_BE
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#endif
-
/* Since so many PPC SOCs have a semi-common LBC, define this here */
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
defined(CONFIG_MPC83xx)
#define CONFIG_PPC_SPINTABLE_COMPATIBLE
#include <fsl_ddrc_version.h>
-#define CONFIG_SYS_FSL_DDR_BE
/* IP endianness */
#define CONFIG_SYS_FSL_IFC_BE
-#define CONFIG_SYS_FSL_SEC_BE
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SEC_MON_BE
-/* Number of TLB CAM entries we have on FSL Book-E chips */
-#if defined(CONFIG_E500MC)
-#define CONFIG_SYS_NUM_TLBCAMS 64
-#elif defined(CONFIG_E500)
-#define CONFIG_SYS_NUM_TLBCAMS 16
-#endif
-
-#if defined(CONFIG_ARCH_MPC8536)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_ARCH_MPC8540)
-#define CONFIG_SYS_FSL_DDRC_GEN1
-
-#elif defined(CONFIG_ARCH_MPC8541)
-#define CONFIG_SYS_FSL_DDRC_GEN1
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-
-#elif defined(CONFIG_ARCH_MPC8544)
-#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_ARCH_MPC8548)
-#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
-#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
-#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+#if defined(CONFIG_ARCH_MPC8548)
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
-
-#elif defined(CONFIG_ARCH_MPC8555)
-#define CONFIG_SYS_FSL_DDRC_GEN1
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-
-#elif defined(CONFIG_ARCH_MPC8560)
-#define CONFIG_SYS_FSL_DDRC_GEN1
#elif defined(CONFIG_ARCH_MPC8568)
-#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x10000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_MPC8569)
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x20000UL
#define MAX_QE_RISC 4
#define QE_NUM_OF_SNUM 46
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_ARCH_MPC8572)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_DDR_115
-#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
-#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
-#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_FSL_ERRATUM_A004477
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
#define CONFIG_ESDHC_HC_BLK_ADDR
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_ARCH_P1011)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P1020)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
#elif defined(CONFIG_ARCH_P1021)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1022)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_FSL_SATA_ERRATUM_A001
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_A004477
#elif defined(CONFIG_ARCH_P1023)
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_QMAN_NUM_PORTALS 3
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
/* P1024 is lower end variant of P1020 */
#elif defined(CONFIG_ARCH_P1024)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_ARCH_P1025)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
-#define CONFIG_SYS_FSL_ERRATUM_USB14
-#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
-#define CONFIG_SYS_FSL_ERRATUM_A004849
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#elif defined(CONFIG_ARCH_P3041)
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
-#define CONFIG_SYS_FSL_ERRATUM_USB14
-#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
-#define CONFIG_SYS_FSL_ERRATUM_A004849
-#define CONFIG_SYS_FSL_ERRATUM_A005812
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM2_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
-#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
-#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
-#define CONFIG_SYS_P4080_ERRATUM_CPU22
-#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
-#define CONFIG_SYS_P4080_ERRATUM_SERDES8
-#define CONFIG_SYS_P4080_ERRATUM_SERDES9
-#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
-#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
-#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
-#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
-#define CONFIG_SYS_FSL_ERRATUM_A004849
-#define CONFIG_SYS_FSL_ERRATUM_A004580
-#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
-#define CONFIG_SYS_FSL_ERRATUM_A005812
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A007075
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
-#define CONFIG_SYS_PPC64 /* 64-bit core */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_USB14
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
-#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_ERRATUM_A006261
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_ARCH_P5040)
-#define CONFIG_SYS_PPC64
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_USB14
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
-#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_ERRATUM_A004699
-#define CONFIG_SYS_FSL_ERRATUM_A004510
-#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
-#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-#define CONFIG_SYS_FSL_ERRATUM_A005812
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_ARCH_BSC9132)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_NUM_DDR_CONTROLLERS 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-#define CONFIG_SYS_FSL_ERRATUM_A005434
-#define CONFIG_SYS_FSL_ERRATUM_A004477
-#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
-#define CONFIG_E6500
-#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#ifdef CONFIG_ARCH_T4240
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 3
-#define CONFIG_SYS_FSL_ERRATUM_A006261
#else
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#if defined(CONFIG_ARCH_T4160)
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#endif
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_SRDS_3
#define CONFIG_SYS_FSL_SRDS_4
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_PME_CLK 0
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM1_CLK 3
#define CONFIG_SYS_FSL_SRIO_LIODN
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_A004468
-#define CONFIG_SYS_FSL_ERRATUM_A005871
-#define CONFIG_SYS_FSL_ERRATUM_A006379
-#define CONFIG_SYS_FSL_ERRATUM_A007186
-#define CONFIG_SYS_FSL_ERRATUM_A006593
-#define CONFIG_SYS_FSL_ERRATUM_A007798
-#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_PCI_VER_3_X
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
-#define CONFIG_E6500
-#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
#define CONFIG_SYS_MAPLE
#define CONFIG_SYS_CPRI
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_CPRI_CLK 3
#define CONFIG_SYS_ULB_CLK 4
#define CONFIG_SYS_ETVPE_CLK 1
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_ERRATUM_A005871
-#define CONFIG_SYS_FSL_ERRATUM_A006379
-#define CONFIG_SYS_FSL_ERRATUM_A007186
-#define CONFIG_SYS_FSL_ERRATUM_A006593
-#define CONFIG_SYS_FSL_ERRATUM_A007075
-#define CONFIG_SYS_FSL_ERRATUM_A006475
-#define CONFIG_SYS_FSL_ERRATUM_A006384
-#define CONFIG_SYS_FSL_ERRATUM_A007212
-#define CONFIG_SYS_FSL_ERRATUM_A004477
-#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_SFP_VER_3_0
#ifdef CONFIG_ARCH_B4860
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#endif
-#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
-defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
#define CONFIG_E5500
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_PME_PLAT_CLK_DIV 2
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_SYS_FSL_ERRATUM_A008044
#define CONFIG_SYS_FMAN_V3
#define CONFIG_FM_PLAT_CLK_DIV 1
#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0
-#define CONFIG_SYS_FSL_ERRATUM_A008378
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009942
-#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\
-defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
#define CONFIG_E5500
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#define CONFIG_SYS_FMAN_V3
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#endif
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0
-#define CONFIG_SYS_FSL_ERRATUM_A008378
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009942
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
-#define CONFIG_E6500
-#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_QMAN_V3
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FM1_10GEC 2
#endif
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_PME_PLAT_CLK_DIV 1
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
per rcw field value */
#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_A006593
-#define CONFIG_SYS_FSL_ERRATUM_A007186
-#define CONFIG_SYS_FSL_ERRATUM_A006379
-#define CONFIG_SYS_FSL_ERRATUM_A009942
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2_1
-#define CONFIG_SYS_FSL_SEC_COMPAT 6
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
-#elif defined(CONFIG_ARCH_QEMU_E500)
-
-#else
-#error Processor type not defined for this platform
-#endif
-
-#ifdef CONFIG_E6500
-#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
-#else
-#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
-#endif
-
-#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
- !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
- !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
- !defined(CONFIG_SYS_FSL_DDRC_GEN4)
-#define CONFIG_SYS_FSL_DDRC_GEN3
#endif
#if !defined(CONFIG_ARCH_C29X)
#ifndef _ASM_MPC86xx_CONFIG_H_
#define _ASM_MPC86xx_CONFIG_H_
-#define CONFIG_SYS_FSL_DDR_86XX
-
#endif /* _ASM_MPC85xx_CONFIG_H_ */
defined(CONFIG_TARGET_B4420QDS) || \
defined(CONFIG_TARGET_T4160QDS) || \
defined(CONFIG_TARGET_T4240QDS) || \
- defined(CONFIG_T2080QDS) || \
- defined(CONFIG_T2080RDB) || \
- defined(CONFIG_T1040QDS) || \
- defined(CONFIG_T104xD4QDS) || \
+ defined(CONFIG_TARGET_T2080QDS) || \
+ defined(CONFIG_TARGET_T2080RDB) || \
+ defined(CONFIG_TARGET_T1040QDS) || \
defined(CONFIG_TARGET_T1040RDB) || \
defined(CONFIG_TARGET_T1040D4RDB) || \
defined(CONFIG_TARGET_T1042RDB) || \
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
-#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
-defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
-#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) || \
- defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
int board_init(void)
{
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME;
-
/* address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
mx27_fec_init_pins();
#endif
-#ifdef CONFIG_MXC_MMC
+#ifdef CONFIG_MMC_MXC
mx27_sd2_init_pins();
imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16));
gpio_request(PC_PWRON, "pc_pwron");
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
- /* board id for linux */
- gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO_800EVA;
/* adress of boot parameters */
gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
int board_init(void)
{
- /* arch number of AT91SAM9X5EK-Board */
- gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
-
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
}
#endif
-#ifdef CONFIG_TEGRA_MMC
+#ifdef CONFIG_MMC_SDHCI_TEGRA
/*
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
#include <common.h>
#include <spl.h>
+#include <asm/gpio.h>
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = BOOT_DEVICE_MMC2;
spl_boot_list[1] = BOOT_DEVICE_MMC1;
}
+
+#define GPIO7A3_HUB_RST 227
+
+int rk_board_late_init(void)
+{
+ int ret;
+
+ ret = gpio_request(GPIO7A3_HUB_RST, "hub_rst");
+ if (ret)
+ return ret;
+ ret = gpio_direction_output(GPIO7A3_HUB_RST, 1);
+ if (ret)
+ return ret;
+
+ return 0;
+}
gd->ram_size = dram_init_banksize_int(1);
return 0;
}
-
-
-#ifdef CONFIG_EP93XX_SPI
-#include <spi.h>
-
-/*
- * EGIO0-EGIPO7 -> port A
- * EGIO8-EGIP15 -> port B
- */
-
-static void ep93xx_set_epgio(unsigned num)
-{
- struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
- if (num < 8)
- writel(readl(®s->padr) | (1<<num), ®s->padr);
- else
- writel(readl(®s->pbdr) | (1<<(num-8)), ®s->pbdr);
-}
-
-static void ep93xx_clear_epgio(unsigned num)
-{
- struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
- if (num < 8)
- writel(readl(®s->padr) & (~(1<<num)), ®s->padr);
- else
- writel(readl(®s->pbdr) & (~(1<<(num-8))), ®s->pbdr);
-}
-
-static void ep93xx_dir_epgio_out(unsigned num)
-{
- struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
- if (num < 8)
- writel(readl(®s->paddr) | (1<<num), ®s->paddr);
- else
- writel(readl(®s->pbddr) | (1<<(num-8)), ®s->pbddr);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- if (bus == 0 && cs < 16)
- return 1;
-
- return 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- ep93xx_clear_epgio(slave->cs);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- ep93xx_set_epgio(slave->cs);
-}
-
-#ifdef CONFIG_MMC_SPI
-#include <mmc.h>
-
-#ifndef CONFIG_MMC_SPI_CS_EPGIO
-# define CONFIG_MMC_SPI_CS_EPGIO 4
-#endif
-
-#ifndef CONFIG_MMC_SPI_SPEED
-# define CONFIG_MMC_SPI_SPEED 25000000
-#endif
-
-#ifndef CONFIG_MMC_SPI_MODE
-# define CONFIG_MMC_SPI_MODE SPI_MODE_0
-#endif
-
-int board_mmc_init(bd_t *bis)
-{
- struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
-
- ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO);
- ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO);
-
-#ifdef CONFIG_MMC_SPI_POWER_EGPIO
- ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO);
- ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO);
-#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO)
- ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO);
- ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO);
-#endif
- struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO,
- CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE);
-
- if (!mmc) {
- printf("Failed to create MMC Device\n");
- return 1;
- }
- mmc_init(mmc);
- return 0;
-}
-
-
-#endif /* CONFIG_MMC_SPI */
-#endif /* CONFIG_EP93XX_SPI */
#include <asm/arch/pinmux.h>
#include <asm/gpio.h>
-#ifdef CONFIG_TEGRA_MMC
+#ifdef CONFIG_MMC_SDHCI_TEGRA
/*
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
#include <linux/errno.h>
#include <hwconfig.h>
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
#include <mmc.h>
#include <asm/arch/sdmmc_defs.h>
#endif
return 0;
}
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
static struct davinci_mmc mmc_sd0 = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
.host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
/* GP0[11] is required for NOR to work on Rev 3 EVMs */
{ pinmux(0), 8, 4 }, /* GP0[11] */
#endif
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
/* GP0[11] is required for SD to work on Rev 3 EVMs */
{ pinmux(0), 8, 4 }, /* GP0[11] */
#endif
PINMUX_ITEM(emifa_pins_nor),
#endif
PINMUX_ITEM(gpio_pins),
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
PINMUX_ITEM(mmc0_pins),
#endif
};
{ DAVINCI_LPSC_EMAC }, /* image download */
{ DAVINCI_LPSC_UART2 }, /* console */
{ DAVINCI_LPSC_GPIO },
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
{ DAVINCI_LPSC_MMC_SD },
#endif
};
writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
#endif
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
/* Set the GPIO direction as output */
clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/davinci_misc.h>
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
#include <mmc.h>
#include <asm/arch/sdmmc_defs.h>
#endif
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
/* MMC0 pin muxer settings */
const struct pinmux_config mmc0_pins[] = {
/* GP0[11] is required for SD to work on Rev 3 EVMs */
{ DAVINCI_LPSC_EMAC }, /* image download */
{ DAVINCI_LPSC_UART2 }, /* console */
{ DAVINCI_LPSC_GPIO },
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
{ DAVINCI_LPSC_MMC_SD },
#endif
};
irq_init();
#endif
- /* arch number of the board */
- gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
-
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
#endif
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
return 1;
#endif
return 0;
}
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
static struct davinci_mmc mmc_sd0 = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
.host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
int board_init(void)
{
- /* arch number of the board */
- gd->bd->bi_arch_number = MACH_TYPE_EA20;
-
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
rank_density, ctlr_density);
- for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+ for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
* Simple linear assignment if memory
* controllers are not interleaved.
*/
- for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+ for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
total_ctlr_mem = 0;
pinfo->common_timing_params[i].base_address =
current_mem_base;
* may return back in case of non-fatal failures.
*/
- debug("image entry point: 0x%X\n", spl_image->entry_point);
+ debug("image entry point: 0x%lX\n", spl_image->entry_point);
image_entry();
}
#endif /* ifdef CONFIG_SPL_FRAMEWORK */
* Fixed sdram init -- doesn't use serial presence detect.
*/
extern fixed_ddr_parm_t fixed_ddr_parm_0[];
-#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
extern fixed_ddr_parm_t fixed_ddr_parm_1[];
#endif
ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
memcpy(&ddr_cfg_regs,
fixed_ddr_parm_1[i].ddr_settings,
sizeof(ddr_cfg_regs));
return 0;
}
} else {
-#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
/* We require both controllers have identical DIMMs */
lawbar1_target_id = LAW_TRGT_IF_DDR_1;
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
F: board/freescale/mx6ullevk/
F: include/configs/mx6ullevk.h
F: configs/mx6ull_14x14_evk_defconfig
+F: configs/mx6ull_14x14_evk_plugin_defconfig
obj-y += spl.o
else
obj-y += t102xrdb.o
-obj-$(CONFIG_T1024RDB) += cpld.o
+obj-$(CONFIG_TARGET_T1024RDB) += cpld.o
obj-y += eth_t102xrdb.o
obj-$(CONFIG_PCI) += pci.o
endif
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
#endif
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
popts->wrlvl_ctl_2 = 0x07070606;
popts->half_strength_driver_enable = 1;
popts->cpo_sample = 0x43;
-#elif defined(CONFIG_T1024RDB)
+#elif defined(CONFIG_TARGET_T1024RDB)
/* optimize cpo for erratum A-009942 */
popts->cpo_sample = 0x52;
#endif
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) {
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
case 0x95:
/* set the on-board RGMII2 PHY */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
case 0x135:
/* set the on-board 2.5G SGMII AQR105 PHY */
fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
/* set the on-board 1G SGMII RTL8211F PHY */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
#endif
fm_info_set_mdio(i, dev);
break;
case PHY_INTERFACE_MODE_SGMII:
-#if defined(CONFIG_T1023RDB)
+#if defined(CONFIG_TARGET_T1023RDB)
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-#elif defined(CONFIG_T1024RDB)
+#elif defined(CONFIG_TARGET_T1024RDB)
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
#endif
fm_info_set_mdio(i, dev);
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
(fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
(port == FM1_DTSEC3)) {
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t102xrdb.h"
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
#include "cpld.h"
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#include <i2c.h>
#include <mmc.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
enum {
GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
GPIO1_EMMC_SEL,
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
printf("Board: %sRDB, ", cpu->name);
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
CPLD_READ(hw_ver), CPLD_READ(sw_ver));
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
#endif
printf("boot from ");
puts("SD/MMC\n");
#elif CONFIG_SPIFLASH
puts("SPI\n");
-#elif defined(CONFIG_T1024RDB)
+#elif defined(CONFIG_TARGET_T1024RDB)
u8 reg;
reg = CPLD_READ(flash_csr);
reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
printf("NOR vBank%d\n", reg);
}
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#ifdef CONFIG_NAND
puts("NAND\n");
#else
return 0;
}
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
static void board_mux_lane(void)
{
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
board_mux_lane();
#endif
fdt_fixup_board_enet(blob);
#endif
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
fdt_enable_nor(blob);
#endif
return 0;
}
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
/* Enable NOR flash for RevC */
static void fdt_enable_nor(void *blob)
{
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
static u32 t1023rdb_ctrl(u32 ctrl_type);
static void fdt_enable_nor(void *blob);
#endif
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
-obj-$(CONFIG_T2080QDS) += t208xqds.o eth_t208xqds.o
-obj-$(CONFIG_T2081QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_TARGET_T2081QDS) += t208xqds.o eth_t208xqds.o
obj-$(CONFIG_PCI) += pci.o
endif
#define EMI1_RGMII1 0
#define EMI1_RGMII2 1
#define EMI1_SLOT1 2
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
#define EMI1_SLOT2 6
#define EMI1_SLOT3 3
#define EMI1_SLOT4 4
#define EMI1_SLOT5 5
#define EMI2 7
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
#define EMI1_SLOT2 3
#define EMI1_SLOT3 4
#define EMI1_SLOT5 5
static int mdio_mux[NUM_FM_PORTS];
static const char * const mdio_names[] = {
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
"T2080QDS_MDIO_RGMII1",
"T2080QDS_MDIO_RGMII2",
"T2080QDS_MDIO_SLOT1",
"T2080QDS_MDIO_SLOT5",
"T2080QDS_MDIO_SLOT2",
"T2080QDS_MDIO_10GC",
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
"T2081QDS_MDIO_RGMII1",
"T2081QDS_MDIO_RGMII2",
"T2081QDS_MDIO_SLOT1",
};
/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
#endif
int off;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_T2080QDS
+#ifdef CONFIG_TARGET_T2080QDS
serdes_corenet_t *srds_regs =
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
phy = fm_info_get_phy_address(port);
switch (port) {
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
case FM1_DTSEC1:
if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
media_type = 1;
fdt_status_okay_by_alias(fdt, "emi1_slot2");
}
break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC5:
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
switch (srds_s1) {
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
case 0x51:
case 0x5f:
case 0x65:
lane_to_slot[6] = 3;
lane_to_slot[7] = 3;
break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
case 0x6b:
lane_to_slot[4] = 1;
lane_to_slot[5] = 3;
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
#endif
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
-#if defined(CONFIG_T2081QDS)
+#if defined(CONFIG_TARGET_T2081QDS)
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
#endif
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
break;
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
case 0xd9:
case 0xd3:
case 0xcb:
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
case 0xca:
case 0xcb:
/* SGMII in Slot3 */
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
-#if defined(CONFIG_T2081QDS)
+#if defined(CONFIG_TARGET_T2081QDS)
case 5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i, mii_dev_for_muxval(
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
case 0:
/* SerDes1 is not enabled */
break;
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
case 0x1b:
case 0x1c:
case 0xa2:
*/
QIXIS_WRITE(brdcfg[12], 0x1a);
break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
case 0x50:
case 0x51:
/* SD1(A:D) => SLOT2 XAUI
return -1;
}
-#ifdef CONFIG_T2080QDS
+#ifdef CONFIG_TARGET_T2080QDS
switch (srds_prtcl_s2) {
case 0:
/* SerDes2 is not enabled */
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
-obj-$(CONFIG_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
+obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
obj-$(CONFIG_PCI) += pci.o
endif
{
int ret;
-#ifdef CONFIG_DWMMC
+#ifdef CONFIG_MMC_DW
/* mmc0 clocks are already configured by ATF */
ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
MUX_MCX();
}
-#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC_OMAP_HS) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
F: configs/igep0020_defconfig
F: configs/igep0030_defconfig
F: configs/igep0032_defconfig
-
-IGEP0020_NAND BOARD
-#M: -
-S: Maintained
-F: configs/igep0020_nand_defconfig
-F: configs/igep0030_nand_defconfig
#include <linux/mtd/nand.h>
#include <linux/mtd/onenand.h>
#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+#include <fdt_support.h>
#include "igep00x0.h"
DECLARE_GLOBAL_DATA_PTR;
}
#endif
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+ static struct node_info nodes[] = {
+ { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
+ { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, },
+ };
+
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+ return 0;
+}
+#endif
+
void set_fdt(void)
{
switch (gd->bd->bi_arch_number) {
#include <linux/errno.h>
#include <hwconfig.h>
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
#include <mmc.h>
#include <asm/arch/sdmmc_defs.h>
#endif
#define EEPROM_REV_OFFSET 0x3F00
#define EEPROM_MAC_OFFSET 0x3F06
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
static struct davinci_mmc mmc_sd0 = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
.host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
static struct board_id {
char *name;
int machine_id;
+ char *fdtfile;
} boards[2][2] = {
{
{
.name = "OMAP35xx SOM LV",
.machine_id = MACH_TYPE_OMAP3530_LV_SOM,
+ .fdtfile = "logicpd-som-lv-35xx-devkit.dtb",
},
{
.name = "OMAP35xx Torpedo",
.machine_id = MACH_TYPE_OMAP3_TORPEDO,
+ .fdtfile = "logicpd-torpedo-35xx-devkit.dtb",
},
},
{
{
.name = "DM37xx SOM LV",
- .machine_id = MACH_TYPE_DM3730_SOM_LV,
+ .fdtfile = "logicpd-som-lv-37xx-devkit.dtb",
},
{
.name = "DM37xx Torpedo",
- .machine_id = MACH_TYPE_DM3730_TORPEDO,
+ .fdtfile = "logicpd-torpedo-37xx-devkit.dtb",
},
},
};
*/
int board_init(void)
{
- struct board_id *board;
- unsigned int val;
-
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ struct board_id *board;
+ unsigned int val;
+
/*
* To identify between a SOM LV and Torpedo module,
* a pulldown resistor is on hsusb0_data5 for the SOM LV module.
printf("Board: %s\n", board->name);
/* Set the machine_id passed to Linux */
- gd->bd->bi_arch_number = board->machine_id;
+ if (board->machine_id)
+ gd->bd->bi_arch_number = board->machine_id;
+
+ /* If the user has not set fdtimage, set the default */
+ if (!getenv("fdtimage"))
+ setenv("fdtimage", board->fdtfile);
}
/* restore hsusb0_data5 pin as hsusb0_data5 */
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- /* If we do not have an fdtimage, let's autodetect it*/
- if (getenv("fdtimage"))
- return 0;
-
- switch (gd->bd->bi_arch_number) {
- case MACH_TYPE_DM3730_TORPEDO:
- setenv("fdtimage", "logicpd-torpedo-37xx-devkit.dtb");
- break;
- case MACH_TYPE_DM3730_SOM_LV:
- setenv("fdtimage", "logicpd-som-lv-37xx-devkit.dtb");
- break;
- case MACH_TYPE_OMAP3_TORPEDO:
- setenv("fdtimage", "logicpd-torpedo-35xx-devkit.dtb");
- break;
- case MACH_TYPE_OMAP3530_LV_SOM:
- setenv("fdtimage", "logicpd-som-lv-35xx-devkit.dtb");
- break;
- default:
- /* unknown machine type */
- break;
- }
return 0;
}
#endif
int board_init(void)
{
- gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45;
-
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
pinmux_config_drvgrp_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
}
-#if defined(CONFIG_TEGRA_MMC)
+#if defined(CONFIG_MMC_SDHCI_TEGRA)
/*
* Do I2C/PMU writes to bring up SD card bus power
*
ARRAY_SIZE(dalmore_padctrl));
}
-#if defined(CONFIG_TEGRA_MMC)
+#if defined(CONFIG_MMC_SDHCI_TEGRA)
/*
* Do I2C/PMU writes to bring up SD card bus power
*
#include <asm/arch/tegra.h>
#include <asm/gpio.h>
-#ifdef CONFIG_TEGRA_MMC
+#ifdef CONFIG_MMC_SDHCI_TEGRA
/*
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
}
#endif
-#ifdef CONFIG_TEGRA_MMC
+#ifdef CONFIG_MMC_SDHCI_TEGRA
/*
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
#include <asm/gpio.h>
#include <i2c.h>
-#ifdef CONFIG_TEGRA_MMC
+#ifdef CONFIG_MMC_SDHCI_TEGRA
/*
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
static int init_dwmmc(void)
{
-#ifdef CONFIG_DWMMC
+#ifdef CONFIG_MMC_DW
return exynos_dwmmc_init(gd->fdt_blob);
#else
return 0;
bool "sun50i (Allwinner A64)"
select ARM64
select SUNXI_GEN_SUN6I
+ select SUPPORT_SPL
endchoice
bool
default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
+config RESERVE_ALLWINNER_BOOT0_HEADER
+ bool "reserve space for Allwinner boot0 header"
+ select ENABLE_ARM_SOC_BOOT0_HOOK
+ ---help---
+ Prepend a 1536 byte (empty) header to the U-Boot image file, to be
+ filled with magic values post build. The Allwinner provided boot0
+ blob relies on this information to load and execute U-Boot.
+ Only needed on 64-bit Allwinner boards so far when using boot0.
+
+config ARM_BOOT_HOOK_RMR
+ bool
+ depends on ARM64
+ default y
+ select ENABLE_ARM_SOC_BOOT0_HOOK
+ ---help---
+ Insert some ARM32 code at the very beginning of the U-Boot binary
+ which uses an RMR register write to bring the core into AArch64 mode.
+ The very first instruction acts as a switch, since it's carefully
+ chosen to be a NOP in one mode and a branch in the other, so the
+ code would only be executed if not already in AArch64.
+ This allows both the SPL and the U-Boot proper to be entered in
+ either mode and switch to AArch64 if needed.
+
config DRAM_TYPE
int "sunxi dram type"
depends on MACH_SUN8I_A83T
default 792 if MACH_SUN9I
default 312 if MACH_SUN6I || MACH_SUN8I
default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+ default 672 if MACH_SUN50I
---help---
Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
must be a multiple of 24. For the sun9i (A80), the tested values
default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
default 127 if MACH_SUN7I
default 4145117 if MACH_SUN9I
+ default 3881915 if MACH_SUN50I
---help---
Set the dram zq value.
bool "sunxi dram odt enable"
default n if !MACH_SUN8I_A23
default y if MACH_SUN8I_A23
+ default y if MACH_SUN50I
---help---
Select this to enable dram odt (on die termination).
Set this to enable various workarounds for old kernels, this results in
sub-optimal settings for newer kernels, only enable if needed.
-config MMC
- depends on !UART0_PORT_F
- default y if ARCH_SUNXI
-
config MMC0_CD_PIN
string "Card detect pin for mmc0"
default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
S: Maintained
F: configs/Nintendo_NES_Classic_Edition_defconfig
+ORANGEPI ZERO BOARD
+M: Icenowy Zheng <icenowy@aosc.xyz>
+S: Maintained
+F: configs/orangepi_zero_defconfig
+
R16 EVB PARROT BOARD
M: Quentin Schulz <quentin.schulz@free-electrons.com>
S: Maintained
return 0;
}
-#if defined(CONFIG_OMAP_HSMMC) && \
+#if defined(CONFIG_MMC_OMAP_HS) && \
!defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
return 0;
}
-#if defined(CONFIG_OMAP_HSMMC) && \
+#if defined(CONFIG_MMC_OMAP_HS) && \
!defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
int board_init(void)
{
gpmc_init();
- gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
}
#endif
-#ifdef CONFIG_TEGRA_MMC
+#ifdef CONFIG_MMC_SDHCI_TEGRA
/*
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
default "xilinx"
config SYS_CONFIG_NAME
+ string "Board configuration name"
default "microblaze-generic"
+ help
+ This option contains information about board configuration name.
+ Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+ will be used for board configuration.
config XILINX_MICROBLAZE0_USE_MSR_INSTR
int "USE_MSR_INSTR range (0:1)"
int board_late_init(void)
{
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+ case ZYNQ_BM_QSPI:
+ setenv("modeboot", "qspiboot");
+ break;
+ case ZYNQ_BM_NAND:
+ setenv("modeboot", "nandboot");
+ break;
case ZYNQ_BM_NOR:
setenv("modeboot", "norboot");
break;
else if (len == 4) {
char buf[11];
- sprintf(buf, "0x%08X", *(uint32_t *)nodep);
+ sprintf(buf, "0x%08X", fdt32_to_cpu(*(fdt32_t *)nodep));
setenv(var, buf);
} else if (len%4 == 0 && len <= 20) {
/* Needed to print things like sha1 hashes. */
else if (strncmp(argv[1], "ap", 2) == 0) {
unsigned long addr;
struct fdt_header *blob;
+ int ret;
if (argc != 3)
return CMD_RET_USAGE;
if (!fdt_valid(&blob))
return CMD_RET_FAILURE;
- if (fdt_overlay_apply(working_fdt, blob))
+ ret = fdt_overlay_apply(working_fdt, blob);
+ if (ret) {
+ printf("fdt_overlay_apply(): %s\n", fdt_strerror(ret));
return CMD_RET_FAILURE;
+ }
}
#endif
/* resize the fdt */
cp = newp;
tmp = simple_strtoul(cp, &newp, 0);
- *(__be32 *)data = __cpu_to_be32(tmp);
+ *(fdt32_t *)data = cpu_to_fdt32(tmp);
data += 4;
*len += 4;
static int fpga_get_op(char *opstr);
/* Local defines */
-#define FPGA_NONE -1
-#define FPGA_INFO 0
-#define FPGA_LOAD 1
-#define FPGA_LOADB 2
-#define FPGA_DUMP 3
-#define FPGA_LOADMK 4
-#define FPGA_LOADP 5
-#define FPGA_LOADBP 6
-#define FPGA_LOADFS 7
+enum {
+ FPGA_NONE = -1,
+ FPGA_INFO,
+ FPGA_LOAD,
+ FPGA_LOADB,
+ FPGA_DUMP,
+ FPGA_LOADMK,
+ FPGA_LOADP,
+ FPGA_LOADBP,
+ FPGA_LOADFS,
+};
/* ------------------------------------------------------------------------- */
/* command form:
static int do_mem_cp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- ulong addr, dest, count, bytes;
+ ulong addr, dest, count;
int size;
- const void *src;
- void *buf;
if (argc != 4)
return CMD_RET_USAGE;
}
#endif
- bytes = size * count;
- buf = map_sysmem(dest, bytes);
- src = map_sysmem(addr, bytes);
- while (count-- > 0) {
- if (size == 4)
- *((u32 *)buf) = *((u32 *)src);
-#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
- else if (size == 8)
- *((u64 *)buf) = *((u64 *)src);
-#endif
- else if (size == 2)
- *((u16 *)buf) = *((u16 *)src);
- else
- *((u8 *)buf) = *((u8 *)src);
- src += size;
- buf += size;
-
- /* reset watchdog from time to time */
- if ((count % (64 << 10)) == 0)
- WATCHDOG_RESET();
- }
- unmap_sysmem(buf);
- unmap_sysmem(src);
+ memcpy((void *)dest, (void *)addr, count * size);
return 0;
}
if (sata_curr_device != -1)
sata_stop();
- return sata_initialize();
+ return (sata_initialize() < 0) ?
+ CMD_RET_FAILURE : CMD_RET_SUCCESS;
}
/* If the user has not yet run `sata init`, do it now */
if (sata_curr_device == -1) {
rc = sata_initialize();
if (rc == -1)
- return rc;
+ return CMD_RET_FAILURE;
sata_curr_device = rc;
}
return;
/* Driver model will probe the devices as they are found */
-#ifndef CONFIG_DM_USB
# ifdef CONFIG_USB_STORAGE
/* try to recognize storage devices immediately */
usb_stor_curr_dev = usb_stor_scan(1);
# endif
+#ifndef CONFIG_DM_USB
# ifdef CONFIG_USB_KEYBOARD
drv_usb_kbd_init();
# endif
}
/**
+ * Get 'data-offset' property from a given image node.
+ *
+ * @fit: pointer to the FIT image header
+ * @noffset: component image node offset
+ * @data_offset: holds the data-offset property
+ *
+ * returns:
+ * 0, on success
+ * -ENOENT if the property could not be found
+ */
+int fit_image_get_data_offset(const void *fit, int noffset, int *data_offset)
+{
+ const fdt32_t *val;
+
+ val = fdt_getprop(fit, noffset, FIT_DATA_OFFSET_PROP, NULL);
+ if (!val)
+ return -ENOENT;
+
+ *data_offset = fdt32_to_cpu(*val);
+
+ return 0;
+}
+
+/**
+ * Get 'data-size' property from a given image node.
+ *
+ * @fit: pointer to the FIT image header
+ * @noffset: component image node offset
+ * @data_size: holds the data-size property
+ *
+ * returns:
+ * 0, on success
+ * -ENOENT if the property could not be found
+ */
+int fit_image_get_data_size(const void *fit, int noffset, int *data_size)
+{
+ const fdt32_t *val;
+
+ val = fdt_getprop(fit, noffset, FIT_DATA_SIZE_PROP, NULL);
+ if (!val)
+ return -ENOENT;
+
+ *data_size = fdt32_to_cpu(*val);
+
+ return 0;
+}
+
+/**
* fit_image_hash_get_algo - get hash algorithm name
* @fit: pointer to the FIT format image header
* @noffset: hash node offset
if (mode == 1)
printf("scanning bus for devices...\n");
+ blk_unbind_all(IF_TYPE_SCSI);
+
ret = uclass_get(UCLASS_SCSI, &uc);
if (ret)
return ret;
in drivers/power, drivers/power/pmic and drivers/power/regulator
as part of an SPL build.
+config SPL_RAM_SUPPORT
+ bool "Support booting from RAM"
+ depends on SPL
+ default y if MICROBLAZE || ARCH_SOCFPGA || TEGRA || ARCH_ZYNQ
+ help
+ Enable booting of an image in RAM. The image can be preloaded or
+ it can be loaded by SPL directly into RAM (e.g. using USB).
+
+config SPL_RAM_DEVICE
+ bool "Support booting from preloaded image in RAM"
+ depends on SPL_RAM_SUPPORT
+ default y if MICROBLAZE || ARCH_SOCFPGA || TEGRA || ARCH_ZYNQ
+ help
+ Enable booting of an image already loaded in RAM. The image has to
+ be already in memory when SPL takes over, e.g. loaded by the boot
+ ROM.
+
config SPL_SATA_SUPPORT
bool "Support loading from SATA"
depends on SPL
config SPL_DFU_RAM
bool "RAM device"
- depends on SPL_DFU_SUPPORT
+ depends on SPL_DFU_SUPPORT && SPL_RAM_SUPPORT
help
select RAM/DDR memory device for loading binary images
(u-boot/kernel) to the selected device partition using
obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o
obj-$(CONFIG_SPL_DFU_SUPPORT) += spl_dfu.o
obj-$(CONFIG_SPL_SPI_LOAD) += spl_spi.o
+obj-$(CONFIG_SPL_RAM_SUPPORT) += spl_ram.o
endif
}
spl_image->os = image_get_os(header);
spl_image->name = image_get_name(header);
- debug("spl: payload image: %.*s load addr: 0x%x size: %d\n",
+ debug("spl: payload image: %.*s load addr: 0x%lx size: %d\n",
(int)sizeof(spl_image->name), spl_image->name,
spl_image->load_addr, spl_image->size);
} else {
spl_image->load_addr = CONFIG_SYS_LOAD_ADDR;
spl_image->entry_point = CONFIG_SYS_LOAD_ADDR;
spl_image->size = end - start;
- debug("spl: payload zImage, load addr: 0x%x size: %d\n",
+ debug("spl: payload zImage, load addr: 0x%lx size: %d\n",
spl_image->load_addr, spl_image->size);
return 0;
}
typedef void __noreturn (*image_entry_noargs_t)(void);
image_entry_noargs_t image_entry =
- (image_entry_noargs_t)(unsigned long)spl_image->entry_point;
+ (image_entry_noargs_t)spl_image->entry_point;
- debug("image entry point: 0x%X\n", spl_image->entry_point);
- image_entry();
-}
-
-#ifndef CONFIG_SPL_LOAD_FIT_ADDRESS
-# define CONFIG_SPL_LOAD_FIT_ADDRESS 0
-#endif
-
-#if defined(CONFIG_SPL_RAM_DEVICE) || defined(CONFIG_SPL_DFU_SUPPORT)
-static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
- ulong count, void *buf)
-{
- debug("%s: sector %lx, count %lx, buf %lx\n",
- __func__, sector, count, (ulong)buf);
- memcpy(buf, (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + sector), count);
- return count;
-}
-
-static int spl_ram_load_image(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev)
-{
- struct image_header *header;
-
- header = (struct image_header *)CONFIG_SPL_LOAD_FIT_ADDRESS;
-
-#if defined(CONFIG_SPL_DFU_SUPPORT)
- if (bootdev->boot_device == BOOT_DEVICE_DFU)
- spl_dfu_cmd(0, "dfu_alt_info_ram", "ram", "0");
+ debug("image entry point: 0x%lX\n", spl_image->entry_point);
+#if defined(CONFIG_ARMV8_SPIN_TABLE) && defined(CONFIG_ARMV8_MULTIENTRY)
+ /*
+ * Release all slave cores from CPU_RELEASE_ADDR so they could
+ * arrive to the spin-table code in start.S of the u-boot
+ */
+ *(ulong *)CPU_RELEASE_ADDR = (ulong)spl_image->entry_point;
#endif
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.bl_len = 1;
- load.read = spl_ram_load_read;
- spl_load_simple_fit(spl_image, &load, 0, header);
- } else {
- debug("Legacy image\n");
- /*
- * Get the header. It will point to an address defined by
- * handoff which will tell where the image located inside
- * the flash. For now, it will temporary fixed to address
- * pointed by U-Boot.
- */
- header = (struct image_header *)
- (CONFIG_SYS_TEXT_BASE - sizeof(struct image_header));
-
- spl_parse_image_header(spl_image, header);
- }
-
- return 0;
+ image_entry();
}
-#if defined(CONFIG_SPL_RAM_DEVICE)
-SPL_LOAD_IMAGE_METHOD("RAM", 0, BOOT_DEVICE_RAM, spl_ram_load_image);
-#endif
-#if defined(CONFIG_SPL_DFU_SUPPORT)
-SPL_LOAD_IMAGE_METHOD("USB DFU", 0, BOOT_DEVICE_DFU, spl_ram_load_image);
-#endif
-#endif
int spl_init(void)
{
}
}
if (IS_ENABLED(CONFIG_SPL_DM)) {
- /* With CONFIG_OF_PLATDATA, bring in all devices */
+ /* With CONFIG_SPL_OF_PLATDATA, bring in all devices */
ret = dm_init_and_scan(!CONFIG_IS_ENABLED(OF_PLATDATA));
if (ret) {
debug("dm_init_and_scan() returned error %d\n", ret);
/* Read the header too to avoid extra memcpy */
count = blk_dread(mmc_get_blk_desc(mmc), sector, image_size_sectors,
(void *)(ulong)spl_image->load_addr);
- debug("read %x sectors to %x\n", image_size_sectors,
+ debug("read %x sectors to %lx\n", image_size_sectors,
spl_image->load_addr);
if (count != image_size_sectors)
return -EIO;
--- /dev/null
+/*
+ * (C) Copyright 2016
+ * Xilinx, Inc.
+ *
+ * (C) Copyright 2016
+ * Toradex AG
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Stefan Agner <stefan.agner@toradex.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <spl.h>
+#include <libfdt.h>
+
+#ifndef CONFIG_SPL_LOAD_FIT_ADDRESS
+# define CONFIG_SPL_LOAD_FIT_ADDRESS 0
+#endif
+
+static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
+ ulong count, void *buf)
+{
+ debug("%s: sector %lx, count %lx, buf %lx\n",
+ __func__, sector, count, (ulong)buf);
+ memcpy(buf, (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + sector), count);
+ return count;
+}
+
+static int spl_ram_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ struct image_header *header;
+
+ header = (struct image_header *)CONFIG_SPL_LOAD_FIT_ADDRESS;
+
+#if defined(CONFIG_SPL_DFU_SUPPORT)
+ if (bootdev->boot_device == BOOT_DEVICE_DFU)
+ spl_dfu_cmd(0, "dfu_alt_info_ram", "ram", "0");
+#endif
+
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ image_get_magic(header) == FDT_MAGIC) {
+ struct spl_load_info load;
+
+ debug("Found FIT\n");
+ load.bl_len = 1;
+ load.read = spl_ram_load_read;
+ spl_load_simple_fit(spl_image, &load, 0, header);
+ } else {
+ debug("Legacy image\n");
+ /*
+ * Get the header. It will point to an address defined by
+ * handoff which will tell where the image located inside
+ * the flash. For now, it will temporary fixed to address
+ * pointed by U-Boot.
+ */
+ header = (struct image_header *)
+ (CONFIG_SYS_TEXT_BASE - sizeof(struct image_header));
+
+ spl_parse_image_header(spl_image, header);
+ }
+
+ return 0;
+}
+#if defined(CONFIG_SPL_RAM_DEVICE)
+SPL_LOAD_IMAGE_METHOD("RAM", 0, BOOT_DEVICE_RAM, spl_ram_load_image);
+#endif
+#if defined(CONFIG_SPL_DFU_SUPPORT)
+SPL_LOAD_IMAGE_METHOD("DFU", 0, BOOT_DEVICE_DFU, spl_ram_load_image);
+#endif
+
+
*/
#include <common.h>
-#include <nand.h>
+#include <bmp_layout.h>
#include <errno.h>
-#include <splash.h>
-#include <spi_flash.h>
+#include <fs.h>
+#include <fdt_support.h>
+#include <image.h>
+#include <nand.h>
+#include <sata.h>
#include <spi.h>
+#include <spi_flash.h>
+#include <splash.h>
#include <usb.h>
-#include <sata.h>
-#include <bmp_layout.h>
-#include <fs.h>
DECLARE_GLOBAL_DATA_PTR;
return NULL;
}
+#ifdef CONFIG_FIT
+static int splash_load_fit(struct splash_location *location, u32 bmp_load_addr)
+{
+ int res;
+ int node_offset;
+ int splash_offset;
+ int splash_size;
+ struct image_header *img_header;
+ const u32 *fit_header;
+ u32 fit_size;
+ const size_t header_size = sizeof(struct image_header);
+
+ /* Read in image header */
+ res = splash_storage_read_raw(location, bmp_load_addr, header_size);
+ if (res < 0)
+ return res;
+
+ img_header = (struct image_header *)bmp_load_addr;
+ fit_size = fdt_totalsize(img_header);
+
+ /* Read in entire FIT */
+ fit_header = (const u32 *)(bmp_load_addr + header_size);
+ res = splash_storage_read_raw(location, (u32)fit_header, fit_size);
+ if (res < 0)
+ return res;
+
+ res = fit_check_format(fit_header);
+ if (!res) {
+ debug("Could not find valid FIT image\n");
+ return -EINVAL;
+ }
+
+ node_offset = fit_image_get_node(fit_header, location->name);
+ if (node_offset < 0) {
+ debug("Could not find splash image '%s' in FIT\n",
+ location->name);
+ return -ENOENT;
+ }
+
+ res = fit_image_get_data_offset(fit_header, node_offset,
+ &splash_offset);
+ if (res < 0) {
+ printf("Failed to load splash image (err=%d)\n", res);
+ return res;
+ }
+
+ res = fit_image_get_data_size(fit_header, node_offset, &splash_size);
+ if (res < 0) {
+ printf("Failed to load splash image (err=%d)\n", res);
+ return res;
+ }
+
+ /* Align data offset to 4-byte boundrary */
+ fit_size = fdt_totalsize(fit_header);
+ fit_size = (fit_size + 3) & ~3;
+
+ /* Read in the splash data */
+ location->offset = (location->offset + fit_size + splash_offset);
+ res = splash_storage_read_raw(location, bmp_load_addr , splash_size);
+ if (res < 0)
+ return res;
+
+ return 0;
+}
+#endif /* CONFIG_FIT */
+
/**
* splash_source_load - load splash image from a supported location.
*
if (!splash_location)
return -EINVAL;
- if (splash_location->flags & SPLASH_STORAGE_RAW)
+ if (splash_location->flags == SPLASH_STORAGE_RAW)
return splash_load_raw(splash_location, bmp_load_addr);
- else if (splash_location->flags & SPLASH_STORAGE_FS)
+ else if (splash_location->flags == SPLASH_STORAGE_FS)
return splash_load_fs(splash_location, bmp_load_addr);
-
+#ifdef CONFIG_FIT
+ else if (splash_location->flags == SPLASH_STORAGE_FIT)
+ return splash_load_fit(splash_location, bmp_load_addr);
+#endif
return -EINVAL;
}
usb_max_devs = 0;
}
-#ifndef CONFIG_DM_USB
/*******************************************************************************
* scan the usb and reports device info
* to the user if mode = 1
*/
int usb_stor_scan(int mode)
{
- unsigned char i;
-
if (mode == 1)
printf(" scanning usb for storage devices... ");
+#ifndef CONFIG_DM_USB
+ unsigned char i;
+
usb_disable_asynch(1); /* asynch transfer not allowed */
usb_stor_reset();
} /* for */
usb_disable_asynch(0); /* asynch transfer allowed */
+#endif
printf("%d Storage Device(s) found\n", usb_max_devs);
if (usb_max_devs > 0)
return 0;
return -1;
}
-#endif
static int usb_stor_irq(struct usb_device *dev)
{
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR2=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR2=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR2=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR2=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_SYS_FSL_DDR2=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_SYS_FSL_DDR2=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1023RDB"
+CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1023RDB"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1024RDB"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="T1024RDB"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_RSA=y
CONFIG_SPL_OF_LIBFDT=y
+CONFIG_MISC=y
+CONFIG_DM_USB=y
+CONFIG_USB_MUSB_TI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_DFU_RAM=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_DFU_RAM=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_SERIAL=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_MXC=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_MXS=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_SOUND=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_DM_I2C_COMPAT=y
+CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_SOUND=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_SYS_I2C_DW=y
+CONFIG_MMC_DW=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_SERIAL=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_SYS_I2C_DW=y
+CONFIG_MMC_DW=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_SERIAL=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_NETCONSOLE=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_NETCONSOLE=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_NETCONSOLE=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_ROCKCHIP_RK3036_PINCTRL=y
CONFIG_RAM=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_FULL is not set
CONFIG_SPL_PINCTRL=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_ROCKCHIP_GPIO=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_ROCKCHIP_SDHCI=y
CONFIG_MMC_SDHCI=y
CONFIG_PINCTRL=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_FULL is not set
CONFIG_SPL_PINCTRL=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_NETDEVICES=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_CACHE=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_K3=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OMAP34XX=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_UBI=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032"
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_UBI=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_BLK is not set
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
+CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_ROCKCHIP_RK3036_PINCTRL=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
-CONFIG_SYS_FSL_DDR4=y
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FIT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
-CONFIG_SYS_FSL_DDR4=y
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_FIT=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_FSL_DDR3=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SECURE_BOOT=y
-CONFIG_SYS_FSL_DDR3=y
CONFIG_VIDEO=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
-CONFIG_SYS_FSL_DDR3=y
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FIT=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
-CONFIG_SYS_FSL_DDR3=y
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_FIT=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
-CONFIG_SYS_FSL_DDR3=y
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FIT=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_FSL_DDR3=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_FSL_DDR3=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
-CONFIG_SYS_FSL_DDR4=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
-CONFIG_SYS_FSL_DDR4=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_FSL_DDR4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
-CONFIG_SYS_FSL_DDR3=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
-CONFIG_SYS_FSL_DDR4=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_FSL_DDR4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_FSL_DDR4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_FSL_DDR4=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_FSL_DDR4=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_FSL_DDR4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_FSL_DDR4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT_QSPI"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SYS_FSL_DDR4,EMMC_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,EMMC_BOOT"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SYS_FSL_DDR4"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="EMU,LS2080A"
CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,LS2080A"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="LS2080A"
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_ULPI_VIEWPORT_OMAP=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_ULPI_VIEWPORT_OMAP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_MXS=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_MXS=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_CFB_CONSOLE_ANSI=y
# CONFIG_VGA_AS_SINGLE_DEVICE is not set
CONFIG_ADC_EXYNOS=y
CONFIG_DFU_MMC=y
CONFIG_DM_I2C_COMPAT=y
+CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_DM_PMIC=y
CONFIG_OF_CONTROL=y
CONFIG_DFU_MMC=y
CONFIG_DM_I2C_COMPAT=y
+CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_TARGET_OMAPL138_LCDK=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=3
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DFU_MMC=y
+CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
+CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_SPI_FLASH=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
+CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
-CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN50I=y
-CONFIG_DRAM_CLK=672
-CONFIG_DRAM_ZQ=3881915
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_NETDEVICES=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DFU_MMC=y
+CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_MXS=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_MXS=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_DM_I2C_COMPAT=y
+CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_DM_I2C_COMPAT=y
+CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
+CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_SPI_FLASH=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
+CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
+CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami"
CONFIG_BOOTDELAY=0
CONFIG_SYS_NO_FLASH=y
CONFIG_SYS_CONFIG_NAME="topic_miamiplus"
CONFIG_ARCH_ZYNQ=y
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
+CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"
CONFIG_BOOTDELAY=0
CONFIG_SYS_NO_FLASH=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DFU_MMC=y
+CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DFU_MMC=y
+CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_MMC_MXS=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_ULPI_VIEWPORT_OMAP=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARCH_UNIPHIER_LD11=y
CONFIG_MICRO_SUPPORT_CARD=y
-# CONFIG_MMC is not set
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld11-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_GPIO_UNIPHIER=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_UNIPHIER=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC_MXS=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_STORAGE=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+CONFIG_SYS_FSL_DDR2=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
CONFIG_SYS_NO_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
# CONFIG_MMC is not set
+CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
# CONFIG_MMC is not set
+CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
# CONFIG_MMC is not set
+CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_zybo"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
- USB host
- USB device
- Run CPU at full speed (code exists but we only see ~60 DMIPS maximum)
-- Ethernet
- NAND flash
- Support for other Rockchip parts
- Boot U-Boot proper over USB OTG (at present only SPL works)
Here are macro and detailed configuration required to enable DesignWare SDMMC
controller support within SOCFPGA
-#define CONFIG_MMC
--> To enable the SD MMC framework support
-
-#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS)
--> The base address of CSR register for DesignWare SDMMC controller
-
#define CONFIG_GENERIC_MMC
-> Enable the generic MMC driver
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
-
-#define CONFIG_DWMMC
--> Enable the common DesignWare SDMMC controller framework
-
-#define CONFIG_SOCFPGA_DWMMC
--> Enable the SOCFPGA specific driver for DesignWare SDMMC controller
-
-#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
--> The FIFO depth for SOCFPGA DesignWare SDMMC controller
-
-#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
--> Phase-shifted clock of sdmmc_clk for controller to drive command and data to
-the card to meet hold time requirements. SD clock is running at 50MHz and
-drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time
-is 135 / 360 * 20ns = 7.5ns.
-
-#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
--> Phase-shifted clock of sdmmc_clk used to sample the command and data from
-the card
-
-#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4
--> Bus width of data line which either 1, 4 or 8 and based on board routing.
-
-#define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000
--> The clock rate to controller. Do note the controller have a wrapper which
-divide the clock from PLL by 4.
common/splash.c. It is called as part of the splash screen display
sequence. It gives the board an opportunity to prepare the splash
image data before it is processed and sent to the frame buffer by
-U-Boot. Define your own version to use this feature.
+U-Boot. Define your own version to use this feature.
CONFIG_SPLASH_SOURCE
- If splashsource is undefined, use the first splash location as default.
- If splashsource is set to an unsupported value, do not load a splash screen.
-A splash source location can describe either storage with raw data, or storage
-formatted with a file system. In case of a filesystem, the splash screen data is
-loaded as a file. The name of the splash screen file can be controlled with the
-environment variable "splashfile".
+A splash source location can describe either storage with raw data, a storage
+formatted with a file system or a FIT image. In case of a filesystem, the splash
+screen data is loaded as a file. The name of the splash screen file can be
+controlled with the environment variable "splashfile".
+
+To enable loading the splash image from a FIT image, CONFIG_FIT must be
+enabled. Struct splash_location field 'name' should match the splash image
+name within the FIT and the FIT should start at the 'offset' field address in
+the specified storage.
Test passed
+Hardware Signing with PKCS#11
+-----------------------------
+
+Securely managing private signing keys can challenging, especially when the
+keys are stored on the file system of a computer that is connected to the
+Internet. If an attacker is able to steal the key, they can sign malicious FIT
+images which will appear genuine to your devices.
+
+An alternative solution is to keep your signing key securely stored on hardware
+device like a smartcard, USB token or Hardware Security Module (HSM) and have
+them perform the signing. PKCS#11 is standard for interfacing with these crypto
+device.
+
+Requirements:
+Smartcard/USB token/HSM which can work with the pkcs11 engine
+openssl
+libp11 (provides pkcs11 engine)
+p11-kit (recommended to simplify setup)
+opensc (for smartcards and smartcard like USB devices)
+gnutls (recommended for key generation, p11tool)
+
+The following examples use the Nitrokey Pro. Instructions for other devices may vary.
+
+Notes on pkcs11 engine setup:
+
+Make sure p11-kit, opensc are installed and that p11-kit is setup to use opensc.
+/usr/share/p11-kit/modules/opensc.module should be present on your system.
+
+
+Generating Keys On the Nitrokey:
+
+$ gpg --card-edit
+
+Reader ...........: Nitrokey Nitrokey Pro (xxxxxxxx0000000000000000) 00 00
+Application ID ...: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Version ..........: 2.1
+Manufacturer .....: ZeitControl
+Serial number ....: xxxxxxxx
+Name of cardholder: [not set]
+Language prefs ...: de
+Sex ..............: unspecified
+URL of public key : [not set]
+Login data .......: [not set]
+Signature PIN ....: forced
+Key attributes ...: rsa2048 rsa2048 rsa2048
+Max. PIN lengths .: 32 32 32
+PIN retry counter : 3 0 3
+Signature counter : 0
+Signature key ....: [none]
+Encryption key....: [none]
+Authentication key: [none]
+General key info..: [none]
+
+gpg/card> generate
+Make off-card backup of encryption key? (Y/n) n
+
+Please note that the factory settings of the PINs are
+ PIN = '123456' Admin PIN = '12345678'
+You should change them using the command --change-pin
+
+What keysize do you want for the Signature key? (2048) 4096
+The card will now be re-configured to generate a key of 4096 bits
+Note: There is no guarantee that the card supports the requested size.
+ If the key generation does not succeed, please check the
+ documentation of your card to see what sizes are allowed.
+What keysize do you want for the Encryption key? (2048) 4096
+The card will now be re-configured to generate a key of 4096 bits
+What keysize do you want for the Authentication key? (2048) 4096
+The card will now be re-configured to generate a key of 4096 bits
+Please specify how long the key should be valid.
+ 0 = key does not expire
+ <n> = key expires in n days
+ <n>w = key expires in n weeks
+ <n>m = key expires in n months
+ <n>y = key expires in n years
+Key is valid for? (0)
+Key does not expire at all
+Is this correct? (y/N) y
+
+GnuPG needs to construct a user ID to identify your key.
+
+Real name: John Doe
+Email address: john.doe@email.com
+Comment:
+You selected this USER-ID:
+ "John Doe <john.doe@email.com>"
+
+Change (N)ame, (C)omment, (E)mail or (O)kay/(Q)uit? o
+
+
+Using p11tool to get the token URL:
+
+Depending on system configuration, gpg-agent may need to be killed first.
+
+$ p11tool --provider /usr/lib/opensc-pkcs11.so --list-tokens
+Token 0:
+URL: pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29
+Label: OpenPGP card (User PIN (sig))
+Type: Hardware token
+Manufacturer: ZeitControl
+Model: PKCS#15 emulated
+Serial: 000xxxxxxxxx
+Module: (null)
+
+
+Token 1:
+URL: pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%29
+Label: OpenPGP card (User PIN)
+Type: Hardware token
+Manufacturer: ZeitControl
+Model: PKCS#15 emulated
+Serial: 000xxxxxxxxx
+Module: (null)
+
+Use the portion of the signature token URL after "pkcs11:" as the keydir argument (-k) to mkimage below.
+
+
+Use the URL of the token to list the private keys:
+
+$ p11tool --login --provider /usr/lib/opensc-pkcs11.so --list-privkeys \
+"pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29"
+Token 'OpenPGP card (User PIN (sig))' with URL 'pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29' requires user PIN
+Enter PIN:
+Object 0:
+URL: pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29;id=%01;object=Signature%20key;type=private
+Type: Private key
+Label: Signature key
+Flags: CKA_PRIVATE; CKA_NEVER_EXTRACTABLE; CKA_SENSITIVE;
+ID: 01
+
+Use the label, in this case "Signature key" as the key-name-hint in your FIT.
+
+Create the fitImage:
+$ ./tools/mkimage -f fit-image.its fitImage
+
+
+Sign the fitImage with the hardware key:
+
+$ ./tools/mkimage -F -k \
+"model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29" \
+-K u-boot.dtb -N pkcs11 -r fitImage
+
+
Future Work
-----------
- Roll-back protection using a TPM is done using the tpm command. This can
source "drivers/demo/Kconfig"
+source "drivers/ddr/fsl/Kconfig"
+
source "drivers/dfu/Kconfig"
source "drivers/dma/Kconfig"
help
Enable this to support the clocks
+config CLK_ZYNQMP
+ bool "Enable clock driver support for ZynqMP"
+ depends on ARCH_ZYNQMP
+ help
+ This clock driver adds support for clock realted settings for
+ ZynqMP platform.
+
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/uniphier/Kconfig"
source "drivers/clk/exynos/Kconfig"
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
+obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
obj-y += tegra/
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
--- /dev/null
+/*
+ * ZynqMP clock driver
+ *
+ * Copyright (C) 2016 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/bitops.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <clk.h>
+
+#define ZYNQMP_GEM0_REF_CTRL 0xFF5E0050
+#define ZYNQMP_IOPLL_CTRL 0xFF5E0020
+#define ZYNQMP_RPLL_CTRL 0xFF5E0030
+#define ZYNQMP_DPLL_CTRL 0xFD1A002C
+#define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013
+#define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013
+#define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013
+#define ZYNQMP_SIP_SVC_MMIO_READ 0xC2000014
+#define ZYNQMP_DIV_MAX_VAL 0x3F
+#define ZYNQMP_DIV1_SHFT 8
+#define ZYNQMP_DIV1_SHFT 8
+#define ZYNQMP_DIV2_SHFT 16
+#define ZYNQMP_DIV_MASK 0x3F
+#define ZYNQMP_PLL_CTRL_FBDIV_MASK 0x7F
+#define ZYNQMP_PLL_CTRL_FBDIV_SHFT 8
+#define ZYNQMP_GEM_REF_CTRL_SRC_MASK 0x7
+#define ZYNQMP_GEM0_CLK_ID 45
+#define ZYNQMP_GEM1_CLK_ID 46
+#define ZYNQMP_GEM2_CLK_ID 47
+#define ZYNQMP_GEM3_CLK_ID 48
+
+static unsigned long pss_ref_clk;
+
+static int zynqmp_calculate_divisors(unsigned long req_rate,
+ unsigned long parent_rate,
+ u32 *div1, u32 *div2)
+{
+ u32 req_div = 1;
+ u32 i;
+
+ /*
+ * calculate two divisors to get
+ * required rate and each divisor
+ * should be less than 63
+ */
+ req_div = DIV_ROUND_UP(parent_rate, req_rate);
+
+ for (i = 1; i <= req_div; i++) {
+ if ((req_div % i) == 0) {
+ *div1 = req_div / i;
+ *div2 = i;
+ if ((*div1 < ZYNQMP_DIV_MAX_VAL) &&
+ (*div2 < ZYNQMP_DIV_MAX_VAL))
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+static int zynqmp_get_periph_id(unsigned long id)
+{
+ int periph_id;
+
+ switch (id) {
+ case ZYNQMP_GEM0_CLK_ID:
+ periph_id = 0;
+ break;
+ case ZYNQMP_GEM1_CLK_ID:
+ periph_id = 1;
+ break;
+ case ZYNQMP_GEM2_CLK_ID:
+ periph_id = 2;
+ break;
+ case ZYNQMP_GEM3_CLK_ID:
+ periph_id = 3;
+ break;
+ default:
+ printf("%s, Invalid clock id:%ld\n", __func__, id);
+ return -EINVAL;
+ }
+
+ return periph_id;
+}
+
+static int zynqmp_set_clk(unsigned long id, u32 div1, u32 div2)
+{
+ struct pt_regs regs;
+ ulong reg;
+ u32 mask, value;
+
+ id = zynqmp_get_periph_id(id);
+ if (id < 0)
+ return -EINVAL;
+
+ reg = (ulong)((u32 *)ZYNQMP_GEM0_REF_CTRL + id);
+ mask = (ZYNQMP_DIV_MASK << ZYNQMP_DIV1_SHFT) |
+ (ZYNQMP_DIV_MASK << ZYNQMP_DIV2_SHFT);
+ value = (div1 << ZYNQMP_DIV1_SHFT) | (div2 << ZYNQMP_DIV2_SHFT);
+
+ debug("%s: reg:0x%lx, mask:0x%x, value:0x%x\n", __func__, reg, mask,
+ value);
+
+ regs.regs[0] = ZYNQMP_SIP_SVC_MMIO_WRITE;
+ regs.regs[1] = ((u64)mask << 32) | reg;
+ regs.regs[2] = value;
+ regs.regs[3] = 0;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+static unsigned long zynqmp_clk_get_rate(struct clk *clk)
+{
+ struct pt_regs regs;
+ ulong reg;
+ unsigned long value;
+ int id;
+
+ id = zynqmp_get_periph_id(clk->id);
+ if (id < 0)
+ return -EINVAL;
+
+ reg = (ulong)((u32 *)ZYNQMP_GEM0_REF_CTRL + id);
+
+ regs.regs[0] = ZYNQMP_SIP_SVC_MMIO_READ;
+ regs.regs[1] = reg;
+ regs.regs[2] = 0;
+ regs.regs[3] = 0;
+
+ smc_call(®s);
+
+ value = upper_32_bits(regs.regs[0]);
+
+ value &= ZYNQMP_GEM_REF_CTRL_SRC_MASK;
+
+ switch (value) {
+ case 0:
+ regs.regs[1] = ZYNQMP_IOPLL_CTRL;
+ break;
+ case 2:
+ regs.regs[1] = ZYNQMP_RPLL_CTRL;
+ break;
+ case 3:
+ regs.regs[1] = ZYNQMP_DPLL_CTRL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regs.regs[0] = ZYNQMP_SIP_SVC_MMIO_READ;
+ regs.regs[2] = 0;
+ regs.regs[3] = 0;
+
+ smc_call(®s);
+
+ value = upper_32_bits(regs.regs[0]) &
+ (ZYNQMP_PLL_CTRL_FBDIV_MASK <<
+ ZYNQMP_PLL_CTRL_FBDIV_SHFT);
+ value >>= ZYNQMP_PLL_CTRL_FBDIV_SHFT;
+ value *= pss_ref_clk;
+
+ return value;
+}
+
+static ulong zynqmp_clk_set_rate(struct clk *clk, unsigned long clk_rate)
+{
+ int ret;
+ u32 div1 = 0;
+ u32 div2 = 0;
+ unsigned long input_clk;
+
+ input_clk = zynqmp_clk_get_rate(clk);
+ if (IS_ERR_VALUE(input_clk)) {
+ dev_err(dev, "failed to get input_clk\n");
+ return -EINVAL;
+ }
+
+ debug("%s: i/p CLK %ld, clk_rate:0x%ld\n", __func__, input_clk,
+ clk_rate);
+
+ ret = zynqmp_calculate_divisors(clk_rate, input_clk, &div1, &div2);
+ if (ret) {
+ dev_err(dev, "failed to proper divisors\n");
+ return -EINVAL;
+ }
+
+ debug("%s: Div1:%d, Div2:%d\n", __func__, div1, div2);
+
+ ret = zynqmp_set_clk(clk->id, div1, div2);
+ if (ret) {
+ dev_err(dev, "failed to set gem clk\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int zynqmp_clk_probe(struct udevice *dev)
+{
+ struct clk clk;
+ int ret;
+
+ debug("%s\n", __func__);
+ ret = clk_get_by_name(dev, "pss_ref_clk", &clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get pss_ref_clk\n");
+ return ret;
+ }
+
+ pss_ref_clk = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(pss_ref_clk)) {
+ dev_err(dev, "failed to get rate pss_ref_clk\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static struct clk_ops zynqmp_clk_ops = {
+ .set_rate = zynqmp_clk_set_rate,
+ .get_rate = zynqmp_clk_get_rate,
+};
+
+static const struct udevice_id zynqmp_clk_ids[] = {
+ { .compatible = "xlnx,zynqmp-clkc" },
+ { }
+};
+
+U_BOOT_DRIVER(zynqmp_clk) = {
+ .name = "zynqmp-clk",
+ .id = UCLASS_CLK,
+ .of_match = zynqmp_clk_ids,
+ .probe = zynqmp_clk_probe,
+ .ops = &zynqmp_clk_ops,
+};
Enables the Freescale's Cryptographic Accelerator and Assurance
Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses
Job Ring as interface to communicate with CAAM.
+
+config SYS_FSL_HAS_SEC
+ bool
+ help
+ Enable Freescale Secure Boot and Trusted Architecture
+
+config SYS_FSL_SEC_COMPAT_2
+ bool
+ help
+ Secure boot and trust architecture compatible version 2
+
+config SYS_FSL_SEC_COMPAT_4
+ bool
+ help
+ Secure boot and trust architecture compatible version 4
+
+config SYS_FSL_SEC_COMPAT_5
+ bool
+ help
+ Secure boot and trust architecture compatible version 5
+
+config SYS_FSL_SEC_COMPAT_6
+ bool
+ help
+ Secure boot and trust architecture compatible version 6
+
+config SYS_FSL_SEC_BE
+ bool "Big-endian access to Freescale Secure Boot"
+
+config SYS_FSL_SEC_COMPAT
+ int "Freescale Secure Boot compatibility"
+ depends on SYS_FSL_HAS_SEC
+ default 2 if SYS_FSL_SEC_COMPAT_2
+ default 4 if SYS_FSL_SEC_COMPAT_4
+ default 5 if SYS_FSL_SEC_COMPAT_5
+ default 6 if SYS_FSL_SEC_COMPAT_6
+
+config SYS_FSL_SEC_LE
+ bool "Little-endian access to Freescale Secure Boot"
--- /dev/null
+config SYS_FSL_DDR
+ bool
+ help
+ Select Freescale General DDR driver, shared between most Freescale
+ PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
+ based Layerscape SoCs (such as ls2080a).
+
+config SYS_FSL_MMDC
+ bool
+ help
+ Select Freescale Multi Mode DDR controller (MMDC).
+
+config SYS_FSL_DDR_BE
+ bool
+ help
+ Access DDR registers in big-endian
+
+config SYS_FSL_DDR_LE
+ bool
+ help
+ Access DDR registers in little-endian
+
+menu "Freescale DDR controllers"
+ depends on SYS_FSL_DDR
+
+config SYS_NUM_DDR_CTLRS
+ int "Maximum DDR controllers"
+ default 3 if ARCH_LS2080A || \
+ ARCH_T4240
+ default 2 if ARCH_B4860 || \
+ ARCH_BSC9132 || \
+ ARCH_MPC8572 || \
+ ARCH_MPC8641 || \
+ ARCH_P4080 || \
+ ARCH_P5020 || \
+ ARCH_P5040 || \
+ ARCH_T4160
+ default 1
+
+config SYS_FSL_DDR_VER
+ int
+ default 50 if SYS_FSL_DDR_VER_50
+ default 47 if SYS_FSL_DDR_VER_47
+ default 46 if SYS_FSL_DDR_VER_46
+ default 44 if SYS_FSL_DDR_VER_44
+
+config SYS_FSL_DDR_VER_50
+ bool
+
+config SYS_FSL_DDR_VER_47
+ bool
+
+config SYS_FSL_DDR_VER_46
+ bool
+
+config SYS_FSL_DDR_VER_44
+ bool
+
+config SYS_FSL_DDRC_GEN1
+ bool
+ help
+ Enable Freescale DDR controller.
+
+config SYS_FSL_DDRC_GEN2
+ bool
+ depends on !MPC86xx
+ help
+ Enable Freescale DDR2 controller.
+
+config SYS_FSL_DDRC_86XX_GEN2
+ bool
+ depends on MPC86xx
+ help
+ Enable Freescale DDR2 controller for MPC86xx SoCs.
+
+config SYS_FSL_DDRC_GEN3
+ bool
+ depends on PPC
+ help
+ Enable Freescale DDR3 controller for PowerPC SoCs.
+
+config SYS_FSL_DDRC_ARM_GEN3
+ bool
+ depends on ARM
+ help
+ Enable Freescale DDR3 controller for ARM SoCs.
+
+config SYS_FSL_DDRC_GEN4
+ bool
+ help
+ Enable Freescale DDR4 controller.
+
+config SYS_FSL_HAS_DDR4
+ bool
+
+config SYS_FSL_HAS_DDR3
+ bool
+
+config SYS_FSL_HAS_DDR2
+ bool
+
+config SYS_FSL_HAS_DDR1
+ bool
+
+choice
+ prompt "DDR technology"
+ default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
+ default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
+ default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
+ default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
+
+config SYS_FSL_DDR4
+ bool "Freescale DDR4 controller"
+ depends on SYS_FSL_HAS_DDR4
+ select SYS_FSL_DDRC_GEN4
+
+config SYS_FSL_DDR3
+ bool "Freescale DDR3 controller"
+ depends on SYS_FSL_HAS_DDR3
+ select SYS_FSL_DDRC_GEN3 if PPC
+ select SYS_FSL_DDRC_ARM_GEN3 if ARM
+
+config SYS_FSL_DDR2
+ bool "Freescale DDR2 controller"
+ depends on SYS_FSL_HAS_DDR2
+ select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
+ select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx
+
+config SYS_FSL_DDR1
+ bool "Freescale DDR1 controller"
+ depends on SYS_FSL_HAS_DDR1
+ select SYS_FSL_DDRC_GEN1
+
+endchoice
+
+endmenu
+
+config SYS_FSL_ERRATUM_A008378
+ bool
+
+config SYS_FSL_ERRATUM_A008511
+ bool
+
+config SYS_FSL_ERRATUM_A009663
+ bool
+
+config SYS_FSL_ERRATUM_A009801
+ bool
+
+config SYS_FSL_ERRATUM_A009803
+ bool
+
+config SYS_FSL_ERRATUM_A009942
+ bool
+
+config SYS_FSL_ERRATUM_A010165
+ bool
+
+config SYS_FSL_ERRATUM_NMG_DDR120
+ bool
+
+config SYS_FSL_ERRATUM_DDR_115
+ bool
+
+config SYS_FSL_ERRATUM_DDR111_DDR134
+ bool
+
+config SYS_FSL_ERRATUM_DDR_A003
+ bool
+
+config SYS_FSL_ERRATUM_DDR_A003474
+ bool
obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
-obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
+obj-$(CONFIG_SYS_FSL_DDRC_86XX_GEN2) += mpc86xx_ddr.o
obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
case 0:
ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
debug("fsl_ddr_regs_edit: ctrl_num = %u, "
"regname = %s, value = %s\n",
ctrl_num, regname, value_str);
- if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
+ if (ctrl_num > CONFIG_SYS_NUM_DDR_CTLRS)
return;
ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
/* STEP 1: DIMM SPD data */
if (do_mask & STEP_GET_SPD) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
/* STEP 2: DIMM Parameters */
if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
/* STEP 3: Common Parameters */
if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
printf("\"lowest common\" DIMM parameters: "
/* STEP 4: User Configuration Options */
if (do_mask & STEP_GATHER_OPTS) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
printf("User Config Options: Controller=%u\n", i);
/* STEP 5: Address assignment */
if (do_mask & STEP_ASSIGN_ADDRESSES) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
/* STEP 6: computed controller register values */
if (do_mask & STEP_COMPUTE_REGS) {
- for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
if (!(ctrl_mask & (1 << i)))
continue;
printf("Computed Register Values: Controller=%u\n", i);
#if defined(SPD_EEPROM_ADDRESS) || \
defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
-#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS,
};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+#elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
[1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
[1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
[2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
};
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
-u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
[1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
unsigned int i;
unsigned int i2c_address = 0;
- if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
+ if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
return;
}
assert_reset = pinfo->board_need_mem_reset();
/* data bus width capacity adjust shift amount */
- unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
+ unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS];
for (i = first_ctrl; i <= last_ctrl; i++)
dbw_capacity_adjust[i] = 0;
&pinfo->common_timing_params[i],
law_memctl, i);
}
-#if CONFIG_NUM_DDR_CONTROLLERS > 3
+#if CONFIG_SYS_NUM_DDR_CTLRS > 3
else if (i == 2) {
law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
fsl_ddr_set_lawbar(
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
* if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
* with 256 Byte is enabled.
*/
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
;
"ctlr_intlv",
"cacheline", buf)) {
popts->memctl_interleaving_mode =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
popts->memctl_interleaving =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : 1;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"page", buf)) {
popts->memctl_interleaving_mode =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_PAGE_INTERLEAVING;
popts->memctl_interleaving =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : 1;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"bank", buf)) {
popts->memctl_interleaving_mode =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_BANK_INTERLEAVING;
popts->memctl_interleaving =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : 1;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"superbank", buf)) {
popts->memctl_interleaving_mode =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_SUPERBANK_INTERLEAVING;
popts->memctl_interleaving =
- ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
+ ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
0 : 1;
-#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"3way_1KB", buf)) {
"3way_8KB", buf)) {
popts->memctl_interleaving_mode =
FSL_DDR_3WAY_8KB_INTERLEAVING;
-#elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
+#elif (CONFIG_SYS_NUM_DDR_CTLRS == 4)
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"4way_1KB", buf)) {
}
#endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
done:
-#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
+#endif /* CONFIG_SYS_NUM_DDR_CTLRS > 1 */
if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
/* test null first. if CONFIG_HWCONFIG is not defined,
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
case FSL_DDR_SUPERBANK_INTERLEAVING:
-#if (3 == CONFIG_NUM_DDR_CONTROLLERS)
+#if (3 == CONFIG_SYS_NUM_DDR_CTLRS)
k = 2;
#else
- k = CONFIG_NUM_DDR_CONTROLLERS;
+ k = CONFIG_SYS_NUM_DDR_CTLRS;
#endif
break;
case FSL_DDR_3WAY_1KB_INTERLEAVING:
case FSL_DDR_4WAY_4KB_INTERLEAVING:
case FSL_DDR_4WAY_8KB_INTERLEAVING:
default:
- k = CONFIG_NUM_DDR_CONTROLLERS;
+ k = CONFIG_SYS_NUM_DDR_CTLRS;
break;
}
debug("%d of %d controllers are interleaving.\n", j, k);
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
-#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
+#if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
#endif
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
#endif
uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
int cas_lat;
-#if CONFIG_NUM_DDR_CONTROLLERS >= 2
+#if CONFIG_SYS_NUM_DDR_CTLRS >= 2
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
(start_ctrl == 1)) {
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
-#if CONFIG_NUM_DDR_CONTROLLERS >= 3
+#if CONFIG_SYS_NUM_DDR_CTLRS >= 3
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
(start_ctrl == 2)) {
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
else
puts(", ECC off)");
-#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
#ifdef CONFIG_E6500
if (*mcintl3r & 0x80000000) {
puts("\n");
}
#endif
#endif
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
puts("\n");
puts(" DDR Controller Interleaving Mode: ");
{
unsigned int i;
u32 ddrc_debug20;
- u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {};
- u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {};
+ u32 ddrc_debug2[CONFIG_SYS_NUM_DDR_CTLRS] = {};
+ u32 *ddrc_debug2_p[CONFIG_SYS_NUM_DDR_CTLRS] = {};
struct ccsr_ddr __iomem *ddr;
for (i = first_ctrl; i <= last_ctrl; i++) {
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
#define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
#endif
-static int zynq_info(xilinx_desc *desc)
-{
- return FPGA_SUCCESS;
-}
-
#define DUMMY_WORD 0xffffffff
/* Xilinx binary format header */
}
#endif
-static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
-{
- return FPGA_FAIL;
-}
-
struct xilinx_fpga_op zynq_op = {
.load = zynq_load,
#if defined(CONFIG_CMD_FPGA_LOADFS)
.loadfs = zynq_loadfs,
#endif
- .dump = zynq_dump,
- .info = zynq_info,
};
static const struct udevice_id cdns_i2c_of_match[] = {
{ .compatible = "cdns,i2c-r1p10" },
+ { .compatible = "cdns,i2c-r1p14" },
{ /* end of table */ }
};
It is compliant with the SD Host Controller Standard V3.0
specification.
-config ROCKCHIP_DWMMC
+config MMC_DAVINCI
+ bool "TI DAVINCI Multimedia Card Interface support"
+ depends on ARCH_DAVINCI
+ default y
+ help
+ This selects the TI DAVINCI Multimedia card Interface.
+ If you have an DAVINCI board with a Multimedia Card slot,
+ say Y here. If unsure, say N.
+
+config MMC_DW
+ bool "Synopsys DesignWare Memory Card Interface"
+ help
+ This selects support for the Synopsys DesignWare Mobile Storage IP
+ block, this provides host support for SD and MMC interfaces, in both
+ PIO, internal DMA mode and external DMA mode.
+
+config MMC_DW_EXYNOS
+ bool "Exynos specific extensions for Synopsys DW Memory Card Interface"
+ depends on ARCH_EXYNOS
+ depends on MMC_DW
+ default y
+ help
+ This selects support for Samsung Exynos SoC specific extensions to the
+ Synopsys DesignWare Memory Card Interface driver. Select this option
+ for platforms based on Exynos4 and Exynos5 SoC's.
+
+config MMC_DW_K3
+ bool "K3 specific extensions for Synopsys DW Memory Card Interface"
+ depends on MMC_DW
+ help
+ This selects support for Hisilicon K3 SoC specific extensions to the
+ Synopsys DesignWare Memory Card Interface driver. Select this option
+ for platforms based on Hisilicon K3 SoC's.
+
+config MMC_DW_ROCKCHIP
bool "Rockchip SD/MMC controller support"
depends on DM_MMC && OF_CONTROL
+ depends on MMC_DW
help
This enables support for the Rockchip SD/MMM controller, which is
based on Designware IP. The device is compatible with at least
SD 3.0, SDIO 3.0 and MMC 4.5 and supports common eMMC chips as well
as removeable SD and micro-SD cards.
+config MMC_DW_SOCFPGA
+ bool "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
+ depends on ARCH_SOCFPGA
+ depends on MMC_DW
+ default y
+ help
+ This selects support for Altera SOCFPGA specific extensions to the
+ Synopsys DesignWare Memory Card Interface driver. Select this option
+ for platforms based on Altera SOCFPGA.
+
+config MMC_MXC
+ bool "Freescale i.MX21/27/31 or MPC512x Multimedia Card support"
+ help
+ This selects the Freescale i.MX21, i.MX27, i.MX31 or MPC512x
+ Multimedia Card Interface. If you have an i.MX or MPC512x platform
+ with a Multimedia Card slot, say Y here.
+
+ If unsure, say N.
+
+config MMC_MXS
+ bool "Freescale MXS Multimedia Card Interface support"
+ help
+ This selects the Freescale SSP MMC controller found on MXS based
+ platforms like mx23/28.
+
+ If unsure, say N.
+
+config MMC_OMAP_HS
+ bool "TI OMAP High Speed Multimedia Card Interface support"
+ help
+ This selects the TI OMAP High Speed Multimedia card Interface.
+ If you have an omap2plus board with a Multimedia Card slot,
+ say Y here.
+
+ If unsure, say N.
+
config SH_SDHI
bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
depends on RMOBILE
config MMC_UNIPHIER
bool "UniPhier SD/MMC Host Controller support"
depends on ARCH_UNIPHIER
- depends on BLK
- select DM_MMC_OPS
+ depends on BLK && DM_MMC_OPS
+ depends on OF_CONTROL
help
This selects support for the SD/MMC Host Controller on UniPhier SoCs.
If unsure, say N.
+config MMC_SDHCI_CADENCE
+ bool "SDHCI support for the Cadence SD/SDIO/eMMC controller"
+ depends on BLK && DM_MMC_OPS
+ depends on MMC_SDHCI
+ depends on OF_CONTROL
+ help
+ This selects the Cadence SD/SDIO/eMMC driver.
+
+ If you have a controller with this interface, say Y here.
+
+ If unsure, say N.
+
config MMC_SDHCI_KONA
bool "SDHCI support on Broadcom KONA platform"
depends on MMC_SDHCI
If unsure, say N.
+config MMC_SDHCI_TEGRA
+ bool "SDHCI platform support for the Tegra SD/MMC Controller"
+ depends on TEGRA
+ default y
+ help
+ This selects the Tegra SD/MMC controller. If you have a Tegra
+ platform with SD or MMC devices, say Y here.
+
+ If unsure, say N.
+
+config MMC_SUNXI
+ bool "Allwinner sunxi SD/MMC Host Controller support"
+ depends on ARCH_SUNXI && !UART0_PORT_F
+ default y
+ help
+ This selects support for the SD/MMC Host Controller on
+ Allwinner sunxi SoCs.
+
endif
endmenu
+
+config SYS_FSL_ERRATUM_ESDHC111
+ bool
+
+config SYS_FSL_ERRATUM_ESDHC13
+ bool
+
+config SYS_FSL_ERRATUM_ESDHC135
+ bool
+
+config SYS_FSL_ERRATUM_ESDHC_A001
+ bool
obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o
obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
-obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
-obj-$(CONFIG_DWMMC) += dw_mmc.o
-obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
-obj-$(CONFIG_HIKEY_DWMMC) += hi6220_dw_mmc.o
+obj-$(CONFIG_MMC_DAVINCI) += davinci_mmc.o
+
+obj-$(CONFIG_MMC_DW) += dw_mmc.o
+obj-$(CONFIG_MMC_DW_EXYNOS) += exynos_dw_mmc.o
+obj-$(CONFIG_MMC_DW_K3) += hi6220_dw_mmc.o
+obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o
+obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o
obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
endif
obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
obj-$(CONFIG_MMC_SPI) += mmc_spi.o
-obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o
-obj-$(CONFIG_MXC_MMC) += mxcmmc.o
-obj-$(CONFIG_MXS_MMC) += mxsmmc.o
-obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
+obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o
+obj-$(CONFIG_MMC_MXC) += mxcmmc.o
+obj-$(CONFIG_MMC_MXS) += mxsmmc.o
obj-$(CONFIG_X86) += pci_mmc.o
obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
-obj-$(CONFIG_ROCKCHIP_DWMMC) += rockchip_dw_mmc.o
obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
ifdef CONFIG_BLK
endif
obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
-obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
-obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
-obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o
# SDHCI
obj-$(CONFIG_MMC_SDHCI) += sdhci.o
obj-$(CONFIG_MMC_SDHCI_BCM2835) += bcm2835_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o
obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o
obj-$(CONFIG_MMC_SDHCI_MV) += mv_sdhci.o
obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o
obj-$(CONFIG_MMC_SDHCI_SPEAR) += spear_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o
+
+obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
+obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
return 0;
}
-static void host_set_ios(struct mmc *dev)
+static int host_set_ios(struct mmc *dev)
{
struct pl180_mmc_host *host = dev->priv;
u32 sdi_clkcr;
writel(sdi_clkcr, &host->base->clock);
udelay(CLK_CHANGE_DELAY);
+
+ return 0;
}
static const struct mmc_ops arm_pl180_mmci_ops = {
bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
}
-static void bfin_sdh_set_ios(struct mmc *mmc)
+static int bfin_sdh_set_ios(struct mmc *mmc)
{
u16 cfg = 0;
u16 clk_ctl = 0;
}
bfin_write_SDH_CLK_CTL(clk_ctl);
sdh_set_clk(mmc->clock);
+
+ return 0;
}
static int bfin_sdh_init(struct mmc *mmc)
}
/* Set buswidth or clock as indicated by the GENERIC_MMC framework */
-static void dmmc_set_ios(struct mmc *mmc)
+static int dmmc_set_ios(struct mmc *mmc)
{
struct davinci_mmc *host = mmc->priv;
struct davinci_mmc_regs *regs = host->reg_base;
/* Set clock speed */
if (mmc->clock)
dmmc_set_clock(mmc, mmc->clock);
+
+ return 0;
}
static const struct mmc_ops dmmc_ops = {
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
#else
-static void dwmci_set_ios(struct mmc *mmc)
+static int dwmci_set_ios(struct mmc *mmc)
{
#endif
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
if (host->clksel)
host->clksel(host);
-#ifdef CONFIG_DM_MMC_OPS
+
return 0;
-#endif
}
static int dwmci_init(struct mmc *mmc)
}
#endif
-static void esdhc_set_ios(struct mmc *mmc)
+static int esdhc_set_ios(struct mmc *mmc)
{
struct fsl_esdhc_priv *priv = mmc->priv;
struct fsl_esdhc *regs = priv->esdhc_regs;
else if (mmc->bus_width == 8)
esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
+ return 0;
}
static int esdhc_init(struct mmc *mmc)
return ret;
}
-static void ftsdc010_set_ios(struct mmc *mmc)
+static int ftsdc010_set_ios(struct mmc *mmc)
{
struct ftsdc010_chip *chip = mmc->priv;
struct ftsdc010_mmc __iomem *regs = chip->regs;
setbits_le32(®s->bwr, FTSDC010_BWR_MODE_1BIT);
break;
}
+
+ return 0;
}
static int ftsdc010_init(struct mmc *mmc)
}
/* Entered into mmc structure during driver init */
-static void mci_set_ios(struct mmc *mmc)
+static int mci_set_ios(struct mmc *mmc)
{
struct atmel_mci_priv *priv = mmc->priv;
atmel_mci_t *mci = priv->mci;
writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
}
+
+ return 0;
}
/* Entered into mmc structure during driver init */
return ret;
}
-static void mmc_spi_set_ios(struct mmc *mmc)
+static int mmc_spi_set_ios(struct mmc *mmc)
{
struct spi_slave *spi = mmc->priv;
debug("%s: clock %u\n", __func__, mmc->clock);
if (mmc->clock)
spi_set_speed(spi, mmc->clock);
+ return 0;
}
static int mmc_spi_init_p(struct mmc *mmc)
mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
}
-static void mvebu_mmc_set_ios(struct mmc *mmc)
+static int mvebu_mmc_set_ios(struct mmc *mmc)
{
debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME,
mmc->bus_width, mmc->clock);
mvebu_mmc_set_bus(mmc->bus_width);
mvebu_mmc_set_clk(mmc->clock);
+
+ return 0;
}
/*
writel((prescaler << 4) | divider, &host->base->clk_rate);
}
-static void mxcmci_set_ios(struct mmc *mmc)
+static int mxcmci_set_ios(struct mmc *mmc)
{
struct mxcmci_host *host = mmc->priv;
if (mmc->bus_width == 4)
}
host->clock = mmc->clock;
+
+ return 0;
}
static int mxcmci_init(struct mmc *mmc)
return 0;
}
-static void mxsmmc_set_ios(struct mmc *mmc)
+static int mxsmmc_set_ios(struct mmc *mmc)
{
struct mxsmmc_priv *priv = mmc->priv;
struct mxs_ssp_regs *ssp_regs = priv->regs;
debug("MMC%d: Set %d bits bus width\n",
mmc->block_dev.devnum, mmc->bus_width);
+
+ return 0;
}
static int mxsmmc_init(struct mmc *mmc)
return 0;
}
-static void omap_hsmmc_set_ios(struct mmc *mmc)
+static int omap_hsmmc_set_ios(struct mmc *mmc)
{
struct hsmmc *mmc_base;
unsigned int dsor = 0;
while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for ics!\n", __func__);
- return;
+ return -ETIMEDOUT;
}
}
writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
+
+ return 0;
}
#ifdef OMAP_HSMMC_USE_GPIO
DECLARE_GLOBAL_DATA_PTR;
+static int pic32_sdhci_get_cd(struct sdhci_host *host)
+{
+ /* PIC32 SDHCI CD errata:
+ * - set CD_TEST and clear CD_TEST_INS bit
+ */
+ sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
+
+ return 0;
+}
+
+static const struct sdhci_ops pic32_sdhci_ops = {
+ .get_cd = pic32_sdhci_get_cd,
+};
+
static int pic32_sdhci_probe(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
host->ioaddr = ioremap(addr, size);
host->name = dev->name;
- host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_NO_CD;
+ host->quirks = SDHCI_QUIRK_NO_HISPD_BIT;
host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"bus-width", 4);
+ host->ops = &pic32_sdhci_ops;
ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
"clock-freq-min-max", f_min_max, 2);
return 0;
}
-static void pxa_mmc_set_ios(struct mmc *mmc)
+static int pxa_mmc_set_ios(struct mmc *mmc)
{
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
if (!mmc->clock) {
pxa_mmc_stop_clock(mmc);
- return;
+ return 0;
}
/* PXA3xx can do 26MHz with special settings. */
if (mmc->clock == 26000000) {
writel(0x7, ®s->clkrt);
- return;
+ return 0;
}
/* Set clock to the card the usual way. */
}
writel(pxa_mmc_clock, ®s->clkrt);
+
+ return 0;
}
static int pxa_mmc_init(struct mmc *mmc)
#include <libfdt.h>
#include <malloc.h>
#include <sdhci.h>
+#include <clk.h>
+DECLARE_GLOBAL_DATA_PTR;
/* 400KHz is max freq for card ID etc. Use that as min */
#define EMMC_MIN_FREQ 400000
struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
struct rockchip_sdhc *prv = dev_get_priv(dev);
struct sdhci_host *host = &prv->host;
- int ret;
+ int max_frequency, ret;
+ struct clk clk;
+
+
+ max_frequency = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "max-frequency", 0);
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (!ret) {
+ ret = clk_set_rate(&clk, max_frequency);
+ if (IS_ERR_VALUE(ret))
+ printf("%s clk set rate fail!\n", __func__);
+ } else {
+ printf("%s fail to get clk\n", __func__);
+ }
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
- ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ,
+ ret = sdhci_setup_cfg(&plat->cfg, host, max_frequency,
EMMC_MIN_FREQ);
host->mmc = &plat->mmc;
return ret;
}
-static void s3cmmc_set_ios(struct mmc *mmc)
+static int s3cmmc_set_ios(struct mmc *mmc)
{
struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
uint32_t divider = 0;
wide_bus = (mmc->bus_width == 4);
if (!mmc->clock)
- return;
+ return 0;
divider = DIV_ROUND_UP(get_PCLK(), mmc->clock);
if (divider)
writel(divider, &sdi_regs->sdipre);
mdelay(125);
+
+ return 0;
}
static int s3cmmc_init(struct mmc *mmc)
sdhci_writel(host, ctrl, SDHCI_CONTROL2);
}
+static void s5p_set_clock(struct sdhci_host *host, u32 div)
+{
+ /* ToDo : Use the Clock Framework */
+ set_mmc_clk(host->index, div);
+}
+
+static const struct sdhci_ops s5p_sdhci_ops = {
+ .set_clock = &s5p_set_clock,
+ .set_control_reg = &s5p_sdhci_set_control_reg,
+};
+
static int s5p_sdhci_core_init(struct sdhci_host *host)
{
host->name = S5P_NAME;
SDHCI_QUIRK_32BIT_DMA_ADDR |
SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
-
- host->set_control_reg = &s5p_sdhci_set_control_reg;
- host->set_clock = set_mmc_clk;
+ host->ops = &s5p_sdhci_ops;
if (host->bus_width == 8)
host->host_caps |= MMC_MODE_8BIT;
--- /dev/null
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <dm/device.h>
+#include <mmc.h>
+#include <sdhci.h>
+
+/* HRS - Host Register Set (specific to Cadence) */
+#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
+#define SDHCI_CDNS_HRS04_ACK BIT(26)
+#define SDHCI_CDNS_HRS04_RD BIT(25)
+#define SDHCI_CDNS_HRS04_WR BIT(24)
+#define SDHCI_CDNS_HRS04_RDATA_SHIFT 12
+#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8
+#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0
+
+/* SRS - Slot Register Set (SDHCI-compatible) */
+#define SDHCI_CDNS_SRS_BASE 0x200
+
+/* PHY */
+#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
+#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
+#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
+#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
+#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
+#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
+#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
+#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
+#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
+
+struct sdhci_cdns_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+ void __iomem *hrs_addr;
+};
+
+static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
+ u8 addr, u8 data)
+{
+ void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
+ u32 tmp;
+
+ tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
+ (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
+ writel(tmp, reg);
+
+ tmp |= SDHCI_CDNS_HRS04_WR;
+ writel(tmp, reg);
+
+ tmp &= ~SDHCI_CDNS_HRS04_WR;
+ writel(tmp, reg);
+}
+
+static void sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat)
+{
+ sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_HS, 4);
+ sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_DEFAULT, 4);
+ sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_LEGACY, 9);
+ sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_SDR, 2);
+ sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_DDR, 3);
+}
+
+static int sdhci_cdns_bind(struct udevice *dev)
+{
+ struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
+
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static int sdhci_cdns_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ fdt_addr_t base;
+ int ret;
+
+ base = dev_get_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
+ if (!plat->hrs_addr)
+ return -ENOMEM;
+
+ host->name = dev->name;
+ host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
+ host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
+
+ sdhci_cdns_phy_init(plat);
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
+ if (ret)
+ return ret;
+
+ upriv->mmc = &plat->mmc;
+ host->mmc = &plat->mmc;
+ host->mmc->priv = host;
+
+ return sdhci_probe(dev);
+}
+
+static const struct udevice_id sdhci_cdns_match[] = {
+ { .compatible = "socionext,uniphier-sd4hc" },
+ { .compatible = "cdns,sd4hc" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sdhci_cdns) = {
+ .name = "sdhci-cdns",
+ .id = UCLASS_MMC,
+ .of_match = sdhci_cdns_match,
+ .bind = sdhci_cdns_bind,
+ .probe = sdhci_cdns_probe,
+ .priv_auto_alloc_size = sizeof(struct sdhci_host),
+ .platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
+ .ops = &sdhci_ops,
+};
div >>= 1;
}
- if (host->set_clock)
- host->set_clock(host->index, div);
+ if (host->ops && host->ops->set_clock)
+ host->ops->set_clock(host, div);
clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
return;
}
- if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
- sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
-
pwr |= SDHCI_POWER_ON;
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
#else
-static void sdhci_set_ios(struct mmc *mmc)
+static int sdhci_set_ios(struct mmc *mmc)
{
#endif
u32 ctrl;
struct sdhci_host *host = mmc->priv;
- if (host->set_control_reg)
- host->set_control_reg(host);
+ if (host->ops && host->ops->set_control_reg)
+ host->ops->set_control_reg(host);
if (mmc->clock != host->clock)
sdhci_set_clock(mmc, mmc->clock);
ctrl &= ~SDHCI_CTRL_HISPD;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-#ifdef CONFIG_DM_MMC_OPS
+
return 0;
-#endif
}
static int sdhci_init(struct mmc *mmc)
sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
- if (host->quirks & SDHCI_QUIRK_NO_CD) {
-#if defined(CONFIG_PIC32_SDHCI)
- /* PIC32 SDHCI CD errata:
- * - set CD_TEST and clear CD_TEST_INS bit
- */
- sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
-#else
- unsigned int status;
-
- sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
- SDHCI_HOST_CONTROL);
-
- status = sdhci_readl(host, SDHCI_PRESENT_STATE);
- while ((!(status & SDHCI_CARD_PRESENT)) ||
- (!(status & SDHCI_CARD_STATE_STABLE)) ||
- (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
- status = sdhci_readl(host, SDHCI_PRESENT_STATE);
-#endif
- }
+ if (host->ops && host->ops->get_cd)
+ host->ops->get_cd(host);
/* Enable only interrupts served by the SD controller */
sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
cfg->voltages |= host->voltages;
cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
+
+ /* Since Host Controller Version3.0 */
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
- if (caps & SDHCI_CAN_DO_8BIT)
- cfg->host_caps |= MMC_MODE_8BIT;
+ if (!(caps & SDHCI_CAN_DO_8BIT))
+ cfg->host_caps &= ~MMC_MODE_8BIT;
+
+ /* Find out whether clock multiplier is supported */
+ caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
+ SDHCI_CLOCK_MUL_SHIFT;
}
if (host->host_caps)
cfg->host_caps |= host->host_caps;
-
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- /*
- * In case of Host Controller v3.00, find out whether clock
- * multiplier is supported.
- */
- if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
- caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
- host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
- SDHCI_CLOCK_MUL_SHIFT;
- }
-
return 0;
}
return ret;
}
-static void sh_mmcif_set_ios(struct mmc *mmc)
+static int sh_mmcif_set_ios(struct mmc *mmc)
{
struct sh_mmcif_host *host = mmc->priv;
host->bus_width = MMC_BUS_WIDTH_1;
debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
+
+ return 0;
}
static int sh_mmcif_init(struct mmc *mmc)
return ret;
}
-static void sh_sdhi_set_ios(struct mmc *mmc)
+static int sh_sdhi_set_ios(struct mmc *mmc)
{
int ret;
struct sh_sdhi_host *host = mmc_priv(mmc);
ret = sh_sdhi_clock_control(host, mmc->clock);
if (ret)
- return;
+ return -EINVAL;
if (mmc->bus_width == 4)
sh_sdhi_writew(host, SDHI_OPTION, ~OPT_BUS_WIDTH_1 &
sh_sdhi_readw(host, SDHI_OPTION));
debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
+
+ return 0;
}
static int sh_sdhi_initialize(struct mmc *mmc)
return 0;
}
-static void sunxi_mmc_set_ios(struct mmc *mmc)
+static int sunxi_mmc_set_ios(struct mmc *mmc)
{
struct sunxi_mmc_host *mmchost = mmc->priv;
/* Change clock first */
if (mmc->clock && mmc_config_clock(mmc) != 0) {
mmchost->fatal_err = 1;
- return;
+ return -EINVAL;
}
/* Change bus width */
writel(0x1, &mmchost->reg->width);
else
writel(0x0, &mmchost->reg->width);
+
+ return 0;
}
static int sunxi_mmc_core_init(struct mmc *mmc)
priv->clock = clock;
}
-static void tegra_mmc_set_ios(struct mmc *mmc)
+static int tegra_mmc_set_ios(struct mmc *mmc)
{
struct tegra_mmc_priv *priv = mmc->priv;
unsigned char ctrl;
writeb(ctrl, &priv->reg->hostctl);
debug("mmc_set_ios: hostctl = %08X\n", ctrl);
+
+ return 0;
}
static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
nand_chip.numchips = 1;
/* identify flash device */
- puts("NAND : ");
+ puts(": ");
if (mxs_flash_ident(mtd)) {
printf("Failed to identify\n");
return -1;
struct nand_chip *chip = mtd_to_nand(mtd);
struct omap_nand_info *info = nand_get_controller_data(chip);
- count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
- NULL, errloc);
+ count = decode_bch(info->control, NULL, SECTOR_BYTES,
+ read_ecc, calc_ecc, NULL, errloc);
if (count > 0) {
/* correct errors */
for (i = 0; i < count; i++) {
/* correct data only, not ecc bytes */
- if (errloc[i] < 8*512)
- data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
+ if (errloc[i] < SECTOR_BYTES << 3)
+ data[errloc[i] >> 3] ^= 1 << (errloc[i] & 7);
debug("corrected bitflip %u\n", errloc[i]);
#ifdef DEBUG
puts("read_ecc: ");
return 0;
}
/* Use priorty 0 to override the default if it happens to be linked in */
-SPL_LOAD_IMAGE_METHOD("sunxi SPI" 0, BOOT_DEVICE_SPI, spl_spi_load_image);
+SPL_LOAD_IMAGE_METHOD("sunxi SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image);
This driver implements 10/100 Mbps Ethernet and MAC layer for
Microchip PIC32 microcontrollers.
+config GMAC_ROCKCHIP
+ bool "Rockchip Synopsys Designware Ethernet MAC"
+ depends on DM_ETH && ETH_DESIGNWARE
+ help
+ This driver provides Rockchip SoCs network support based on the
+ Synopsys Designware driver.
+
endif # NETDEVICES
obj-$(CONFIG_FTMAC110) += ftmac110.o
obj-$(CONFIG_FTMAC100) += ftmac100.o
obj-$(CONFIG_GRETH) += greth.o
+obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
return 0;
}
-static void dw_adjust_link(struct eth_mac_regs *mac_p,
- struct phy_device *phydev)
+static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
+ struct phy_device *phydev)
{
u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
if (!phydev->link) {
printf("%s: No link.\n", phydev->dev->name);
- return;
+ return 0;
}
if (phydev->speed != 1000)
printf("Speed: %d, %s duplex%s\n", phydev->speed,
(phydev->duplex) ? "full" : "half",
(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
+
+ return 0;
}
static void _dw_eth_halt(struct dw_eth_dev *priv)
phy_shutdown(priv->phydev);
}
-static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
+int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
{
struct eth_mac_regs *mac_p = priv->mac_regs_p;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
return ret;
}
- dw_adjust_link(mac_p, priv->phydev);
+ ret = dw_adjust_link(priv, mac_p, priv->phydev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int designware_eth_enable(struct dw_eth_dev *priv)
+{
+ struct eth_mac_regs *mac_p = priv->mac_regs_p;
if (!priv->phydev->link)
return -EIO;
#ifndef CONFIG_DM_ETH
static int dw_eth_init(struct eth_device *dev, bd_t *bis)
{
- return _dw_eth_init(dev->priv, dev->enetaddr);
+ int ret;
+
+ ret = designware_eth_init(dev->priv, dev->enetaddr);
+ if (!ret)
+ ret = designware_eth_enable(dev->priv);
+
+ return ret;
}
static int dw_eth_send(struct eth_device *dev, void *packet, int length)
static int designware_eth_start(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct dw_eth_dev *priv = dev_get_priv(dev);
+ int ret;
- return _dw_eth_init(dev->priv, pdata->enetaddr);
+ ret = designware_eth_init(priv, pdata->enetaddr);
+ if (ret)
+ return ret;
+ ret = designware_eth_enable(priv);
+ if (ret)
+ return ret;
+
+ return 0;
}
-static int designware_eth_send(struct udevice *dev, void *packet, int length)
+int designware_eth_send(struct udevice *dev, void *packet, int length)
{
struct dw_eth_dev *priv = dev_get_priv(dev);
return _dw_eth_send(priv, packet, length);
}
-static int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct dw_eth_dev *priv = dev_get_priv(dev);
return _dw_eth_recv(priv, packetp);
}
-static int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
- int length)
+int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
{
struct dw_eth_dev *priv = dev_get_priv(dev);
return _dw_free_pkt(priv);
}
-static void designware_eth_stop(struct udevice *dev)
+void designware_eth_stop(struct udevice *dev)
{
struct dw_eth_dev *priv = dev_get_priv(dev);
return _dw_eth_halt(priv);
}
-static int designware_eth_write_hwaddr(struct udevice *dev)
+int designware_eth_write_hwaddr(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct dw_eth_dev *priv = dev_get_priv(dev);
return 0;
}
-static int designware_eth_probe(struct udevice *dev)
+int designware_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct dw_eth_dev *priv = dev_get_priv(dev);
return 0;
}
-static const struct eth_ops designware_eth_ops = {
+const struct eth_ops designware_eth_ops = {
.start = designware_eth_start,
.send = designware_eth_send,
.recv = designware_eth_recv,
.write_hwaddr = designware_eth_write_hwaddr,
};
-static int designware_eth_ofdata_to_platdata(struct udevice *dev)
+int designware_eth_ofdata_to_platdata(struct udevice *dev)
{
struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
#ifdef CONFIG_DM_GPIO
};
#ifdef CONFIG_DM_ETH
+int designware_eth_ofdata_to_platdata(struct udevice *dev);
+int designware_eth_probe(struct udevice *dev);
+extern const struct eth_ops designware_eth_ops;
+
struct dw_eth_pdata {
struct eth_pdata eth_pdata;
u32 reset_delays[3];
};
+
+int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr);
+int designware_eth_enable(struct dw_eth_dev *priv);
+int designware_eth_send(struct udevice *dev, void *packet, int length);
+int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp);
+int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
+ int length);
+void designware_eth_stop(struct udevice *dev);
+int designware_eth_write_hwaddr(struct udevice *dev);
#endif
#endif
obj-$(CONFIG_ARCH_P5040) += p5040.o
obj-$(CONFIG_ARCH_T1040) += t1040.o
obj-$(CONFIG_ARCH_T1042) += t1040.o
-obj-$(CONFIG_PPC_T1020) += t1040.o
-obj-$(CONFIG_PPC_T1022) += t1040.o
obj-$(CONFIG_ARCH_T1023) += t1024.o
obj-$(CONFIG_ARCH_T1024) += t1024.o
obj-$(CONFIG_ARCH_T2080) += t2080.o
--- /dev/null
+/*
+ * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Rockchip GMAC ethernet IP driver for U-Boot
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <phy.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3288.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include "designware.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Platform data for the gmac
+ *
+ * dw_eth_pdata: Required platform data for designware driver (must be first)
+ */
+struct gmac_rockchip_platdata {
+ struct dw_eth_pdata dw_eth_pdata;
+ int tx_delay;
+ int rx_delay;
+};
+
+static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
+{
+ struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+
+ pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "tx-delay", 0x30);
+ pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "rx-delay", 0x10);
+
+ return designware_eth_ofdata_to_platdata(dev);
+}
+
+static int gmac_rockchip_fix_mac_speed(struct dw_eth_dev *priv)
+{
+ struct rk3288_grf *grf;
+ int clk;
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = GMAC_CLK_SEL_2_5M;
+ break;
+ case 100:
+ clk = GMAC_CLK_SEL_25M;
+ break;
+ case 1000:
+ clk = GMAC_CLK_SEL_125M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->soc_con1,
+ GMAC_CLK_SEL_MASK << GMAC_CLK_SEL_SHIFT,
+ clk << GMAC_CLK_SEL_SHIFT);
+
+ return 0;
+}
+
+static int gmac_rockchip_probe(struct udevice *dev)
+{
+ struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+ struct rk3288_grf *grf;
+ struct clk clk;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return ret;
+
+ /* Since mac_clk is fed by an external clock we can use 0 here */
+ ret = clk_set_rate(&clk, 0);
+ if (ret)
+ return ret;
+
+ /* Set to RGMII mode */
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->soc_con1,
+ RMII_MODE_MASK << RMII_MODE_SHIFT |
+ GMAC_PHY_INTF_SEL_MASK << GMAC_PHY_INTF_SEL_SHIFT,
+ GMAC_PHY_INTF_SEL_RGMII << GMAC_PHY_INTF_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->soc_con3,
+ RXCLK_DLY_ENA_GMAC_MASK << RXCLK_DLY_ENA_GMAC_SHIFT |
+ TXCLK_DLY_ENA_GMAC_MASK << TXCLK_DLY_ENA_GMAC_SHIFT |
+ CLK_RX_DL_CFG_GMAC_MASK << CLK_RX_DL_CFG_GMAC_SHIFT |
+ CLK_TX_DL_CFG_GMAC_MASK << CLK_TX_DL_CFG_GMAC_SHIFT,
+ RXCLK_DLY_ENA_GMAC_ENABLE << RXCLK_DLY_ENA_GMAC_SHIFT |
+ TXCLK_DLY_ENA_GMAC_ENABLE << TXCLK_DLY_ENA_GMAC_SHIFT |
+ pdata->rx_delay << CLK_RX_DL_CFG_GMAC_SHIFT |
+ pdata->tx_delay << CLK_TX_DL_CFG_GMAC_SHIFT);
+
+ return designware_eth_probe(dev);
+}
+
+static int gmac_rockchip_eth_start(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct dw_eth_dev *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = designware_eth_init(priv, pdata->enetaddr);
+ if (ret)
+ return ret;
+ ret = gmac_rockchip_fix_mac_speed(priv);
+ if (ret)
+ return ret;
+ ret = designware_eth_enable(priv);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+const struct eth_ops gmac_rockchip_eth_ops = {
+ .start = gmac_rockchip_eth_start,
+ .send = designware_eth_send,
+ .recv = designware_eth_recv,
+ .free_pkt = designware_eth_free_pkt,
+ .stop = designware_eth_stop,
+ .write_hwaddr = designware_eth_write_hwaddr,
+};
+
+static const struct udevice_id rockchip_gmac_ids[] = {
+ { .compatible = "rockchip,rk3288-gmac" },
+ { }
+};
+
+U_BOOT_DRIVER(eth_gmac_rockchip) = {
+ .name = "gmac_rockchip",
+ .id = UCLASS_ETH,
+ .of_match = rockchip_gmac_ids,
+ .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
+ .probe = gmac_rockchip_probe,
+ .ops = &gmac_rockchip_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
+ .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
static int xilinxphy_of_init(struct phy_device *phydev)
{
- struct udevice *dev = (struct udevice *)&phydev->dev;
u32 phytype;
debug("%s\n", __func__);
- phytype = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "phy-type", -1);
+ phytype = fdtdec_get_int(gd->fdt_blob, phydev->dev->of_offset,
+ "phy-type", -1);
if (phytype == XAE_PHY_TYPE_1000BASE_X)
phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <clk.h>
#include <common.h>
#include <dm.h>
#include <net.h>
struct phy_device *phydev;
int phy_of_handle;
struct mii_dev *bus;
+#ifdef CONFIG_CLK_ZYNQMP
+ struct clk clk;
+#endif
};
-static inline int mdio_wait(struct zynq_gem_regs *regs)
-{
- u32 timeout = 20000;
-
- /* Wait till MDIO interface is ready to accept a new transaction. */
- while (--timeout) {
- if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
- break;
- WATCHDOG_RESET();
- }
-
- if (!timeout) {
- printf("%s: Timeout\n", __func__);
- return 1;
- }
-
- return 0;
-}
-
static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
u32 op, u16 *data)
{
u32 mgtcr;
struct zynq_gem_regs *regs = priv->iobase;
+ int err;
- if (mdio_wait(regs))
- return 1;
+ err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
+ true, 20000, true);
+ if (err)
+ return err;
/* Construct mgtcr mask for the operation */
mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
/* Write mgtcr and wait for completion */
writel(mgtcr, ®s->phymntnc);
- if (mdio_wait(regs))
- return 1;
+ err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
+ true, 20000, true);
+ if (err)
+ return err;
if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
*data = readl(®s->phymntnc);
/* Change the rclk and clk only not using EMIO interface */
if (!priv->emio)
+#ifndef CONFIG_CLK_ZYNQMP
zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
ZYNQ_GEM_BASEADDR0, clk_rate);
+#else
+ ret = clk_set_rate(&priv->clk, clk_rate);
+ if (IS_ERR_VALUE(ret))
+ return -1;
+#endif
setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);
priv->tx_bd = (struct emac_bd *)bd_space;
priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
+#ifdef CONFIG_CLK_ZYNQMP
+ ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get clock\n");
+ return -EINVAL;
+ }
+#endif
+
priv->bus = mdio_alloc();
priv->bus->read = zynq_gem_miiphy_read;
priv->bus->write = zynq_gem_miiphy_write;
if PCI
config DM_PCI
- bool "Enable driver mode for PCI"
+ bool "Enable driver model for PCI"
depends on DM
help
Use driver model for PCI. Driver model is the new method for
0, 0, 0, 0};
static const unsigned ether_rmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 39,
41, 42, 45};
-static const int ether_rmii_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
+static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1};
static const unsigned i2c0_pins[] = {63, 64};
static const int i2c0_muxvals[] = {0, 0};
static const unsigned i2c1_pins[] = {65, 66};
return rc;
if (ver != 0x05)
- return -1;
+ return -EINVAL;
return 0;
}
ver &= 0x0f;
if (ver != 0x1)
- return -1;
+ return -EINVAL;
/* Mask all interrupts */
for (i = AXP209_IRQ_ENABLE1; i <= AXP209_IRQ_ENABLE5; i++) {
struct power_battery *p_bat = bat->pbat;
if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450))
- return -1;
+ return -EINVAL;
return 0;
}
COMPAT_SAMSUNG_EXYNOS_TMU);
if (node < 0) {
debug("EXYNOS_TMU: No node for tmu in device tree\n");
- return -1;
+ return -ENODEV;
}
/*
addr = fdtdec_get_addr(blob, node, "reg");
if (addr == FDT_ADDR_T_NONE) {
debug("%s: Missing tmu-base\n", __func__);
- return -1;
+ return -ENODEV;
}
info->tmu_base = (struct exynos5_tmu_reg *)addr;
if (error) {
debug("fail to get tmu node properties\n");
- return -1;
+ return -EINVAL;
}
#else
/* Non DT support may never be added. Just in case */
- return -1;
+ return -ENODEV;
#endif
return 0;
if (pmic_probe(p)) {
puts("Can't find max17042 fuel gauge\n");
- return -1;
+ return -ENODEV;
}
ret |= pmic_reg_read(p, MAX17042_VFSOC, &val);
if (pmic_probe(p)) {
puts("Can't find max17042 fuel gauge\n");
- return -1;
+ return -ENODEV;
}
ret |= pmic_reg_read(p, MAX17042_STATUS, &val);
if (pmic_probe(p)) {
puts("Can't find max77693 fuel gauge\n");
- return -1;
+ return -ENODEV;
}
ret = max77693_get_soc(&pb->bat->state_of_chrg);
if (pmic_probe(p)) {
puts("Can't find max77693 fuel gauge\n");
- return -1;
+ return -ENODEV;
}
ret = pmic_reg_read(p, MAX77693_STATUS, &val);
unsigned int val;
if (pmic_probe(p))
- return -1;
+ return -ENODEV;
/* unlock write capability */
val = MAX77693_CHG_UNLOCK;
pmic_reg_read(p, MAX77693_CHG_CNFG_00, &val);
val &= ~0x01;
pmic_reg_write(p, MAX77693_CHG_CNFG_00, val);
- return -1;
+ return -ENOTSUPP;
}
if (current < CHARGER_MIN_CURRENT || current > CHARGER_MAX_CURRENT) {
printf("%s: Wrong charge current: %d [mA]\n",
__func__, current);
- return -1;
+ return -EINVAL;
}
/* set charging current */
unsigned int val;
if (pmic_probe(p))
- return -1;
+ return -ENODEV;
pmic_reg_read(p, MAX77693_CHG_INT_OK, &val);
u8 val = 0;
#if defined(CONFIG_DRA7XX)
+ int ret;
/*
* Currently valid for the dra7xx_evm board:
* Set TPS659038 LDO1 to 3.0 V
*/
val = LDO_VOLT_3V0;
- if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_VOLTAGE, val)) {
+ ret = palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_VOLTAGE, val);
+ if (ret) {
printf("tps65903x: could not set LDO1 voltage.\n");
- return 1;
+ return ret;
}
/* TURN ON LDO1 */
val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE;
- if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_CTRL, val)) {
+ ret = palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_CTRL, val);
+ if (ret) {
printf("tps65903x: could not turn on LDO1.\n");
- return 1;
+ return ret;
}
return 0;
#else
int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
{
if (check_reg(p, reg))
- return -1;
+ return -EINVAL;
hi6553_writeb(reg, (uint8_t)val);
int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
{
if (check_reg(p, reg))
- return -1;
+ return -EINVAL;
*val = (u32)hi6553_readb(reg);
if (ldo < 1 || ldo > 26) {
printf("%s: %d is wrong ldo number\n", __func__, ldo);
- return -1;
+ return -EINVAL;
}
adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
hex = max77686_ldo_volt2hex(ldo, uV);
if (!hex)
- return -1;
+ return -EINVAL;
ret = pmic_reg_read(p, adr, &val);
if (ret)
if (ldo < 1 || 26 < ldo) {
printf("%s: %d is wrong ldo number\n", __func__, ldo);
- return -1;
+ return -EINVAL;
}
adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
if (mode == 0xff) {
printf("%s: %d is not supported on LDO%d\n",
__func__, opmode, ldo);
- return -1;
+ return -ENOTSUPP;
}
ret = pmic_reg_read(p, adr, &val);
size = ARRAY_SIZE(max77686_buck_addr);
if (buck >= size) {
printf("%s: %d is wrong buck number\n", __func__, buck);
- return -1;
+ return -EINVAL;
}
adr = max77686_buck_addr[buck];
if (mode == 0xff) {
printf("%s: %d is not supported on BUCK%d\n",
__func__, opmode, buck);
- return -1;
+ return -ENOTSUPP;
}
ret = pmic_reg_read(p, adr, &val);
if (node < 0) {
debug("PMIC: No node for PMIC Chip in device tree\n");
debug("node = %d\n", node);
- return -1;
+ return -ENODEV;
}
parent = fdt_parent_offset(blob, node);
if (parent < 0) {
debug("%s: Cannot find node parent\n", __func__);
- return -1;
+ return -ENODEV;
}
/* tmp since p->bus is unsigned */
tmp = i2c_get_bus_num_fdt(parent);
if (tmp < 0) {
debug("%s: Cannot find I2C bus\n", __func__);
- return -1;
+ return -ENODEV;
}
p->bus = tmp;
p->hw.i2c.addr = fdtdec_get_int(blob, node, "reg", 9);
u32 val = 0;
if (pmic_probe(p))
- return -1;
+ return -ENODEV;
if (state == PMIC_CHARGER_DISABLE) {
puts("Disable the charger.\n");
val &= ~(MBCHOSTEN | VCHGR_FC);
pmic_reg_write(p, MAX8997_REG_MBCCTRL2, val);
- return -1;
+ return -ENOTSUPP;
}
if (current < CHARGER_MIN_CURRENT || current > CHARGER_MAX_CURRENT) {
printf("%s: Wrong charge current: %d [mA]\n",
__func__, current);
- return -1;
+ return -EINVAL;
}
fc = (current - CHARGER_MIN_CURRENT) / CHARGER_CURRENT_RESOLUTION;
u32 val;
if (pmic_probe(p))
- return -1;
+ return -ENODEV;
pmic_reg_read(p, MAX8997_REG_STATUS4, &val);
if (reg >= p->number_of_regs) {
printf("<reg num> = %d is invalid. Should be less than %d\n",
reg, p->number_of_regs);
- return -1;
+ return -EINVAL;
}
return 0;
u32 val;
if (pmic_reg_read(p, reg, &val))
- return -1;
+ return -ENOTSUPP;
if (on)
val |= out;
val &= ~out;
if (pmic_reg_write(p, reg, val))
- return -1;
+ return -ENOTSUPP;
return 0;
}
if (!p) {
puts("Wrong PMIC name!\n");
- return -1;
+ return -ENODEV;
}
pmic_show_info(p);
unsigned char buf[4] = { 0 };
if (check_reg(p, reg))
- return -1;
+ return -EINVAL;
I2C_SET_BUS(p->bus);
break;
default:
printf("%s: invalid tx_num: %d", __func__, pmic_i2c_tx_num);
- return -1;
+ return -EINVAL;
}
- if (i2c_write(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num))
- return -1;
-
- return 0;
+ return i2c_write(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num);
}
int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
{
unsigned char buf[4] = { 0 };
u32 ret_val = 0;
+ int ret;
if (check_reg(p, reg))
- return -1;
+ return -EINVAL;
I2C_SET_BUS(p->bus);
- if (i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num))
- return -1;
+ ret = i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num);
+ if (ret)
+ return ret;
switch (pmic_i2c_tx_num) {
case 3:
break;
default:
printf("%s: invalid tx_num: %d", __func__, pmic_i2c_tx_num);
- return -1;
+ return -EINVAL;
}
memcpy(val, &ret_val, sizeof(ret_val));
debug("Bus: %d PMIC:%s probed!\n", p->bus, p->name);
if (i2c_probe(pmic_i2c_addr)) {
printf("Can't find PMIC:%s\n", p->name);
- return -1;
+ return -ENODEV;
}
return 0;
p->hw.spi.mode);
if (!slave)
- return -1;
+ return -ENODEV;
}
if (check_reg(p, reg))
- return -1;
+ return -EINVAL;
if (spi_claim_bus(slave))
- return -1;
+ return -EBUSY;
pmic_tx = p->hw.spi.prepare_tx(reg, val, write);
err:
spi_release_bus(slave);
- return -1;
+ return -ENOTSUPP;
}
int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
{
- if (pmic_reg(p, reg, &val, 1))
- return -1;
-
- return 0;
+ return pmic_reg(p, reg, &val, 1);
}
int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
{
- if (pmic_reg(p, reg, val, 0))
- return -1;
-
- return 0;
+ return pmic_reg(p, reg, val, 0);
}
ctrl1 = tps6586x_read(SUPPLY_CONTROL1);
ctrl2 = tps6586x_read(SUPPLY_CONTROL2);
if (ctrl1 == -1 || ctrl2 == -1)
- return -1;
+ return -ENOTSUPP;
/* Figure out whether V1 or V2 is selected */
is_v2 = (ctrl1 | ctrl2) & CTRL_SM0_SUPPLY2;
*sm0 = tps6586x_read(is_v2 ? SM0_VOLTAGE_V2 : SM0_VOLTAGE_V1);
*sm1 = tps6586x_read(is_v2 ? SM1_VOLTAGE_V2 : SM1_VOLTAGE_V1);
if (*sm0 == -1 || *sm1 == -1)
- return -1;
+ return -ENOTSUPP;
return 0;
}
/* write v1, v2 and rate, then trigger */
if (tps6586x_write(reg, buff, 3) ||
tps6586x_write(SUPPLY_CONTROL1, &control_bit, 1))
- return -1;
+ return -ENOTSUPP;
return 0;
}
/* get current voltage settings */
if (read_voltages(&sm0, &sm1)) {
debug("%s: Cannot read voltage settings\n", __func__);
- return -1;
+ return -EINVAL;
}
/*
if (min_sm0_over_sm1 != -1 && sm0 < sm1 + min_sm0_over_sm1) {
debug("%s: SM0 is %d, SM1 is %d, but min_sm0_over_sm1 is %d\n",
__func__, sm0, sm1, min_sm0_over_sm1);
- return -1;
+ return -EINVAL;
}
/*
}
debug("%d-%d %d-%d done\n", sm0, sm0_target, sm1, sm1_target);
- return bad ? -1 : 0;
+ return bad ? -EINVAL : 0;
}
int tps6586x_init(struct udevice *dev)
bool "Enable PCF2127 driver"
depends on DM_RTC
help
- Enable pcf2127 driver which provides rtc get and set function
+ The PCF2127 is a CMOS Real Time Clock (RTC) and calendar with an integrated
+ Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz
+ crystal optimized for very high accuracy and very low power consumption. The PCF2127
+ has a selectable I2C-bus or SPI-bus, a backup battery switch-over circuit, a
+ programmable watchdog function, a timestamp function, and many other features.
endmenu
#include <i2c.h>
#include <rtc.h>
-#define PCF2127_REG_CTRL1 (0x00)
-#define PCF2127_REG_CTRL2 (0x01)
-#define PCF2127_REG_CTRL3 (0x02)
-#define PCF2127_REG_SC (0x03) /* datetime */
-#define PCF2127_REG_MN (0x04)
-#define PCF2127_REG_HR (0x05)
-#define PCF2127_REG_DM (0x06)
-#define PCF2127_REG_DW (0x07)
-#define PCF2127_REG_MO (0x08)
-#define PCF2127_REG_YR (0x09)
+#define PCF2127_REG_CTRL1 0x00
+#define PCF2127_REG_CTRL2 0x01
+#define PCF2127_REG_CTRL3 0x02
+#define PCF2127_REG_SC 0x03
+#define PCF2127_REG_MN 0x04
+#define PCF2127_REG_HR 0x05
+#define PCF2127_REG_DM 0x06
+#define PCF2127_REG_DW 0x07
+#define PCF2127_REG_MO 0x08
+#define PCF2127_REG_YR 0x09
static int pcf2127_rtc_set(struct udevice *dev, const struct rtc_time *tm)
{
uchar buf[8];
- int i = 0;
+ int i = 0, ret;
/* start register address */
buf[i++] = PCF2127_REG_SC;
buf[i++] = bin2bcd(tm->tm_year % 100);
/* write register's data */
- if (dm_i2c_write(dev, PCF2127_REG_CTRL1, buf, sizeof(buf)) < 0)
- return -1;
+ ret = dm_i2c_write(dev, PCF2127_REG_CTRL1, buf, sizeof(buf));
- return 0;
+ return ret;
}
static int pcf2127_rtc_get(struct udevice *dev, struct rtc_time *tm)
{
- int rel = 0;
+ int ret = 0;
uchar buf[10] = { PCF2127_REG_CTRL1 };
- if (dm_i2c_write(dev, PCF2127_REG_CTRL1, buf, 1) < 0)
- return -1;
- if (dm_i2c_read(dev, PCF2127_REG_CTRL1, buf, sizeof(buf)) < 0)
- return -1;
+ ret = dm_i2c_write(dev, PCF2127_REG_CTRL1, buf, 1);
+ if (ret < 0)
+ return ret;
+ ret = dm_i2c_read(dev, PCF2127_REG_CTRL1, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
if (buf[PCF2127_REG_CTRL3] & 0x04)
puts("### Warning: RTC Low Voltage - date/time not reliable\n");
tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
- return rel;
+ return ret;
}
static int pcf2127_rtc_reset(struct udevice *dev)
{
/*Doing nothing here*/
+
return 0;
}
depends on DM_SERIAL && SPL_OF_PLATDATA
help
Select this to enable a debug UART for Rockchip devices when using
- CONFIG_OF_PLATDATA (i.e. a compiled-in device tree replacemenmt).
+ CONFIG_SPL_OF_PLATDATA (i.e. a compiled-in device tree replacemenmt).
This uses the ns16550 driver, converting the platdata from of-platdata
to the ns16550 format.
obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
-obj-$(CONFIG_CF_QSPI) += cf_qspi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
-obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
#include <linux/errno.h>
#include <wait_bit.h>
#include <spi.h>
+#include <bouncebuf.h>
#include "cadence_qspi.h"
#define CQSPI_REG_POLL_US 1 /* 1us */
{
unsigned int remaining = n_rx;
unsigned int bytes_to_read = 0;
+ struct bounce_buffer bb;
+ u8 *bb_rxbuf;
int ret;
writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
writel(CQSPI_REG_INDIRECTRD_START,
plat->regbase + CQSPI_REG_INDIRECTRD);
+ ret = bounce_buffer_start(&bb, (void *)rxbuf, n_rx, GEN_BB_WRITE);
+ if (ret)
+ return ret;
+ bb_rxbuf = bb.bounce_buffer;
+
while (remaining > 0) {
ret = cadence_qspi_wait_for_data(plat);
if (ret < 0) {
bytes_to_read *= CQSPI_FIFO_WIDTH;
bytes_to_read = bytes_to_read > remaining ?
remaining : bytes_to_read;
- /* Handle non-4-byte aligned access to avoid data abort. */
- if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
- readsb(plat->ahbbase, rxbuf, bytes_to_read);
- else
- readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
- rxbuf += bytes_to_read;
+ readsl(plat->ahbbase, bb_rxbuf, bytes_to_read >> 2);
+ if (bytes_to_read % 4)
+ readsb(plat->ahbbase,
+ bb_rxbuf + rounddown(bytes_to_read, 4),
+ bytes_to_read % 4);
+
+ bb_rxbuf += bytes_to_read;
remaining -= bytes_to_read;
bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
}
/* Clear indirect completion status */
writel(CQSPI_REG_INDIRECTRD_DONE,
plat->regbase + CQSPI_REG_INDIRECTRD);
+ bounce_buffer_stop(&bb);
return 0;
/* Cancel the indirect read */
writel(CQSPI_REG_INDIRECTRD_CANCEL,
plat->regbase + CQSPI_REG_INDIRECTRD);
+ bounce_buffer_stop(&bb);
return ret;
}
unsigned int remaining = n_tx;
unsigned int write_bytes;
int ret;
+ struct bounce_buffer bb;
+ u8 *bb_txbuf;
+
+ /*
+ * Handle non-4-byte aligned accesses via bounce buffer to
+ * avoid data abort.
+ */
+ ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ);
+ if (ret)
+ return ret;
+ bb_txbuf = bb.bounce_buffer;
/* Configure the indirect read transfer bytes */
writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
while (remaining > 0) {
write_bytes = remaining > page_size ? page_size : remaining;
- /* Handle non-4-byte aligned access to avoid data abort. */
- if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
- writesb(plat->ahbbase, txbuf, write_bytes);
- else
- writesl(plat->ahbbase, txbuf, write_bytes >> 2);
+ writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
+ if (write_bytes % 4)
+ writesb(plat->ahbbase,
+ bb_txbuf + rounddown(write_bytes, 4),
+ write_bytes % 4);
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
CQSPI_REG_SDRAMLEVEL_WR_MASK <<
goto failwr;
}
- txbuf += write_bytes;
+ bb_txbuf += write_bytes;
remaining -= write_bytes;
}
printf("Indirect write completion error (%i)\n", ret);
goto failwr;
}
+ bounce_buffer_stop(&bb);
/* Clear indirect completion status */
writel(CQSPI_REG_INDIRECTWR_DONE,
/* Cancel the indirect write */
writel(CQSPI_REG_INDIRECTWR_CANCEL,
plat->regbase + CQSPI_REG_INDIRECTWR);
+ bounce_buffer_stop(&bb);
return ret;
}
+++ /dev/null
-/*
- * Freescale Coldfire Queued SPI driver
- *
- * NOTE:
- * This driver is written to transfer 8 bit at-a-time and uses the dedicated
- * SPI slave select pins as bit-banged GPIO to work with spi_flash subsystem.
- *
- * Copyright (C) 2011 Ruggedcom, Inc.
- * Richard Retanubun (richardretanubun@freescale.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <spi.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, slave)
-
-struct cf_qspi_slave {
- struct spi_slave slave; /* Specific bus:cs ID for each device */
- qspi_t *regs; /* Pointer to SPI controller registers */
- u16 qmr; /* QMR: Queued Mode Register */
- u16 qwr; /* QWR: Queued Wrap Register */
- u16 qcr; /* QCR: Queued Command Ram */
-};
-
-/* Register write wrapper functions */
-static void write_qmr(volatile qspi_t *qspi, u16 val) { qspi->mr = val; }
-static void write_qdlyr(volatile qspi_t *qspi, u16 val) { qspi->dlyr = val; }
-static void write_qwr(volatile qspi_t *qspi, u16 val) { qspi->wr = val; }
-static void write_qir(volatile qspi_t *qspi, u16 val) { qspi->ir = val; }
-static void write_qar(volatile qspi_t *qspi, u16 val) { qspi->ar = val; }
-static void write_qdr(volatile qspi_t *qspi, u16 val) { qspi->dr = val; }
-/* Register read wrapper functions */
-static u16 read_qdlyr(volatile qspi_t *qspi) { return qspi->dlyr; }
-static u16 read_qwr(volatile qspi_t *qspi) { return qspi->wr; }
-static u16 read_qir(volatile qspi_t *qspi) { return qspi->ir; }
-static u16 read_qdr(volatile qspi_t *qspi) { return qspi->dr; }
-
-/* These call points may be different for each ColdFire CPU */
-extern void cfspi_port_conf(void);
-static void cfspi_cs_activate(uint bus, uint cs, uint cs_active_high);
-static void cfspi_cs_deactivate(uint bus, uint cs, uint cs_active_high);
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- return 0;
-}
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
-__attribute__((weak))
-void spi_init(void)
-{
- cfspi_port_conf();
-}
-
-__attribute__((weak))
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
-
- cfspi_cs_activate(slave->bus, slave->cs, !(dev->qwr & QSPI_QWR_CSIV));
-}
-
-__attribute__((weak))
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
-
- cfspi_cs_deactivate(slave->bus, slave->cs, !(dev->qwr & QSPI_QWR_CSIV));
-}
-
-__attribute__((weak))
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- /* Only 1 bus and 4 chipselect per controller */
- if (bus == 0 && (cs >= 0 && cs < 4))
- return 1;
- else
- return 0;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
-
- free(dev);
-}
-
-/* Translate information given by spi_setup_slave to members of cf_qspi_slave */
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct cf_qspi_slave *dev = NULL;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- dev = spi_alloc_slave(struct cf_qspi_slave, bus, cs);
- if (!dev)
- return NULL;
-
- /* Initialize to known value */
- dev->regs = (qspi_t *)MMAP_QSPI;
- dev->qmr = 0;
- dev->qwr = 0;
- dev->qcr = 0;
-
-
- /* Map max_hz to QMR[BAUD] */
- if (max_hz == 0) /* Go as fast as possible */
- dev->qmr = 2u;
- else /* Get the closest baud rate */
- dev->qmr = clamp(((gd->bus_clk >> 2) + max_hz - 1)/max_hz,
- 2lu, 255lu);
-
- /* Map mode to QMR[CPOL] and QMR[CPHA] */
- if (mode & SPI_CPOL)
- dev->qmr |= QSPI_QMR_CPOL;
-
- if (mode & SPI_CPHA)
- dev->qmr |= QSPI_QMR_CPHA;
-
- /* Hardcode bit length to 8 bit per transter */
- dev->qmr |= QSPI_QMR_BITS_8;
-
- /* Set QMR[MSTR] to enable QSPI as master */
- dev->qmr |= QSPI_QMR_MSTR;
-
- /*
- * Set QCR and QWR to default values for spi flash operation.
- * If more custom QCR and QRW are needed, overload mode variable
- */
- dev->qcr = (QSPI_QDR_CONT | QSPI_QDR_BITSE);
-
- if (!(mode & SPI_CS_HIGH))
- dev->qwr |= QSPI_QWR_CSIV;
-
- return &dev->slave;
-}
-
-/* Transfer 8 bit at a time */
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
- volatile qspi_t *qspi = dev->regs;
- u8 *txbuf = (u8 *)dout;
- u8 *rxbuf = (u8 *)din;
- u32 count = DIV_ROUND_UP(bitlen, 8);
- u32 n, i = 0;
-
- /* Sanitize arguments */
- if (slave == NULL) {
- printf("%s: NULL slave ptr\n", __func__);
- return -1;
- }
-
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
-
- /* There is something to send, lets process it. spi_xfer is also called
- * just to toggle chip select, so bitlen of 0 is valid */
- if (count > 0) {
- /*
- * NOTE: Since chip select is driven as a bit-bang-ed GPIO
- * using spi_cs_activate() and spi_cs_deactivate(),
- * the chip select settings inside the controller
- * (i.e. QCR[CONT] and QWR[CSIV]) are moot. The bits are set to
- * keep the controller settings consistent with the actual
- * operation of the bus.
- */
-
- /* Write the slave device's settings for the controller.*/
- write_qmr(qspi, dev->qmr);
- write_qwr(qspi, dev->qwr);
-
- /* Limit transfer to 16 at a time */
- n = min(count, 16u);
- do {
- /* Setup queue end point */
- write_qwr(qspi, ((read_qwr(qspi) & QSPI_QWR_ENDQP_MASK)
- | QSPI_QWR_ENDQP((n-1))));
-
- /* Write Command RAM */
- write_qar(qspi, QSPI_QAR_CMD);
- for (i = 0; i < n; ++i)
- write_qdr(qspi, dev->qcr);
-
- /* Write TxBuf, if none given, fill with ZEROes */
- write_qar(qspi, QSPI_QAR_TRANS);
- if (txbuf) {
- for (i = 0; i < n; ++i)
- write_qdr(qspi, *txbuf++);
- } else {
- for (i = 0; i < n; ++i)
- write_qdr(qspi, 0);
- }
-
- /* Clear QIR[SPIF] by writing a 1 to it */
- write_qir(qspi, read_qir(qspi) | QSPI_QIR_SPIF);
- /* Set QDLYR[SPE] to start sending */
- write_qdlyr(qspi, read_qdlyr(qspi) | QSPI_QDLYR_SPE);
-
- /* Poll QIR[SPIF] for transfer completion */
- while ((read_qir(qspi) & QSPI_QIR_SPIF) != 1)
- udelay(1);
-
- /* If given read RxBuf, load data to it */
- if (rxbuf) {
- write_qar(qspi, QSPI_QAR_RECV);
- for (i = 0; i < n; ++i)
- *rxbuf++ = read_qdr(qspi);
- }
-
- /* Decrement count */
- count -= n;
- } while (count);
- }
-
- if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
-
- return 0;
-}
-
-/* Each MCF CPU may have different pin assignments for chip selects. */
-#if defined(CONFIG_M5271)
-/* Assert chip select, val = [1|0] , dir = out, mode = GPIO */
-void cfspi_cs_activate(uint bus, uint cs, uint cs_active_high)
-{
- debug("%s: bus %d cs %d cs_active_high %d\n",
- __func__, bus, cs, cs_active_high);
-
- switch (cs) {
- case 0: /* QSPI_CS[0] = PQSPI[3] */
- if (cs_active_high)
- mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x08);
- else
- mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xF7);
-
- mbar_writeByte(MCF_GPIO_PDDR_QSPI,
- mbar_readByte(MCF_GPIO_PDDR_QSPI) | 0x08);
-
- mbar_writeByte(MCF_GPIO_PAR_QSPI,
- mbar_readByte(MCF_GPIO_PAR_QSPI) & 0xDF);
- break;
- case 1: /* QSPI_CS[1] = PQSPI[4] */
- if (cs_active_high)
- mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x10);
- else
- mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xEF);
-
- mbar_writeByte(MCF_GPIO_PDDR_QSPI,
- mbar_readByte(MCF_GPIO_PDDR_QSPI) | 0x10);
-
- mbar_writeByte(MCF_GPIO_PAR_QSPI,
- mbar_readByte(MCF_GPIO_PAR_QSPI) & 0x3F);
- break;
- case 2: /* QSPI_CS[2] = PTIMER[7] */
- if (cs_active_high)
- mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x80);
- else
- mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0x7F);
-
- mbar_writeByte(MCF_GPIO_PDDR_TIMER,
- mbar_readByte(MCF_GPIO_PDDR_TIMER) | 0x80);
-
- mbar_writeShort(MCF_GPIO_PAR_TIMER,
- mbar_readShort(MCF_GPIO_PAR_TIMER) & 0x3FFF);
- break;
- case 3: /* QSPI_CS[3] = PTIMER[3] */
- if (cs_active_high)
- mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x08);
- else
- mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0xF7);
-
- mbar_writeByte(MCF_GPIO_PDDR_TIMER,
- mbar_readByte(MCF_GPIO_PDDR_TIMER) | 0x08);
-
- mbar_writeShort(MCF_GPIO_PAR_TIMER,
- mbar_readShort(MCF_GPIO_PAR_TIMER) & 0xFF3F);
- break;
- }
-}
-
-/* Deassert chip select, val = [1|0], dir = in, mode = GPIO
- * direction set as IN to undrive the pin, external pullup/pulldown will bring
- * bus to deassert state.
- */
-void cfspi_cs_deactivate(uint bus, uint cs, uint cs_active_high)
-{
- debug("%s: bus %d cs %d cs_active_high %d\n",
- __func__, bus, cs, cs_active_high);
-
- switch (cs) {
- case 0: /* QSPI_CS[0] = PQSPI[3] */
- if (cs_active_high)
- mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xF7);
- else
- mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x08);
-
- mbar_writeByte(MCF_GPIO_PDDR_QSPI,
- mbar_readByte(MCF_GPIO_PDDR_QSPI) & 0xF7);
-
- mbar_writeByte(MCF_GPIO_PAR_QSPI,
- mbar_readByte(MCF_GPIO_PAR_QSPI) & 0xDF);
- break;
- case 1: /* QSPI_CS[1] = PQSPI[4] */
- if (cs_active_high)
- mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xEF);
- else
- mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x10);
-
- mbar_writeByte(MCF_GPIO_PDDR_QSPI,
- mbar_readByte(MCF_GPIO_PDDR_QSPI) & 0xEF);
-
- mbar_writeByte(MCF_GPIO_PAR_QSPI,
- mbar_readByte(MCF_GPIO_PAR_QSPI) & 0x3F);
- break;
- case 2: /* QSPI_CS[2] = PTIMER[7] */
- if (cs_active_high)
- mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0x7F);
- else
- mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x80);
-
- mbar_writeByte(MCF_GPIO_PDDR_TIMER,
- mbar_readByte(MCF_GPIO_PDDR_TIMER) & 0x7F);
-
- mbar_writeShort(MCF_GPIO_PAR_TIMER,
- mbar_readShort(MCF_GPIO_PAR_TIMER) & 0x3FFF);
- break;
- case 3: /* QSPI_CS[3] = PTIMER[3] */
- if (cs_active_high)
- mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0xF7);
- else
- mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x08);
-
- mbar_writeByte(MCF_GPIO_PDDR_TIMER,
- mbar_readByte(MCF_GPIO_PDDR_TIMER) & 0xF7);
-
- mbar_writeShort(MCF_GPIO_PAR_TIMER,
- mbar_readShort(MCF_GPIO_PAR_TIMER) & 0xFF3F);
- break;
- }
-}
-#endif /* CONFIG_M5271 */
}
#endif /* CONFIG_CF_DSPI */
-#ifdef CONFIG_CF_QSPI
-/* 52xx, 53xx */
-#endif /* CONFIG_CF_QSPI */
-
#ifdef CONFIG_CMD_SPI
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
+++ /dev/null
-/*
- * SPI Driver for EP93xx
- *
- * Copyright (C) 2013 Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
- *
- * Inspired form linux kernel driver and atmel uboot driver
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spi.h>
-#include <malloc.h>
-
-#include <asm/io.h>
-
-#include <asm/arch/ep93xx.h>
-
-#define SSPBASE SPI_BASE
-
-#define SSPCR0 0x0000
-#define SSPCR0_MODE_SHIFT 6
-#define SSPCR0_SCR_SHIFT 8
-#define SSPCR0_SPH BIT(7)
-#define SSPCR0_SPO BIT(6)
-#define SSPCR0_FRF_SPI 0
-#define SSPCR0_DSS_8BIT 7
-
-#define SSPCR1 0x0004
-#define SSPCR1_RIE BIT(0)
-#define SSPCR1_TIE BIT(1)
-#define SSPCR1_RORIE BIT(2)
-#define SSPCR1_LBM BIT(3)
-#define SSPCR1_SSE BIT(4)
-#define SSPCR1_MS BIT(5)
-#define SSPCR1_SOD BIT(6)
-
-#define SSPDR 0x0008
-
-#define SSPSR 0x000c
-#define SSPSR_TFE BIT(0)
-#define SSPSR_TNF BIT(1)
-#define SSPSR_RNE BIT(2)
-#define SSPSR_RFF BIT(3)
-#define SSPSR_BSY BIT(4)
-#define SSPCPSR 0x0010
-
-#define SSPIIR 0x0014
-#define SSPIIR_RIS BIT(0)
-#define SSPIIR_TIS BIT(1)
-#define SSPIIR_RORIS BIT(2)
-#define SSPICR SSPIIR
-
-#define SSPCLOCK 14745600
-#define SSP_MAX_RATE (SSPCLOCK / 2)
-#define SSP_MIN_RATE (SSPCLOCK / (254 * 256))
-
-/* timeout in milliseconds */
-#define SPI_TIMEOUT 5
-/* maximum depth of RX/TX FIFO */
-#define SPI_FIFO_SIZE 8
-
-struct ep93xx_spi_slave {
- struct spi_slave slave;
-
- unsigned sspcr0;
- unsigned sspcpsr;
-};
-
-static inline struct ep93xx_spi_slave *to_ep93xx_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct ep93xx_spi_slave, slave);
-}
-
-void spi_init()
-{
-}
-
-static inline void ep93xx_spi_write_u8(u16 reg, u8 value)
-{
- writel(value, (unsigned int *)(SSPBASE + reg));
-}
-
-static inline u8 ep93xx_spi_read_u8(u16 reg)
-{
- return readl((unsigned int *)(SSPBASE + reg));
-}
-
-static inline void ep93xx_spi_write_u16(u16 reg, u16 value)
-{
- writel(value, (unsigned int *)(SSPBASE + reg));
-}
-
-static inline u16 ep93xx_spi_read_u16(u16 reg)
-{
- return (u16)readl((unsigned int *)(SSPBASE + reg));
-}
-
-static int ep93xx_spi_init_hw(unsigned int rate, unsigned int mode,
- struct ep93xx_spi_slave *slave)
-{
- unsigned cpsr, scr;
-
- if (rate > SSP_MAX_RATE)
- rate = SSP_MAX_RATE;
-
- if (rate < SSP_MIN_RATE)
- return -1;
-
- /* Calculate divisors so that we can get speed according the
- * following formula:
- * rate = spi_clock_rate / (cpsr * (1 + scr))
- *
- * cpsr must be even number and starts from 2, scr can be any number
- * between 0 and 255.
- */
- for (cpsr = 2; cpsr <= 254; cpsr += 2) {
- for (scr = 0; scr <= 255; scr++) {
- if ((SSPCLOCK / (cpsr * (scr + 1))) <= rate) {
- /* Set CHPA and CPOL, SPI format and 8bit */
- unsigned sspcr0 = (scr << SSPCR0_SCR_SHIFT) |
- SSPCR0_FRF_SPI | SSPCR0_DSS_8BIT;
- if (mode & SPI_CPHA)
- sspcr0 |= SSPCR0_SPH;
- if (mode & SPI_CPOL)
- sspcr0 |= SSPCR0_SPO;
-
- slave->sspcr0 = sspcr0;
- slave->sspcpsr = cpsr;
- return 0;
- }
- }
- }
-
- return -1;
-}
-
-void spi_set_speed(struct spi_slave *slave, unsigned int hz)
-{
- struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
-
- unsigned int mode = 0;
- if (as->sspcr0 & SSPCR0_SPH)
- mode |= SPI_CPHA;
- if (as->sspcr0 & SSPCR0_SPO)
- mode |= SPI_CPOL;
-
- ep93xx_spi_init_hw(hz, mode, as);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct ep93xx_spi_slave *as;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- as = spi_alloc_slave(struct ep93xx_spi_slave, bus, cs);
- if (!as)
- return NULL;
-
- if (ep93xx_spi_init_hw(max_hz, mode, as)) {
- free(as);
- return NULL;
- }
-
- return &as->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
-
- free(as);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
-
- /* Enable the SPI hardware */
- ep93xx_spi_write_u8(SSPCR1, SSPCR1_SSE);
-
-
- ep93xx_spi_write_u8(SSPCPSR, as->sspcpsr);
- ep93xx_spi_write_u16(SSPCR0, as->sspcr0);
-
- debug("Select CS:%d SSPCPSR=%02x SSPCR0=%04x\n",
- slave->cs, as->sspcpsr, as->sspcr0);
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- /* Disable the SPI hardware */
- ep93xx_spi_write_u8(SSPCR1, 0);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
-{
- unsigned int len_tx;
- unsigned int len_rx;
- unsigned int len;
- u32 status;
- const u8 *txp = dout;
- u8 *rxp = din;
- u8 value;
-
- debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
- slave->bus, slave->cs, (uint *)dout, (uint *)din, bitlen);
-
-
- if (bitlen == 0)
- /* Finish any previously submitted transfers */
- goto out;
-
- if (bitlen % 8) {
- /* Errors always terminate an ongoing transfer */
- flags |= SPI_XFER_END;
- goto out;
- }
-
- len = bitlen / 8;
-
-
- if (flags & SPI_XFER_BEGIN) {
- /* Empty RX FIFO */
- while ((ep93xx_spi_read_u8(SSPSR) & SSPSR_RNE))
- ep93xx_spi_read_u8(SSPDR);
-
- spi_cs_activate(slave);
- }
-
- for (len_tx = 0, len_rx = 0; len_rx < len; ) {
- status = ep93xx_spi_read_u8(SSPSR);
-
- if ((len_tx < len) && (status & SSPSR_TNF)) {
- if (txp)
- value = *txp++;
- else
- value = 0xff;
-
- ep93xx_spi_write_u8(SSPDR, value);
- len_tx++;
- }
-
- if (status & SSPSR_RNE) {
- value = ep93xx_spi_read_u8(SSPDR);
-
- if (rxp)
- *rxp++ = value;
- len_rx++;
- }
- }
-
-out:
- if (flags & SPI_XFER_END) {
- /*
- * Wait until the transfer is completely done before
- * we deactivate CS.
- */
- do {
- status = ep93xx_spi_read_u8(SSPSR);
- } while (status & SSPSR_BSY);
-
- spi_cs_deactivate(slave);
- }
-
- return 0;
-}
config G_DNL_PRODUCT_NUM
hex "Product ID of USB device"
+config USBNET_DEVADDR
+ string "USB Gadget Ethernet device mac address"
+ default "de:ad:be:ef:00:01"
+
endif # USB_GADGET_DOWNLOAD
endif # USB_GADGET
"WAIT_FOR_NULL_COMPLETE",
};
-#define DRIVER_DESC "DWC2 HS USB OTG Device Driver, (c) Samsung Electronics"
#define DRIVER_VERSION "15 March 2009"
struct dwc2_udc *the_controller;
static const char driver_name[] = "dwc2-udc";
-static const char driver_desc[] = DRIVER_DESC;
static const char ep0name[] = "ep0-control";
/* Max packet size*/
#include "rndis.h"
#include <dm.h>
+#include <dm/lists.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
struct usb_request *tx_req, *rx_req;
+#ifndef CONFIG_DM_ETH
struct eth_device *net;
+#else
+ struct udevice *net;
+#endif
struct net_device_stats stats;
unsigned int tx_qlen;
/*-------------------------------------------------------------------------*/
struct ether_priv {
struct eth_dev ethdev;
+#ifndef CONFIG_DM_ETH
struct eth_device netdev;
+#else
+ struct udevice *netdev;
+#endif
struct usb_gadget_driver eth_driver;
};
* can't really use its struct. All we do here is say that we're using
* the submode of "SAFE" which directly matches the CDC Subset.
*/
+#ifdef CONFIG_USB_ETH_SUBSET
static const u8 mdlm_detail_desc[] = {
6,
USB_DT_CS_INTERFACE,
0, /* network control capabilities (none) */
0, /* network data capabilities ("raw" encapsulation) */
};
+#endif
#endif
static char rndis_resp_buf[8] __attribute__((aligned(sizeof(__le32))));
+#ifndef CONFIG_DM_ETH
static int rndis_control_ack(struct eth_device *net)
+#else
+static int rndis_control_ack(struct udevice *net)
+#endif
{
struct ether_priv *priv = (struct ether_priv *)net->priv;
struct eth_dev *dev = &priv->ethdev;
int status = -ENOMEM;
int gcnum;
u8 tmp[7];
+#ifdef CONFIG_DM_ETH
+ struct eth_pdata *pdata = dev_get_platdata(l_priv->netdev);
+#endif
/* these flags are only ever cleared; compiler take note */
#ifndef CONFIG_USB_ETH_CDC
/* network device setup */
+#ifndef CONFIG_DM_ETH
dev->net = &l_priv->netdev;
+#else
+ dev->net = l_priv->netdev;
+#endif
dev->cdc = cdc;
dev->zlp = zlp;
dev->out_ep = out_ep;
dev->status_ep = status_ep;
+ memset(tmp, 0, sizeof(tmp));
/*
* Module params for these addresses should come from ID proms.
* The host side address is used with CDC and RNDIS, and commonly
* host side code for the SAFE thing cares -- its original BLAN
* thing didn't, Sharp never assigned those addresses on Zaurii.
*/
+#ifndef CONFIG_DM_ETH
get_ether_addr(dev_addr, dev->net->enetaddr);
-
- memset(tmp, 0, sizeof(tmp));
memcpy(tmp, dev->net->enetaddr, sizeof(dev->net->enetaddr));
+#else
+ get_ether_addr(dev_addr, pdata->enetaddr);
+ memcpy(tmp, pdata->enetaddr, sizeof(pdata->enetaddr));
+#endif
get_ether_addr(host_addr, dev->host_mac);
status_ep ? " STATUS " : "",
status_ep ? status_ep->name : ""
);
- printf("MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev->net->enetaddr[0], dev->net->enetaddr[1],
- dev->net->enetaddr[2], dev->net->enetaddr[3],
- dev->net->enetaddr[4], dev->net->enetaddr[5]);
+#ifndef CONFIG_DM_ETH
+ printf("MAC %pM\n", dev->net->enetaddr);
+#else
+ printf("MAC %pM\n", pdata->enetaddr);
+#endif
if (cdc || rndis)
printf("HOST MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
}
usb_gadget_unregister_driver(&priv->eth_driver);
-#ifdef CONFIG_DM_USB
- device_remove(dev->usb_udev);
-#else
+#ifndef CONFIG_DM_USB
board_usb_cleanup(0, USB_INIT_DEVICE);
#endif
}
+#ifndef CONFIG_DM_ETH
static int usb_eth_init(struct eth_device *netdev, bd_t *bd)
{
struct ether_priv *priv = (struct ether_priv *)netdev->priv;
eth_register(netdev);
return 0;
}
+#else
+static int usb_eth_start(struct udevice *dev)
+{
+ struct ether_priv *priv = dev_get_priv(dev);
+
+ return _usb_eth_init(priv);
+}
+
+static int usb_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct ether_priv *priv = dev_get_priv(dev);
+
+ return _usb_eth_send(priv, packet, length);
+}
+
+static int usb_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct ether_priv *priv = dev_get_priv(dev);
+ struct eth_dev *ethdev = &priv->ethdev;
+ int ret;
+
+ ret = _usb_eth_recv(priv);
+ if (ret) {
+ error("error packet receive\n");
+ return ret;
+ }
+
+ if (packet_received) {
+ if (ethdev->rx_req) {
+ *packetp = (uchar *)net_rx_packets[0];
+ return ethdev->rx_req->length;
+ } else {
+ error("dev->rx_req invalid");
+ return -EFAULT;
+ }
+ }
+
+ return -EAGAIN;
+}
+
+static int usb_eth_free_pkt(struct udevice *dev, uchar *packet,
+ int length)
+{
+ struct ether_priv *priv = dev_get_priv(dev);
+ struct eth_dev *ethdev = &priv->ethdev;
+
+ packet_received = 0;
+
+ return rx_submit(ethdev, ethdev->rx_req, 0);
+}
+
+static void usb_eth_stop(struct udevice *dev)
+{
+ struct ether_priv *priv = dev_get_priv(dev);
+
+ _usb_eth_halt(priv);
+}
+
+static int usb_eth_probe(struct udevice *dev)
+{
+ struct ether_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ priv->netdev = dev;
+ l_priv = priv;
+
+ get_ether_addr(CONFIG_USBNET_DEVADDR, pdata->enetaddr);
+ eth_setenv_enetaddr("usbnet_devaddr", pdata->enetaddr);
+
+ return 0;
+}
+
+static const struct eth_ops usb_eth_ops = {
+ .start = usb_eth_start,
+ .send = usb_eth_send,
+ .recv = usb_eth_recv,
+ .free_pkt = usb_eth_free_pkt,
+ .stop = usb_eth_stop,
+};
+
+int usb_ether_init(void)
+{
+ struct udevice *dev;
+ struct udevice *usb_dev;
+ int ret;
+
+ ret = uclass_first_device(UCLASS_USB_DEV_GENERIC, &usb_dev);
+ if (!usb_dev || ret) {
+ error("No USB device found\n");
+ return ret;
+ }
+
+ ret = device_bind_driver(usb_dev, "usb_ether", "usb_ether", &dev);
+ if (!dev || ret) {
+ error("usb - not able to bind usb_ether device\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(eth_usb) = {
+ .name = "usb_ether",
+ .id = UCLASS_ETH,
+ .probe = usb_eth_probe,
+ .ops = &usb_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct ether_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif /* CONFIG_DM_ETH */
return -ENOTSUPP;
}
+#ifndef CONFIG_DM_ETH
int rndis_register(int (*rndis_control_ack)(struct eth_device *))
+#else
+int rndis_register(int (*rndis_control_ack)(struct udevice *))
+#endif
{
u8 i;
return;
}
-int rndis_set_param_dev(u8 configNr, struct eth_device *dev, int mtu,
- struct net_device_stats *stats, u16 *cdc_filter)
+#ifndef CONFIG_DM_ETH
+int rndis_set_param_dev(u8 configNr, struct eth_device *dev, int mtu,
+ struct net_device_stats *stats, u16 *cdc_filter)
+#else
+int rndis_set_param_dev(u8 configNr, struct udevice *dev, int mtu,
+ struct net_device_stats *stats, u16 *cdc_filter)
+#endif
{
debug("%s: configNr = %d\n", __func__, configNr);
if (!dev || !stats)
const u8 *host_mac;
u16 *filter;
- struct eth_device *dev;
struct net_device_stats *stats;
int mtu;
u32 vendorID;
const char *vendorDescr;
- int (*ack)(struct eth_device *);
+#ifndef CONFIG_DM_ETH
+ struct eth_device *dev;
+ int (*ack)(struct eth_device *);
+#else
+ struct udevice *dev;
+ int (*ack)(struct udevice *);
+#endif
struct list_head resp_queue;
} rndis_params;
/* RNDIS Message parser and other useless functions */
int rndis_msg_parser(u8 configNr, u8 *buf);
enum rndis_state rndis_get_state(int configNr);
-int rndis_register(int (*rndis_control_ack)(struct eth_device *));
void rndis_deregister(int configNr);
+#ifndef CONFIG_DM_ETH
+int rndis_register(int (*rndis_control_ack)(struct eth_device *));
int rndis_set_param_dev(u8 configNr, struct eth_device *dev, int mtu,
- struct net_device_stats *stats, u16 *cdc_filter);
+ struct net_device_stats *stats, u16 *cdc_filter);
+#else
+int rndis_register(int (*rndis_control_ack)(struct udevice *));
+int rndis_set_param_dev(u8 configNr, struct udevice *dev, int mtu,
+ struct net_device_stats *stats, u16 *cdc_filter);
+#endif
int rndis_set_param_vendor(u8 configNr, u32 vendorID,
const char *vendorDescr);
int rndis_set_param_medium(u8 configNr, u32 medium, u32 speed);
help
Enables support for the on-chip xHCI controller on Rockchip SoCs.
+config USB_XHCI_ZYNQMP
+ bool "Support for Xilinx ZynqMP on-chip xHCI USB controller"
+ depends on ARCH_ZYNQMP
+ help
+ Enables support for the on-chip xHCI controller on Xilinx ZynqMP SoCs.
+
endif # USB_XHCI_HCD
config USB_EHCI_HCD
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/sys_proto.h>
#include <dm.h>
+#include <power/regulator.h>
#include "ehci.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define USB_OTGREGS_OFFSET 0x000
#define USB_H1REGS_OFFSET 0x200
#define USB_H2REGS_OFFSET 0x400
#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
#define USBNC_OFFSET 0x200
+#define USBNC_PHY_STATUS_OFFSET 0x23C
#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
#define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
struct ehci_mx6_priv_data {
struct ehci_ctrl ctrl;
struct usb_ehci *ehci;
+ struct udevice *vbus_supply;
enum usb_init_type init_type;
int portnr;
};
if (ret)
return ret;
- board_ehci_power(priv->portnr, (type == USB_INIT_DEVICE) ? 0 : 1);
+ if (priv->vbus_supply) {
+ ret = regulator_set_enable(priv->vbus_supply,
+ (type == USB_INIT_DEVICE) ?
+ false : true);
+ if (ret) {
+ puts("Error enabling VBUS supply\n");
+ return ret;
+ }
+ }
if (type == USB_INIT_DEVICE)
return 0;
.init_after_reset = mx6_init_after_reset
};
+static int ehci_usb_phy_mode(struct udevice *dev)
+{
+ struct usb_platdata *plat = dev_get_platdata(dev);
+ void *__iomem addr = (void *__iomem)dev_get_addr(dev);
+ void *__iomem phy_ctrl, *__iomem phy_status;
+ const void *blob = gd->fdt_blob;
+ int offset = dev->of_offset, phy_off;
+ u32 val;
+
+ /*
+ * About fsl,usbphy, Refer to
+ * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
+ */
+ if (is_mx6()) {
+ phy_off = fdtdec_lookup_phandle(blob,
+ offset,
+ "fsl,usbphy");
+ if (phy_off < 0)
+ return -EINVAL;
+
+ addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
+ "reg");
+ if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
+ val = readl(phy_ctrl);
+
+ if (val & USBPHY_CTRL_OTG_ID)
+ plat->init_type = USB_INIT_DEVICE;
+ else
+ plat->init_type = USB_INIT_HOST;
+ } else if (is_mx7()) {
+ phy_status = (void __iomem *)(addr +
+ USBNC_PHY_STATUS_OFFSET);
+ val = readl(phy_status);
+
+ if (val & USBNC_PHYSTATUS_ID_DIG)
+ plat->init_type = USB_INIT_DEVICE;
+ else
+ plat->init_type = USB_INIT_HOST;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct usb_platdata *plat = dev_get_platdata(dev);
+ const char *mode;
+
+ mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "dr_mode", NULL);
+ if (mode) {
+ if (strcmp(mode, "peripheral") == 0)
+ plat->init_type = USB_INIT_DEVICE;
+ else if (strcmp(mode, "host") == 0)
+ plat->init_type = USB_INIT_HOST;
+ else if (strcmp(mode, "otg") == 0)
+ return ehci_usb_phy_mode(dev);
+ else
+ return -EINVAL;
+
+ return 0;
+ }
+
+ return ehci_usb_phy_mode(dev);
+}
+
static int ehci_usb_probe(struct udevice *dev)
{
struct usb_platdata *plat = dev_get_platdata(dev);
struct usb_ehci *ehci = (struct usb_ehci *)dev_get_addr(dev);
struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
+ enum usb_init_type type = plat->init_type;
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
int ret;
priv->ehci = ehci;
priv->portnr = dev->seq;
- priv->init_type = plat->init_type;
+ priv->init_type = type;
+
+ ret = device_get_supply_regulator(dev, "vbus-supply",
+ &priv->vbus_supply);
+ if (ret)
+ debug("%s: No vbus supply\n", dev->name);
ret = ehci_mx6_common_init(ehci, priv->portnr);
if (ret)
return ret;
- board_ehci_power(priv->portnr, (priv->init_type == USB_INIT_DEVICE) ? 0 : 1);
+ if (priv->vbus_supply) {
+ ret = regulator_set_enable(priv->vbus_supply,
+ (type == USB_INIT_DEVICE) ?
+ false : true);
+ if (ret) {
+ puts("Error enabling VBUS supply\n");
+ return ret;
+ }
+ }
if (priv->init_type == USB_INIT_HOST) {
setbits_le32(&ehci->usbmode, CM_HOST);
.name = "ehci_mx6",
.id = UCLASS_USB,
.of_match = mx6_usb_ids,
+ .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
.probe = ehci_usb_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
__maybe_unused int y_off = 0;
__maybe_unused ulong addr;
__maybe_unused char *s;
- __maybe_unused int len, space;
+ __maybe_unused int len, ret, space;
splash_get_pos(&video_logo_xpos, &video_logo_ypos);
#ifdef CONFIG_SPLASH_SCREEN
s = getenv("splashimage");
if (s != NULL) {
- splash_screen_prepare();
+ ret = splash_screen_prepare();
+ if (ret < 0)
+ return video_fb_address;
addr = simple_strtoul(s, NULL, 16);
if (video_display_bitmap(addr,
static const struct hdmi_phy_config rockchip_phy_config[] = {
{
- .mpixelclock = 74250,
+ .mpixelclock = 74250000,
.sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
}, {
- .mpixelclock = 148500,
+ .mpixelclock = 148500000,
.sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
}, {
- .mpixelclock = 297000,
+ .mpixelclock = 297000000,
.sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
}, {
.mpixelclock = ~0ul,
static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
{
- .mpixelclock = 40000,
+ .mpixelclock = 40000000,
.cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
}, {
- .mpixelclock = 65000,
+ .mpixelclock = 65000000,
.cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
}, {
- .mpixelclock = 66000,
+ .mpixelclock = 66000000,
.cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
}, {
- .mpixelclock = 83500,
+ .mpixelclock = 835000000,
.cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
}, {
- .mpixelclock = 146250,
+ .mpixelclock = 146250000,
.cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
}, {
- .mpixelclock = 148500,
+ .mpixelclock = 148500000,
.cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
}, {
.mpixelclock = ~0ul,
clk_free(&clk);
}
if (ret) {
- debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
+ debug("%s: Failed to set hdmi clock: ret=%d\n", __func__, ret);
return ret;
}
/*
* Before we probe the display device (eDP), tell it that this device
- * is are the source of the display data.
+ * is the source of the display data.
*/
ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev);
if (ret) {
typedef volatile unsigned short vu_short;
typedef volatile unsigned char vu_char;
+/* Allow sharing constants with type modifiers between C and assembly. */
+#define _AC(X, Y) (X##Y)
+
#include <config.h>
#include <errno.h>
+#include <time.h>
#include <asm-offsets.h>
#include <linux/bitops.h>
+#include <linux/delay.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/stringify.h>
#endif
#endif
-/*
- * Return the current value of a monotonically increasing microsecond timer.
- * Granularity may be larger than 1us if hardware does not support this.
- */
-ulong timer_get_us(void);
-
/* $(CPU)/cpu.c */
static inline int cpumask_next(int cpu, unsigned int mask)
{
void irq_install_handler(int, interrupt_handler_t *, void *);
void irq_free_handler (int);
void reset_timer (void);
-ulong get_timer (ulong base);
/* Return value of monotonic microsecond timer */
unsigned long timer_get_us(void);
void wait_ticks (unsigned long);
/* arch/$(ARCH)/lib/time.c */
-void __udelay (unsigned long);
ulong usec2ticks (unsigned long usec);
ulong ticks2usec (unsigned long ticks);
int init_timebase (void);
int(*compar)(const void *, const void *));
int strcmp_compar(const void *, const void *);
-/* lib/time.c */
-void udelay (unsigned long);
-void mdelay(unsigned long);
-
/* lib/uuid.c */
#include <uuid.h>
int cpu_release(int nr, int argc, char * const argv[]);
#endif
-#endif /* __ASSEMBLY__ */
+#else /* __ASSEMBLY__ */
+
+/* Drop a C type modifier (like in 3UL) for constants used in assembly. */
+#define _AC(X, Y) X
+
+#endif /* __ASSEMBLY__ */
#ifdef CONFIG_PPC
/*
/* Put only stuff here that the assembler can digest */
+/* Declare an unsigned long constant digestable both by C and an assembler. */
+#define UL(x) _AC(x, UL)
+
#ifdef CONFIG_POST
#define CONFIG_HAS_POST
#ifndef CONFIG_POST_ALT_LIST
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_FSL_DDR3
#ifndef CONFIG_SPL_BUILD
#define CONFIG_FSL_DDR_INTERACTIVE
#endif
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_SYS_MEMTEST_END 0x01ffffff
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
#undef CONFIG_SYS_DDR_RAW_TIMING
#undef CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_SYS_TEXT_BASE 0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1
#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_RAMBOOT
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
#define CONFIG_SYS_MEMTEST_END 0x01ffffff
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
#define CONFIG_PANIC_HANG
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x50
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ESDHC_USE_PIO
#define CONFIG_GENERIC_MMC
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
/*
- * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
- * undefine it to use old spd_sdram.c
+ * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
+ * unselect it to use old spd_sdram.c
*/
-#define CONFIG_SYS_FSL_DDR2
-#ifdef CONFIG_SYS_FSL_DDR2
-#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x52
#define SPD_EEPROM_ADDRESS2 0x51
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#endif
/*
* 32-bit data path mode.
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#ifndef __CONFIG_H
#define __CONFIG_H
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-
/*
* default CCARBAR is at 0xff700000
* assume U-Boot is less than 0.5MB
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#ifndef __CONFIG_H
#define __CONFIG_H
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#endif
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#ifndef __CONFIG_H
#define __CONFIG_H
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#endif
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_CPM2 1 /* has CPM2 */
/*
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#ifndef __CONFIG_H
#define __CONFIG_H
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#define CONFIG_SYS_SRIO
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#ifndef __CONFIG_H
#define __CONFIG_H
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-
#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
#define CONFIG_SYS_SRIO
#endif
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
#define CONFIG_DDR_SPD
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
/*
* DDR Setup
*/
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_E500 /* BOOKE e500 family */
#include <asm/config_mpc85xx.h>
#define CONFIG_NAND_FSL_IFC
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_MP /* support multiple processors */
#ifndef CONFIG_SYS_TEXT_BASE
/* DDR Setup */
#define CONFIG_DDR_SPD
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_FSL_DDR3
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_MP /* support multiple processors */
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
#define CONFIG_SYS_SPD_BUS_NUM 0
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x52
#define __T1024QDS_H
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#define CONFIG_ENABLE_36BIT_PHYS
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3
-#endif
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
#define __T1024RDB_H
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#define CONFIG_ENABLE_36BIT_PHYS
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
#endif
#define CONFIG_SPL_NAND_BOOT
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
#endif
#define CONFIG_SPL_SPI_BOOT
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
#endif
#define CONFIG_SPL_MMC_BOOT
#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_ENV_SECT_SIZE 0x10000
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_ENV_SECT_SIZE 0x40000
#endif
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#endif
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_FSL_DDR_INTERACTIVE
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-#elif defined(CONFIG_T1023RDB)
-#define CONFIG_SYS_FSL_DDR4
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_SDRAM_SIZE 2048
#endif
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
#endif
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
#define CONFIG_SYS_DPAA_FMAN
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
#define CONFIG_QE
#define CONFIG_U_QE
#endif
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
#endif
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_AQUANTIA
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
#define RGMII_PHY1_ADDR 0x2
#define RGMII_PHY2_ADDR 0x6
#define SGMII_AQR_PHY_ADDR 0x2
#define FM1_10GEC1_PHY_ADDR 0x1
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
#define RGMII_PHY1_ADDR 0x1
#define SGMII_RTK_PHY_ADDR 0x3
#define SGMII_AQR_PHY_ADDR 0x2
/*
* T1040 QDS board configuration file
*/
-#define CONFIG_T1040QDS
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3
-#endif
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
/*
* T104x RDB board configuration file
*/
-#define CONFIG_E500 /* BOOKE e500 family */
#include <asm/config_mpc85xx.h>
#ifdef CONFIG_RAMBOOT_PBL
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3
-#endif
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_USB_EHCI
#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_T2080QDS
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
#elif defined(CONFIG_ARCH_T2081)
-#define CONFIG_T2081QDS
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#define CONFIG_ENABLE_36BIT_PHYS
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#ifndef __T2080RDB_H
#define __T2080RDB_H
-#define CONFIG_T2080RDB
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_USB_EHCI
#define CONFIG_FSL_SATA_V2
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#define CONFIG_ENABLE_36BIT_PHYS
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define CONFIG_CMD_REGINFO
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
/*
* IFC Definitions
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500
-/* #define CONFIG_MPC85xx */
-
#define CONFIG_MP
#define CONFIG_ENV_OVERWRITE
/* DDR Setup */
#define CONFIG_DDR_ECC_ENABLE
-#define CONFIG_SYS_FSL_DDR3
#ifndef CONFIG_DDR_ECC_ENABLE
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Default settings for DDR3 */
#endif
#ifdef CONFIG_USB_MUSB_GADGET
-/* Removing USB gadget and can be enabled adter adding support usb DM */
-#ifndef CONFIG_DM_ETH
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
-#endif /* CONFIG_DM_ETH */
#endif /* CONFIG_USB_MUSB_GADGET */
/*
#define CONFIG_ENV_OFFSET 0x0
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_SYS_MMC_MAX_DEVICE 2
#elif defined(CONFIG_NOR_BOOT)
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
#define CONFIG_GENERIC_MMC 1
-#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
/*
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
/*
/* SD/MMC support */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_MXC_MMC
#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
#endif
* SD/MMC configuration
*/
#define CONFIG_GENERIC_MMC
-#define CONFIG_DWMMC
#define CONFIG_DOS_PARTITION
/*
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
/* MMC/SD IP block */
#if defined(CONFIG_EMMC_BOOT)
#define CONFIG_GENERIC_MMC
- #define CONFIG_OMAP_HSMMC
#define CONFIG_SUPPORT_EMMC_BOOT
#endif /* CONFIG_EMMC_BOOT */
/* MMC/SD IP block */
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
#define CONFIG_SUPPORT_EMMC_BOOT
/* Always 64 KiB env size */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
115200}
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
/* USB */
#define CONFIG_OMAP_GPIO
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
/* USB */
#define CONFIG_TEGRA_UARTA_SDIO1
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T20
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC support */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* USB host support */
#define CONFIG_USB_EHCI
/* SD/MMC support */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE /* BOOKE */
-#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_CONTROLCENTERD
#define CONFIG_MP /* support multiple processors */
#define CONFIG_SYS_SDRAM_SIZE 1024
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_FSL_DDR3
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS1 0x51
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS1 0x51
/* SD/MMC configuration */
#ifndef CONFIG_USE_NOR
-#define CONFIG_DAVINCI_MMC_SD1
#define CONFIG_GENERIC_MMC
-#define CONFIG_DAVINCI_MMC
#endif
/*
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-/* Define to enable MMC on SPI support */
-/* #define CONFIG_EP93XX_SPI_MMC */
-
-#ifdef CONFIG_EP93XX_SPI_MMC
-#define CONFIG_EP93XX_SPI
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC_SPI
-#define CONFIG_MMC_SPI_NPOWER_EGPIO 9
-#endif
-
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_OHCI_EP93XX
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
+
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+/* SPL @ 32k for 34k
+ * u-boot directly after @ 68k for 400k or so
+ * ENV @ 992k
+ */
+#define CONFIG_ENV_OFFSET ((1024-32) * 1024)
+#else
/* SPL @ 32k for ~36k
* ENV @ 96k
* u-boot @ 128K
*/
#define CONFIG_ENV_OFFSET (96 * 1024)
+#endif
#define CONFIG_SYS_WHITE_ON_BLACK
/* SD/MMC configuration */
#define CONFIG_GENERIC_MMC
-#define CONFIG_DWMMC
-#define CONFIG_EXYNOS_DWMMC
#define CONFIG_BOUNCE_BUFFER
/* PWM */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
+
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+/* SPL @ 32k for 34k
+ * u-boot directly after @ 68k for 400k or so
+ * ENV @ 992k
+ */
+#define CONFIG_ENV_OFFSET ((1024-32) * 1024)
+#else
/* SPL @ 32k for ~36k
* ENV @ 96k
* u-boot @ 128K
*/
#define CONFIG_ENV_OFFSET (96 * 1024)
+#endif
#define CONFIG_SYS_WHITE_ON_BLACK
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* NAND support */
#define CONFIG_CMD_NAND
/* SD/MMC configuration */
#define CONFIG_GENERIC_MMC
-#define CONFIG_DWMMC
-#define CONFIG_HIKEY_DWMMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FS_EXT4
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
- * Machine type
- */
-#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT
-
-/*
* Compression configuration
*/
#define CONFIG_BZIP2
* SD/MMC
*/
#define CONFIG_GENERIC_MMC
-#define CONFIG_MXC_MMC
#define CONFIG_DOS_PARTITION
/*
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
/* MMC/SD */
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
#undef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_IS_IN_FAT
#define CONFIG_CADENCE_QSPI
#define CONFIG_CQSPI_REF_CLK 384000000
#define CONFIG_CQSPI_DECODER 0x0
+#define CONFIG_BOUNCE_BUFFER
#endif
#endif /* __CONFIG_K2G_EVM_H */
*/
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
/*
* Power
#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_MP /* support multiple processors */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* emmc */
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
-#define CONFIG_ENV_OFFSET (SZ_4M - SZ_64K) /* reserved area */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+/* SPL @ 32k for 34k
+ * u-boot directly after @ 68k for 400k or so
+ * ENV @ 992k
+ */
+#define CONFIG_ENV_OFFSET ((1024-32) * 1024)
+#else
+/* SPL @ 32k for ~36k
+ * ENV @ 96k
+ * u-boot @ 128K
+ */
+#define CONFIG_ENV_OFFSET (96 * 1024)
+#endif
#endif
#define CONFIG_ENV_SIZE (16 << 10)
/* SD/MMC configuration */
-#define CONFIG_DAVINCI_MMC_SD1
#define CONFIG_GENERIC_MMC
-#define CONFIG_DAVINCI_MMC
/*
* Enable MMC commands only when
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-#define CONFIG_OMAP_HSMMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_BOOTARGS "root=romfs"
#define CONFIG_HOSTNAME XILINX_BOARD_NAME
#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
-#define CONFIG_IPADDR 192.168.0.3
-#define CONFIG_SERVERIP 192.168.0.5
-#define CONFIG_GATEWAYIP 192.168.0.1
/* architecture dependent code */
#define CONFIG_SYS_USR_EXCEP /* user exception */
#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
"nor0=flash-0\0"\
"mtdparts=mtdparts=flash-0:"\
"setenv stdin nc\0" \
"serial=setenv stdout serial;"\
"setenv stdin serial\0"
+#endif
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
-#define CONFIG_SPL_RAM_DEVICE
#ifdef CONFIG_SYS_FLASH_BASE
# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
#endif
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+/* SPL @ 32k for 34k
+ * u-boot directly after @ 68k for 400k or so
+ * ENV @ 992k
+ */
+#define CONFIG_ENV_OFFSET ((1024-32) * 1024)
+#else
/* SPL @ 32k for ~36k
* ENV @ 96k
* u-boot @ 128K
*/
#define CONFIG_ENV_OFFSET (96 * 1024)
+#endif
#define CONFIG_SYS_WHITE_ON_BLACK
/* Secure boot (HAB) support */
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CSF_SIZE 0x2000
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_CAAM
#define CONFIG_CMD_DEKBLOB
-#define CONFIG_SYS_FSL_SEC_LE
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#endif
#define CONFIG_IOMUX_LPSR
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_RTL8152
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif
+
#endif /* __CONFIG_H */
/* Secure boot (HAB) support */
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CSF_SIZE 0x2000
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_CAAM
#define CONFIG_CMD_DEKBLOB
-#define CONFIG_SYS_FSL_SEC_LE
#endif
#endif
#ifdef CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_MXS_MMC
#endif
/* NAND */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
/* USB */
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
/* MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
/* SPL */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_REVISION_TAG 1
/* Status LED available for IGEP0020 and IGEP0030 but not IGEP0032 */
-#if (CONFIG_MACH_TYPE != MACH_TYPE_IGEP0032)
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
+ (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
#define CONFIG_STATUS_LED
#define CONFIG_BOARD_SPECIFIC_LED
#define CONFIG_GPIO_LED
#define RED_LED_GPIO 27
#elif (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
#define RED_LED_GPIO 16
-#else
-#error "status LED not defined for this machine."
#endif
#define RED_LED_DEV 0
#define STATUS_LED_BIT RED_LED_GPIO
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
-#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
/* Hardware drivers */
"saveenv;"
#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x81000000\0" \
- "uimage=uImage\0" \
- "zimage=zImage\0" \
+ DEFAULT_LINUX_BOOT_ENV \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"mmcdev=0\0" \
"${optargs};" \
"run addmtdparts; " \
"run vrfb_arg\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo 'Running bootscript from mmc ...'; " \
"source ${loadaddr}\0" \
"loaduimage=mmc rescan; " \
- "fatload mmc ${mmcdev} ${loadaddr} ${uimage}\0" \
+ "load mmc ${mmcdev} ${loadaddr} uImage\0" \
"loadzimage=mmc rescan; " \
- "fatload mmc ${mmcdev} ${loadaddr} ${zimage}\0" \
+ "load mmc ${mmcdev} ${loadaddr} zImage\0" \
"ramdisksize=64000\0" \
- "ramdiskaddr=0x82000000\0" \
"ramdiskimage=rootfs.ext2.gz.uboot\0" \
"loadramdisk=mmc rescan; " \
- "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}\0" \
+ "load mmc ${mmcdev} ${rdaddr} ${ramdiskimage}\0" \
"ramargs=run setconsole; setenv bootargs console=${console} " \
"root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
"mmcargs=run setconsole; setenv bootargs console=${console} " \
"ip=${ipaddr}:${tftpserver}:${gatewayip}:${netmask}::eth0:off\0" \
"nfsrootpath=/opt/nfs-exports/omap\0" \
"autoload=no\0" \
- "fdtaddr=0x86000000\0" \
- "loadfdtimage=mmc rescan; " \
- "fatload mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \
+ "loadfdt=mmc rescan; " \
+ "load mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \
"mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
"run mmcargs; " \
"run common_bootargs; " \
"run dump_bootargs; " \
"run loadzimage; " \
- "run loadfdtimage; " \
+ "run loadfdt; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
"mmcramboot=echo 'Booting uImage kernel from mmc w/ramdisk...'; " \
"run ramargs; " \
"run dump_bootargs; " \
"run loaduimage; " \
"run loadramdisk; " \
- "bootm ${loadaddr} ${ramdiskaddr}\0" \
+ "bootm ${loadaddr} ${rdaddr}\0" \
"mmcrambootz=echo 'Booting zImage kernel from mmc w/ramdisk...'; " \
"run ramargs; " \
"run common_bootargs; " \
"run dump_bootargs; " \
"run loadzimage; " \
"run loadramdisk; " \
- "run loadfdtimage; " \
- "bootz ${loadaddr} ${ramdiskaddr} ${fdtaddr};\0" \
+ "run loadfdt; " \
+ "bootz ${loadaddr} ${rdaddr} ${fdtaddr};\0" \
"tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
"run ramargs; " \
"run common_bootargs; " \
"run dump_bootargs; " \
"tftpboot ${loadaddr} ${zimage}; " \
- "tftpboot ${ramdiskaddr} ${ramdiskimage}; " \
- "bootm ${loadaddr} ${ramdiskaddr}\0" \
+ "tftpboot ${rdaddr} ${ramdiskimage}; " \
+ "bootm ${loadaddr} ${rdaddr}\0" \
"tftpbootz=echo 'Booting kernel NFS rootfs...'; " \
"dhcp;" \
"run nfsargs;" \
"run autoboot"
/* Miscellaneous configurable options */
-#define CONFIG_AUTO_COMPLETE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
#define CONFIG_CMD_UBIFS
#endif
-#ifdef CONFIG_USE_SPIFLASH
-#endif
-
#if !defined(CONFIG_USE_NAND) && \
!defined(CONFIG_SYS_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH)
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_DAVINCI_MMC
#ifdef CONFIG_MMC
#define CONFIG_DOS_PARTITION
#endif
#endif
-/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500
-
#define CONFIG_MP
#define CONFIG_FSL_ELBC
#endif
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Default settings for DDR3 */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500
-
#define CONFIG_MP
#define CONFIG_FSL_ELBC
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Default settings for DDR3 */
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_FSL_ESDHC_NUM 1
/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
+
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+/* SPL @ 32k for 34k
+ * u-boot directly after @ 68k for 400k or so
+ * ENV @ 992k
+ */
+#define CONFIG_ENV_OFFSET ((1024-32) * 1024)
+#else
/* SPL @ 32k for ~36k
* ENV @ 96k
* u-boot @ 128K
*/
#define CONFIG_ENV_OFFSET (96 * 1024)
+#endif
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_CMD_REGINFO
-/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */
/* MMC/SD IP block */
#define CONFIG_GENERIC_MMC
-#define CONFIG_DWMMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FAT_WRITE
/* MMC/SD IP block */
#define CONFIG_GENERIC_MMC
-#define CONFIG_DWMMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FAT_WRITE
#define CONFIG_G_DNL_VENDOR_NUM 0x2207
#define CONFIG_G_DNL_PRODUCT_NUM 0x320a
+/* usb host support */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+#endif
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00000000\0" \
"pxefile_addr_r=0x00100000\0" \
/* MMC/SD IP block */
#define CONFIG_GENERIC_MMC
-#define CONFIG_DWMMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
/* First try to boot from SD (index 0), then eMMC (index 1 */
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
- func(MMC, mmc, 1)
+ func(MMC, mmc, 1) \
+ func(PXE, pxe, na) \
+ func(DHCP, dchp, na)
/* Enable gpt partition table */
#define CONFIG_CMD_GPT
(&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
#endif
-/*
- * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
- * so 2708 has historically been used rather than a dedicated 2835 ID.
- *
- * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation
- * chose to use someone else's previously registered machine ID (3139, MX51_GGC)
- * rather than obtaining a valid ID:-/
- *
- * For the bcm2837, hopefully a machine type is not needed, since everything
- * is DT.
- */
-#ifdef CONFIG_BCM2835
-#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708
-#endif
-
/* Memory layout */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
/* #define CONFIG_CMD_EXT2 EXT2 Support */
/*
* High Level Configuration Options
*/
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_SBC8548 1 /* SBC8548 board specific */
/*
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
/*
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CACHE_LINE_INTERLEAVING 0x20000000
#define PAGE_INTERLEAVING 0x21000000
#define BANK_INTERLEAVING 0x22000000
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
#define CONFIG_SPI
#define CONFIG_SYS_MAXARGS 32
/* setting board specific options */
-#define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB
#define CONFIG_AUTO_COMPLETE
#define CONFIG_ENV_OVERWRITE 1 /* Overwrite ethaddr / serial# */
#define CONFIG_AUTO_COMPLETE
*/
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
/*
* Power
#ifdef CONFIG_CMD_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_GENERIC_MMC
-#define CONFIG_DWMMC
-#define CONFIG_SOCFPGA_DWMMC
-#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
#endif
#define CONFIG_CQSPI_DECODER 0
+#define CONFIG_BOUNCE_BUFFER
/*
* Designware SPI support
* 0xFFFF_FF00 ...... End of SRAM
*/
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SPL_MAX_SIZE (64 * 1024)
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_SOCRATES 1
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
#define CONFIG_CQSPI_DECODER 0
#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
+#define CONFIG_BOUNCE_BUFFER
#endif
/*
* High Level Configuration Options
*/
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */
#endif
/* mmc config */
#ifdef CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC_SUNXI
#define CONFIG_MMC_SUNXI_SLOT 0
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
#define CONFIG_SPL_FRAMEWORK
+#ifndef CONFIG_ARM64 /* AArch64 FEL support is not ready yet */
#define CONFIG_SPL_BOARD_LOAD_IMAGE
+#endif
#if defined(CONFIG_MACH_SUN9I)
#define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */
#define CONFIG_CMD_REGINFO
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
/*
* IFC Definitions
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-#define CONFIG_OMAP_HSMMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
/* GPIO banks */
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* NAND support */
#define CONFIG_CMD_NAND
#ifdef CONFIG_GENERIC_MMC
#undef CONFIG_GENERIC_MMC
#endif
-#ifdef CONFIG_TEGRA_MMC
-#undef CONFIG_TEGRA_MMC
-#endif
#ifdef CONFIG_CMD_MMC
#endif
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
#define CONFIG_OMAP_GPIO
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
/**
#define CONFIG_CMD_ASKEN
#define CONFIG_OMAP_GPIO
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
#define CONFIG_FS_FAT
* supports X-MODEM loading via UART, and we leverage this and then use
* Y-MODEM to load u-boot.img, when booted over UART.
*/
-#define CONFIG_SPL_TEXT_BASE 0x402F0400
+#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
"fit_bootfile=fitImage.itb\0" \
"update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}\0" \
"args_fit=setenv bootargs console=${console} \0" \
- "loadfit=run args_fit; bootm ${loadaddr}:kernel@1 " \
- "${loadaddr}:ramdisk@1 ${loadaddr}:${fdtfile};\0" \
+ "loadfit=run args_fit; bootm ${loadaddr}#${fdtfile};\0" \
/*
* DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_OMAP24XX
-/* MMC/SD IP block */
-#define CONFIG_OMAP_HSMMC
-
/* SPI IP Block */
#define CONFIG_OMAP3_SPI
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
-#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
/* MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
/* I2C */
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in SPI */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_HW_WATCHDOG
-#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX
-
/* text base address used when linking */
#define CONFIG_SYS_TEXT_BASE 0x90008000
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
-
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
-
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_TEGRA_UARTA_UAA_UAB
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER
-
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC */
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA_MMC
/*
* Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes
# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000
# endif
+# define CONFIG_ENV_IS_IN_FAT
+# define FAT_ENV_DEVICE_AND_PART "0:auto"
+# define FAT_ENV_FILE "uboot.env"
+# define FAT_ENV_INTERFACE "mmc"
#endif
#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQMP_USB)
#if defined(CONFIG_ZYNQMP_USB)
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_XHCI_ZYNQMP
#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define DFU_ALT_INFO \
DFU_ALT_INFO_RAM
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_USB_FUNCTION_FASTBOOT
+# define CONFIG_CMD_FASTBOOT
+# define CONFIG_ANDROID_BOOT_IMAGE
+# define CONFIG_FASTBOOT_BUF_ADDR 0x100000
+# define CONFIG_FASTBOOT_BUF_SIZE 0x6000000
+# define CONFIG_FASTBOOT_FLASH
+# ifdef CONFIG_ZYNQ_SDHCI
+# define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
+# endif
+# define CONFIG_PARTITION_UUIDS
+# define CONFIG_CMD_GPT
+
+# define CONFIG_RANDOM_UUID
+# define PARTS_DEFAULT \
+ "partitions=uuid_disk=${uuid_gpt_disk};" \
+ "name=""boot"",size=16M,uuid=${uuid_gpt_boot};" \
+ "name=""Linux"",size=-M,uuid=${uuid_gpt_Linux}\0"
+#endif
#endif
#if !defined(DFU_ALT_INFO)
# define DFU_ALT_INFO
#endif
+#if !defined(PARTS_DEFAULT)
+# define PARTS_DEFAULT
+#endif
+
#define CONFIG_BOARD_LATE_INIT
/* Do not preserve environment */
+#if !defined(CONFIG_ENV_IS_IN_FAT)
#define CONFIG_ENV_IS_NOWHERE 1
-#define CONFIG_ENV_SIZE 0x1000
+#endif
+#define CONFIG_ENV_SIZE 0x8000
/* Monitor Command Prompt */
/* Console I/O Buffer Size */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_RAM_DEVICE
/* u-boot is like dtb */
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin"
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_SDHCI1
-#define CONFIG_AHCI
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
#include <configs/xilinx_zynqmp.h>
/*
* DDR config
*/
-#define CONFIG_SYS_FSL_DDR2
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_DDR_ECC
/*
* High Level Configuration Options
*/
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_XPEDITE5200 1
#define CONFIG_SYS_BOARD_NAME "XPedite5200"
#define CONFIG_SYS_FORM_PMC_XMC 1
/*
* DDR config
*/
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x54
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#define CONFIG_DDR_ECC
/*
* High Level Configuration Options
*/
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_SYS_BOARD_NAME "XPedite5370"
#define CONFIG_SYS_FORM_3U_VPX 1
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
/*
* DDR config
*/
-#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_DDR_ECC
/*
* High Level Configuration Options
*/
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_XPEDITE550X 1
#define CONFIG_SYS_BOARD_NAME "XPedite5500"
#define CONFIG_SYS_FORM_PMC_XMC 1
/*
* DDR config
*/
-#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x54
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#define CONFIG_DDR_ECC
#define CONFIG_SYS_TIMER_COUNTER \
(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
-#define CONFIG_MACH_TYPE MACH_TYPE_ZMX25
/*
* Environment settings
*/
# define CONFIG_PHY_MARVELL
# define CONFIG_PHY_REALTEK
# define CONFIG_PHY_XILINX
-# define CONFIG_BOOTP_SERVERIP
# define CONFIG_BOOTP_BOOTPATH
# define CONFIG_BOOTP_GATEWAY
# define CONFIG_BOOTP_HOSTNAME
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-/* Physical Memory map */
-#define CONFIG_SYS_TEXT_BASE 0x4000000
-
#ifndef CONFIG_NR_DRAM_BANKS
# define CONFIG_NR_DRAM_BANKS 1
#endif
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-zynq/u-boot-spl.lds"
#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
/* All controllers are for main memory */
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS
#endif
#ifdef CONFIG_SYS_FSL_DDR_LE
*
* All data structures have to be on the stack
*/
-#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
typedef struct {
#define sec_in16(a) in_be16(a)
#define sec_clrbits32 clrbits_be32
#define sec_setbits32 setbits_be32
-#else
+#elif defined(CONFIG_SYS_FSL_HAS_SEC)
#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
#endif
/* image node */
#define FIT_DATA_PROP "data"
+#define FIT_DATA_OFFSET_PROP "data-offset"
+#define FIT_DATA_SIZE_PROP "data-size"
#define FIT_TIMESTAMP_PROP "timestamp"
#define FIT_DESC_PROP "description"
#define FIT_ARCH_PROP "arch"
int fit_image_get_entry(const void *fit, int noffset, ulong *entry);
int fit_image_get_data(const void *fit, int noffset,
const void **data, size_t *size);
+int fit_image_get_data_offset(const void *fit, int noffset, int *data_offset);
+int fit_image_get_data_size(const void *fit, int noffset, int *data_size);
int fit_image_hash_get_algo(const void *fit, int noffset, char **algo);
int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value,
* @fit: Pointer to the FIT format image header
* @comment: Comment to add to signature nodes
* @require_keys: Mark all keys as 'required'
+ * @engine_id: Engine to use for signing
*
* Adds hash values for all component images in the FIT blob.
* Hashes are calculated for all component images which have hash subnodes
* libfdt error code, on failure
*/
int fit_add_verification_data(const char *keydir, void *keydest, void *fit,
- const char *comment, int require_keys);
+ const char *comment, int require_keys,
+ const char *engine_id);
int fit_image_verify(const void *fit, int noffset);
int fit_config_verify(const void *fit, int conf_noffset);
const void *fdt_blob; /* FDT containing public keys */
int required_keynode; /* Node offset of key to use: -1=any */
const char *require_keys; /* Value for 'required' property */
+ const char *engine_id; /* Engine to use for signing */
};
#endif /* Allow struct image_region to always be defined for rsa.h */
extern struct p_current *current;
-#define ndelay(x) udelay((x) < 1000 ? 1 : (x)/1000)
-
#define dev_dbg(dev, fmt, args...) \
debug(fmt, ##args)
#define dev_vdbg(dev, fmt, args...) \
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _LINUX_DELAY_H
+#define _LINUX_DELAY_H
+
+#include <linux/kernel.h>
+
+void __udelay(unsigned long usec);
+void udelay(unsigned long usec);
+
+static inline void mdelay(unsigned long msec)
+{
+ while (msec--)
+ udelay(1000);
+}
+
+static inline void ndelay(unsigned long nsec)
+{
+ udelay(DIV_ROUND_UP(nsec, 1000));
+}
+
+#endif /* defined(_LINUX_DELAY_H) */
--- /dev/null
+/*
+ * Copyright (c) 2012-2014 The Linux Foundation. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _LINUX_IOPOLL_H
+#define _LINUX_IOPOLL_H
+
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <time.h>
+
+/**
+ * readx_poll_timeout - Periodically poll an address until a condition is met or a timeout occurs
+ * @op: accessor function (takes @addr as its only argument)
+ * @addr: Address to poll
+ * @val: Variable to read the value into
+ * @cond: Break condition (usually involving @val)
+ * @timeout_us: Timeout in us, 0 means never timeout
+ *
+ * Returns 0 on success and -ETIMEDOUT upon a timeout. In either
+ * case, the last read value at @addr is stored in @val.
+ *
+ * When available, you'll probably want to use one of the specialized
+ * macros defined below rather than this macro directly.
+ */
+#define readx_poll_timeout(op, addr, val, cond, timeout_us) \
+({ \
+ unsigned long timeout = timer_get_us() + timeout_us; \
+ for (;;) { \
+ (val) = op(addr); \
+ if (cond) \
+ break; \
+ if (timeout_us && time_after(timer_get_us(), timeout)) { \
+ (val) = op(addr); \
+ break; \
+ } \
+ } \
+ (cond) ? 0 : -ETIMEDOUT; \
+})
+
+
+#define readb_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readb, addr, val, cond, timeout_us)
+
+#define readw_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readw, addr, val, cond, timeout_us)
+
+#define readl_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readl, addr, val, cond, timeout_us)
+
+#define readq_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readq, addr, val, cond, timeout_us)
+
+#define readb_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readb_relaxed, addr, val, cond, timeout_us)
+
+#define readw_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readw_relaxed, addr, val, cond, timeout_us)
+
+#define readl_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readl_relaxed, addr, val, cond, timeout_us)
+
+#define readq_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+ readx_poll_timeout(readq_relaxed, addr, val, cond, timeout_us)
+
+#endif /* _LINUX_IOPOLL_H */
--- /dev/null
+#ifndef TYPECHECK_H_INCLUDED
+#define TYPECHECK_H_INCLUDED
+
+/*
+ * Check at compile time that something is of a particular type.
+ * Always evaluates to 1 so you may use it easily in comparisons.
+ */
+#define typecheck(type,x) \
+({ type __dummy; \
+ typeof(x) __dummy2; \
+ (void)(&__dummy == &__dummy2); \
+ 1; \
+})
+
+/*
+ * Check at compile time that 'function' is a certain type, or is a pointer
+ * to that type (needs to use typedef for the function type.)
+ */
+#define typecheck_fn(type,function) \
+({ typeof(type) __tmp = function; \
+ (void)__tmp; \
+})
+
+#endif /* TYPECHECK_H_INCLUDED */
struct mmc_ops {
int (*send_cmd)(struct mmc *mmc,
struct mmc_cmd *cmd, struct mmc_data *data);
- void (*set_ios)(struct mmc *mmc);
+ int (*set_ios)(struct mmc *mmc);
int (*init)(struct mmc *mmc);
int (*getcd)(struct mmc *mmc);
int (*getwp)(struct mmc *mmc);
/*
+ * Initialize USB ethernet device with CONFIG_DM_ETH
+ * Returns:
+ * 0 is success, non-zero is error status.
+ */
+int usb_ether_init(void);
+
+/*
* Get the hardware address for an ethernet interface .
* Args:
* base_name - base name for device (normally "eth")
#define SDHCI_ARGUMENT 0x08
#define SDHCI_TRANSFER_MODE 0x0C
-#define SDHCI_TRNS_DMA 0x01
-#define SDHCI_TRNS_BLK_CNT_EN 0x02
-#define SDHCI_TRNS_ACMD12 0x04
-#define SDHCI_TRNS_READ 0x10
-#define SDHCI_TRNS_MULTI 0x20
+#define SDHCI_TRNS_DMA BIT(0)
+#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
+#define SDHCI_TRNS_ACMD12 BIT(2)
+#define SDHCI_TRNS_READ BIT(4)
+#define SDHCI_TRNS_MULTI BIT(5)
#define SDHCI_COMMAND 0x0E
#define SDHCI_CMD_RESP_MASK 0x03
#define SDHCI_BUFFER 0x20
#define SDHCI_PRESENT_STATE 0x24
-#define SDHCI_CMD_INHIBIT 0x00000001
-#define SDHCI_DATA_INHIBIT 0x00000002
-#define SDHCI_DOING_WRITE 0x00000100
-#define SDHCI_DOING_READ 0x00000200
-#define SDHCI_SPACE_AVAILABLE 0x00000400
-#define SDHCI_DATA_AVAILABLE 0x00000800
-#define SDHCI_CARD_PRESENT 0x00010000
-#define SDHCI_CARD_STATE_STABLE 0x00020000
-#define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000
-#define SDHCI_WRITE_PROTECT 0x00080000
+#define SDHCI_CMD_INHIBIT BIT(0)
+#define SDHCI_DATA_INHIBIT BIT(1)
+#define SDHCI_DOING_WRITE BIT(8)
+#define SDHCI_DOING_READ BIT(9)
+#define SDHCI_SPACE_AVAILABLE BIT(10)
+#define SDHCI_DATA_AVAILABLE BIT(11)
+#define SDHCI_CARD_PRESENT BIT(16)
+#define SDHCI_CARD_STATE_STABLE BIT(17)
+#define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
+#define SDHCI_WRITE_PROTECT BIT(19)
#define SDHCI_HOST_CONTROL 0x28
-#define SDHCI_CTRL_LED 0x01
-#define SDHCI_CTRL_4BITBUS 0x02
-#define SDHCI_CTRL_HISPD 0x04
+#define SDHCI_CTRL_LED BIT(0)
+#define SDHCI_CTRL_4BITBUS BIT(1)
+#define SDHCI_CTRL_HISPD BIT(2)
#define SDHCI_CTRL_DMA_MASK 0x18
#define SDHCI_CTRL_SDMA 0x00
#define SDHCI_CTRL_ADMA1 0x08
#define SDHCI_CTRL_ADMA32 0x10
#define SDHCI_CTRL_ADMA64 0x18
-#define SDHCI_CTRL_8BITBUS 0x20
-#define SDHCI_CTRL_CD_TEST_INS 0x40
-#define SDHCI_CTRL_CD_TEST 0x80
+#define SDHCI_CTRL_8BITBUS BIT(5)
+#define SDHCI_CTRL_CD_TEST_INS BIT(6)
+#define SDHCI_CTRL_CD_TEST BIT(7)
#define SDHCI_POWER_CONTROL 0x29
#define SDHCI_POWER_ON 0x01
#define SDHCI_BLOCK_GAP_CONTROL 0x2A
#define SDHCI_WAKE_UP_CONTROL 0x2B
-#define SDHCI_WAKE_ON_INT 0x01
-#define SDHCI_WAKE_ON_INSERT 0x02
-#define SDHCI_WAKE_ON_REMOVE 0x04
+#define SDHCI_WAKE_ON_INT BIT(0)
+#define SDHCI_WAKE_ON_INSERT BIT(1)
+#define SDHCI_WAKE_ON_REMOVE BIT(2)
#define SDHCI_CLOCK_CONTROL 0x2C
#define SDHCI_DIVIDER_SHIFT 8
#define SDHCI_DIV_MASK 0xFF
#define SDHCI_DIV_MASK_LEN 8
#define SDHCI_DIV_HI_MASK 0x300
-#define SDHCI_PROG_CLOCK_MODE 0x0020
-#define SDHCI_CLOCK_CARD_EN 0x0004
-#define SDHCI_CLOCK_INT_STABLE 0x0002
-#define SDHCI_CLOCK_INT_EN 0x0001
+#define SDHCI_PROG_CLOCK_MODE BIT(5)
+#define SDHCI_CLOCK_CARD_EN BIT(2)
+#define SDHCI_CLOCK_INT_STABLE BIT(1)
+#define SDHCI_CLOCK_INT_EN BIT(0)
#define SDHCI_TIMEOUT_CONTROL 0x2E
#define SDHCI_INT_STATUS 0x30
#define SDHCI_INT_ENABLE 0x34
#define SDHCI_SIGNAL_ENABLE 0x38
-#define SDHCI_INT_RESPONSE 0x00000001
-#define SDHCI_INT_DATA_END 0x00000002
-#define SDHCI_INT_DMA_END 0x00000008
-#define SDHCI_INT_SPACE_AVAIL 0x00000010
-#define SDHCI_INT_DATA_AVAIL 0x00000020
-#define SDHCI_INT_CARD_INSERT 0x00000040
-#define SDHCI_INT_CARD_REMOVE 0x00000080
-#define SDHCI_INT_CARD_INT 0x00000100
-#define SDHCI_INT_ERROR 0x00008000
-#define SDHCI_INT_TIMEOUT 0x00010000
-#define SDHCI_INT_CRC 0x00020000
-#define SDHCI_INT_END_BIT 0x00040000
-#define SDHCI_INT_INDEX 0x00080000
-#define SDHCI_INT_DATA_TIMEOUT 0x00100000
-#define SDHCI_INT_DATA_CRC 0x00200000
-#define SDHCI_INT_DATA_END_BIT 0x00400000
-#define SDHCI_INT_BUS_POWER 0x00800000
-#define SDHCI_INT_ACMD12ERR 0x01000000
-#define SDHCI_INT_ADMA_ERROR 0x02000000
+#define SDHCI_INT_RESPONSE BIT(0)
+#define SDHCI_INT_DATA_END BIT(1)
+#define SDHCI_INT_DMA_END BIT(3)
+#define SDHCI_INT_SPACE_AVAIL BIT(4)
+#define SDHCI_INT_DATA_AVAIL BIT(5)
+#define SDHCI_INT_CARD_INSERT BIT(6)
+#define SDHCI_INT_CARD_REMOVE BIT(7)
+#define SDHCI_INT_CARD_INT BIT(8)
+#define SDHCI_INT_ERROR BIT(15)
+#define SDHCI_INT_TIMEOUT BIT(16)
+#define SDHCI_INT_CRC BIT(17)
+#define SDHCI_INT_END_BIT BIT(18)
+#define SDHCI_INT_INDEX BIT(19)
+#define SDHCI_INT_DATA_TIMEOUT BIT(20)
+#define SDHCI_INT_DATA_CRC BIT(21)
+#define SDHCI_INT_DATA_END_BIT BIT(22)
+#define SDHCI_INT_BUS_POWER BIT(23)
+#define SDHCI_INT_ACMD12ERR BIT(24)
+#define SDHCI_INT_ADMA_ERROR BIT(25)
#define SDHCI_INT_NORMAL_MASK 0x00007FFF
#define SDHCI_INT_ERROR_MASK 0xFFFF8000
#define SDHCI_CLOCK_BASE_SHIFT 8
#define SDHCI_MAX_BLOCK_MASK 0x00030000
#define SDHCI_MAX_BLOCK_SHIFT 16
-#define SDHCI_CAN_DO_8BIT 0x00040000
-#define SDHCI_CAN_DO_ADMA2 0x00080000
-#define SDHCI_CAN_DO_ADMA1 0x00100000
-#define SDHCI_CAN_DO_HISPD 0x00200000
-#define SDHCI_CAN_DO_SDMA 0x00400000
-#define SDHCI_CAN_VDD_330 0x01000000
-#define SDHCI_CAN_VDD_300 0x02000000
-#define SDHCI_CAN_VDD_180 0x04000000
-#define SDHCI_CAN_64BIT 0x10000000
+#define SDHCI_CAN_DO_8BIT BIT(18)
+#define SDHCI_CAN_DO_ADMA2 BIT(19)
+#define SDHCI_CAN_DO_ADMA1 BIT(20)
+#define SDHCI_CAN_DO_HISPD BIT(21)
+#define SDHCI_CAN_DO_SDMA BIT(22)
+#define SDHCI_CAN_VDD_330 BIT(24)
+#define SDHCI_CAN_VDD_300 BIT(25)
+#define SDHCI_CAN_VDD_180 BIT(26)
+#define SDHCI_CAN_64BIT BIT(28)
#define SDHCI_CAPABILITIES_1 0x44
#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
-#define SDHCI_QUIRK_NO_CD (1 << 5)
#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
-#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 7)
#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
/* to make gcc happy */
#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
struct sdhci_ops {
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
- u32 (*read_l)(struct sdhci_host *host, int reg);
- u16 (*read_w)(struct sdhci_host *host, int reg);
- u8 (*read_b)(struct sdhci_host *host, int reg);
- void (*write_l)(struct sdhci_host *host, u32 val, int reg);
- void (*write_w)(struct sdhci_host *host, u16 val, int reg);
- void (*write_b)(struct sdhci_host *host, u8 val, int reg);
+ u32 (*read_l)(struct sdhci_host *host, int reg);
+ u16 (*read_w)(struct sdhci_host *host, int reg);
+ u8 (*read_b)(struct sdhci_host *host, int reg);
+ void (*write_l)(struct sdhci_host *host, u32 val, int reg);
+ void (*write_w)(struct sdhci_host *host, u16 val, int reg);
+ void (*write_b)(struct sdhci_host *host, u8 val, int reg);
#endif
+ int (*get_cd)(struct sdhci_host *host);
+ void (*set_control_reg)(struct sdhci_host *host);
+ void (*set_clock)(struct sdhci_host *host, u32 div);
};
struct sdhci_host {
struct gpio_desc pwr_gpio; /* Power GPIO */
struct gpio_desc cd_gpio; /* Card Detect GPIO */
- void (*set_control_reg)(struct sdhci_host *host);
- void (*set_clock)(int dev_index, unsigned int div);
uint voltages;
struct mmc_config cfg;
struct spl_image_info {
const char *name;
u8 os;
- u32 load_addr;
- u32 entry_point;
+ ulong load_addr;
+ ulong entry_point;
u32 size;
u32 flags;
};
};
enum splash_flags {
- SPLASH_STORAGE_RAW,
- SPLASH_STORAGE_FS,
+ SPLASH_STORAGE_RAW, /* Stored in raw memory */
+ SPLASH_STORAGE_FS, /* Stored within a file system */
+ SPLASH_STORAGE_FIT, /* Stored inside a FIT image */
};
struct splash_location {
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TIME_H
+#define _TIME_H
+
+#include <linux/typecheck.h>
+
+unsigned long get_timer(unsigned long base);
+
+/*
+ * Return the current value of a monotonically increasing microsecond timer.
+ * Granularity may be larger than 1us if hardware does not support this.
+ */
+unsigned long timer_get_us(void);
+
+/*
+ * These inlines deal with timer wrapping correctly. You are
+ * strongly encouraged to use them
+ * 1. Because people otherwise forget
+ * 2. Because if the timer wrap changes in future you won't have to
+ * alter your driver code.
+ *
+ * time_after(a,b) returns true if the time a is after time b.
+ *
+ * Do this with "<0" and ">=0" to only test the sign of the result. A
+ * good compiler would generate better code (and a really good compiler
+ * wouldn't care). Gcc is currently neither.
+ */
+#define time_after(a,b) \
+ (typecheck(unsigned long, a) && \
+ typecheck(unsigned long, b) && \
+ ((long)((b) - (a)) < 0))
+#define time_before(a,b) time_after(b,a)
+
+#define time_after_eq(a,b) \
+ (typecheck(unsigned long, a) && \
+ typecheck(unsigned long, b) && \
+ ((long)((a) - (b)) >= 0))
+#define time_before_eq(a,b) time_after_eq(b,a)
+
+/*
+ * Calculate whether a is in the range of [b, c].
+ */
+#define time_in_range(a,b,c) \
+ (time_after_eq(a,b) && \
+ time_before_eq(a,c))
+
+/*
+ * Calculate whether a is in the range of [b, c).
+ */
+#define time_in_range_open(a,b,c) \
+ (time_after_eq(a,b) && \
+ time_before(a,c))
+
+#endif /* _TIME_H */
#include <common.h>
#include <console.h>
+#include <watchdog.h>
#include <linux/errno.h>
#include <asm/io.h>
}
udelay(1);
+ WATCHDOG_RESET();
}
debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", prefix, reg, mask,
--- /dev/null
+*.efi
+*.so
int symbol_off, fixup_off;
int prop_len;
+ if (symbols_off < 0)
+ return symbols_off;
+
symbol_path = fdt_getprop(fdt, symbols_off, label,
&prop_len);
if (!symbol_path)
/* We can have overlays without any fixups */
fixups_off = fdt_path_offset(fdto, "/__fixups__");
- if ((fixups_off < 0 && (fixups_off != -FDT_ERR_NOTFOUND)))
+ if (fixups_off == -FDT_ERR_NOTFOUND)
+ return 0; /* nothing to do */
+ if (fixups_off < 0)
return fixups_off;
/* And base DTs without symbols */
for (addr.s_addr = 0, i = 0; i < 4; ++i) {
ulong val = s ? simple_strtoul(s, &e, 10) : 0;
+ if (val > 255) {
+ addr.s_addr = 0;
+ return addr;
+ }
+ if (i != 3 && *e != '.') {
+ addr.s_addr = 0;
+ return addr;
+ }
addr.s_addr <<= 8;
addr.s_addr |= (val & 0xFF);
if (s) {
#include <openssl/err.h>
#include <openssl/ssl.h>
#include <openssl/evp.h>
+#include <openssl/engine.h>
#if OPENSSL_VERSION_NUMBER >= 0x10000000L
#define HAVE_ERR_REMOVE_THREAD_STATE
}
/**
- * rsa_get_pub_key() - read a public key from a .crt file
+ * rsa_pem_get_pub_key() - read a public key from a .crt file
*
* @keydir: Directory containins the key
* @name Name of key file (will have a .crt extension)
* @rsap Returns RSA object, or NULL on failure
* @return 0 if ok, -ve on error (in which case *rsap will be set to NULL)
*/
-static int rsa_get_pub_key(const char *keydir, const char *name, RSA **rsap)
+static int rsa_pem_get_pub_key(const char *keydir, const char *name, RSA **rsap)
{
char path[1024];
EVP_PKEY *key;
}
/**
- * rsa_get_priv_key() - read a private key from a .key file
+ * rsa_engine_get_pub_key() - read a public key from given engine
*
- * @keydir: Directory containins the key
+ * @keydir: Key prefix
+ * @name Name of key
+ * @engine Engine to use
+ * @rsap Returns RSA object, or NULL on failure
+ * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL)
+ */
+static int rsa_engine_get_pub_key(const char *keydir, const char *name,
+ ENGINE *engine, RSA **rsap)
+{
+ const char *engine_id;
+ char key_id[1024];
+ EVP_PKEY *key;
+ RSA *rsa;
+ int ret;
+
+ *rsap = NULL;
+
+ engine_id = ENGINE_get_id(engine);
+
+ if (engine_id && !strcmp(engine_id, "pkcs11")) {
+ if (keydir)
+ snprintf(key_id, sizeof(key_id),
+ "pkcs11:%s;object=%s;type=public",
+ keydir, name);
+ else
+ snprintf(key_id, sizeof(key_id),
+ "pkcs11:object=%s;type=public",
+ name);
+ } else {
+ fprintf(stderr, "Engine not supported\n");
+ return -ENOTSUP;
+ }
+
+ key = ENGINE_load_public_key(engine, key_id, NULL, NULL);
+ if (!key)
+ return rsa_err("Failure loading public key from engine");
+
+ /* Convert to a RSA_style key. */
+ rsa = EVP_PKEY_get1_RSA(key);
+ if (!rsa) {
+ rsa_err("Couldn't convert to a RSA style key");
+ ret = -EINVAL;
+ goto err_rsa;
+ }
+
+ EVP_PKEY_free(key);
+ *rsap = rsa;
+
+ return 0;
+
+err_rsa:
+ EVP_PKEY_free(key);
+ return ret;
+}
+
+/**
+ * rsa_get_pub_key() - read a public key
+ *
+ * @keydir: Directory containing the key (PEM file) or key prefix (engine)
+ * @name Name of key file (will have a .crt extension)
+ * @engine Engine to use
+ * @rsap Returns RSA object, or NULL on failure
+ * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL)
+ */
+static int rsa_get_pub_key(const char *keydir, const char *name,
+ ENGINE *engine, RSA **rsap)
+{
+ if (engine)
+ return rsa_engine_get_pub_key(keydir, name, engine, rsap);
+ return rsa_pem_get_pub_key(keydir, name, rsap);
+}
+
+/**
+ * rsa_pem_get_priv_key() - read a private key from a .key file
+ *
+ * @keydir: Directory containing the key
* @name Name of key file (will have a .key extension)
* @rsap Returns RSA object, or NULL on failure
* @return 0 if ok, -ve on error (in which case *rsap will be set to NULL)
*/
-static int rsa_get_priv_key(const char *keydir, const char *name, RSA **rsap)
+static int rsa_pem_get_priv_key(const char *keydir, const char *name,
+ RSA **rsap)
{
char path[1024];
RSA *rsa;
return 0;
}
+/**
+ * rsa_engine_get_priv_key() - read a private key from given engine
+ *
+ * @keydir: Key prefix
+ * @name Name of key
+ * @engine Engine to use
+ * @rsap Returns RSA object, or NULL on failure
+ * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL)
+ */
+static int rsa_engine_get_priv_key(const char *keydir, const char *name,
+ ENGINE *engine, RSA **rsap)
+{
+ const char *engine_id;
+ char key_id[1024];
+ EVP_PKEY *key;
+ RSA *rsa;
+ int ret;
+
+ *rsap = NULL;
+
+ engine_id = ENGINE_get_id(engine);
+
+ if (engine_id && !strcmp(engine_id, "pkcs11")) {
+ if (keydir)
+ snprintf(key_id, sizeof(key_id),
+ "pkcs11:%s;object=%s;type=private",
+ keydir, name);
+ else
+ snprintf(key_id, sizeof(key_id),
+ "pkcs11:object=%s;type=private",
+ name);
+ } else {
+ fprintf(stderr, "Engine not supported\n");
+ return -ENOTSUP;
+ }
+
+ key = ENGINE_load_private_key(engine, key_id, NULL, NULL);
+ if (!key)
+ return rsa_err("Failure loading private key from engine");
+
+ /* Convert to a RSA_style key. */
+ rsa = EVP_PKEY_get1_RSA(key);
+ if (!rsa) {
+ rsa_err("Couldn't convert to a RSA style key");
+ ret = -EINVAL;
+ goto err_rsa;
+ }
+
+ EVP_PKEY_free(key);
+ *rsap = rsa;
+
+ return 0;
+
+err_rsa:
+ EVP_PKEY_free(key);
+ return ret;
+}
+
+/**
+ * rsa_get_priv_key() - read a private key
+ *
+ * @keydir: Directory containing the key (PEM file) or key prefix (engine)
+ * @name Name of key
+ * @engine Engine to use for signing
+ * @rsap Returns RSA object, or NULL on failure
+ * @return 0 if ok, -ve on error (in which case *rsap will be set to NULL)
+ */
+static int rsa_get_priv_key(const char *keydir, const char *name,
+ ENGINE *engine, RSA **rsap)
+{
+ if (engine)
+ return rsa_engine_get_priv_key(keydir, name, engine, rsap);
+ return rsa_pem_get_priv_key(keydir, name, rsap);
+}
+
static int rsa_init(void)
{
int ret;
return 0;
}
+static int rsa_engine_init(const char *engine_id, ENGINE **pe)
+{
+ ENGINE *e;
+ int ret;
+
+ ENGINE_load_builtin_engines();
+
+ e = ENGINE_by_id(engine_id);
+ if (!e) {
+ fprintf(stderr, "Engine isn't available\n");
+ ret = -1;
+ goto err_engine_by_id;
+ }
+
+ if (!ENGINE_init(e)) {
+ fprintf(stderr, "Couldn't initialize engine\n");
+ ret = -1;
+ goto err_engine_init;
+ }
+
+ if (!ENGINE_set_default_RSA(e)) {
+ fprintf(stderr, "Couldn't set engine as default for RSA\n");
+ ret = -1;
+ goto err_set_rsa;
+ }
+
+ *pe = e;
+
+ return 0;
+
+err_set_rsa:
+ ENGINE_finish(e);
+err_engine_init:
+ ENGINE_free(e);
+err_engine_by_id:
+ ENGINE_cleanup();
+ return ret;
+}
+
static void rsa_remove(void)
{
CRYPTO_cleanup_all_ex_data();
EVP_cleanup();
}
+static void rsa_engine_remove(ENGINE *e)
+{
+ if (e) {
+ ENGINE_finish(e);
+ ENGINE_free(e);
+ }
+}
+
static int rsa_sign_with_key(RSA *rsa, struct checksum_algo *checksum_algo,
const struct image_region region[], int region_count,
uint8_t **sigp, uint *sig_size)
uint8_t **sigp, uint *sig_len)
{
RSA *rsa;
+ ENGINE *e = NULL;
int ret;
ret = rsa_init();
if (ret)
return ret;
- ret = rsa_get_priv_key(info->keydir, info->keyname, &rsa);
+ if (info->engine_id) {
+ ret = rsa_engine_init(info->engine_id, &e);
+ if (ret)
+ goto err_engine;
+ }
+
+ ret = rsa_get_priv_key(info->keydir, info->keyname, e, &rsa);
if (ret)
goto err_priv;
ret = rsa_sign_with_key(rsa, info->checksum, region,
goto err_sign;
RSA_free(rsa);
+ if (info->engine_id)
+ rsa_engine_remove(e);
rsa_remove();
return ret;
err_sign:
RSA_free(rsa);
err_priv:
+ if (info->engine_id)
+ rsa_engine_remove(e);
+err_engine:
rsa_remove();
return ret;
}
int ret;
int bits;
RSA *rsa;
+ ENGINE *e = NULL;
debug("%s: Getting verification data\n", __func__);
- ret = rsa_get_pub_key(info->keydir, info->keyname, &rsa);
+ if (info->engine_id) {
+ ret = rsa_engine_init(info->engine_id, &e);
+ if (ret)
+ return ret;
+ }
+ ret = rsa_get_pub_key(info->keydir, info->keyname, e, &rsa);
if (ret)
- return ret;
+ goto err_get_pub_key;
ret = rsa_get_params(rsa, &exponent, &n0_inv, &modulus, &r_squared);
if (ret)
- return ret;
+ goto err_get_params;
bits = BN_num_bits(modulus);
parent = fdt_subnode_offset(keydest, 0, FIT_SIG_NODENAME);
if (parent == -FDT_ERR_NOTFOUND) {
BN_free(modulus);
BN_free(r_squared);
if (ret)
- return ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO;
+ ret = ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO;
+err_get_params:
+ RSA_free(rsa);
+err_get_pub_key:
+ if (info->engine_id)
+ rsa_engine_remove(e);
- return 0;
+ return ret;
}
usec -= kv;
} while(usec);
}
-
-void mdelay(unsigned long msec)
-{
- while (msec--)
- udelay(1000);
-}
info->zs = 1;
}
-static void div_out(struct printf_info *info, unsigned int *num,
- unsigned int div)
+static void div_out(struct printf_info *info, unsigned long *num,
+ unsigned long div)
{
unsigned char dgt = 0;
{
char ch;
char *p;
- unsigned int num;
+ unsigned long num;
char buf[12];
- unsigned int div;
+ unsigned long div;
while ((ch = *(fmt++))) {
if (ch != '%') {
} else {
bool lz = false;
int width = 0;
+ bool islong = false;
ch = *(fmt++);
+ if (ch == '-')
+ ch = *(fmt++);
+
if (ch == '0') {
ch = *(fmt++);
lz = 1;
ch = *fmt++;
}
}
+ if (ch == 'l') {
+ ch = *(fmt++);
+ islong = true;
+ }
+
info->bf = buf;
p = info->bf;
info->zs = 0;
goto abort;
case 'u':
case 'd':
- num = va_arg(va, unsigned int);
- if (ch == 'd' && (int)num < 0) {
- num = -(int)num;
- out(info, '-');
+ div = 1000000000;
+ if (islong) {
+ num = va_arg(va, unsigned long);
+ if (sizeof(long) > 4)
+ div *= div * 10;
+ } else {
+ num = va_arg(va, unsigned int);
+ }
+
+ if (ch == 'd') {
+ if (islong && (long)num < 0) {
+ num = -(long)num;
+ out(info, '-');
+ } else if (!islong && (int)num < 0) {
+ num = -(int)num;
+ out(info, '-');
+ }
}
if (!num) {
out_dgt(info, 0);
} else {
- for (div = 1000000000; div; div /= 10)
+ for (; div; div /= 10)
div_out(info, &num, div);
}
break;
case 'x':
- num = va_arg(va, unsigned int);
+ if (islong) {
+ num = va_arg(va, unsigned long);
+ div = 1UL << (sizeof(long) * 8 - 4);
+ } else {
+ num = va_arg(va, unsigned int);
+ div = 0x10000000;
+ }
if (!num) {
out_dgt(info, 0);
} else {
- for (div = 0x10000000; div; div /= 0x10)
+ for (; div; div /= 0x10)
div_out(info, &num, div);
}
break;
# Bring in any U-Boot-specific include after the '/dts-v1/;' header
cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
cat $< $(if $(u_boot_dtsi),\
- | sed 's%^/ {$$%\#include \"$(u_boot_dtsi)\"\n&%') | \
+ | sed '/^\/ {$$/{x;s%$$%\#include \"$(u_boot_dtsi)\"%;G;}') | \
$(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) - ; \
$(DTC) -O dtb -o $@ -b 0 \
-i $(dir $<) $(DTC_FLAGS) \
$(obj)/%_efi.S: $(obj)/%.efi
$(call cmd,S_efi)
-$(obj)/%.efi: $(obj)/%.so
- $(OBJCOPY) -j .header -j .text -j .sdata -j .data -j .dynamic \
- -j .dynsym -j .rel* -j .rela* -j .reloc \
+quiet_cmd_efi_objcopy = OBJCOPY $@
+cmd_efi_objcopy = $(OBJCOPY) -j .header -j .text -j .sdata -j .data -j \
+ .dynamic -j .dynsym -j .rel* -j .rela* -j .reloc \
$(if $(EFI_TARGET),$(EFI_TARGET),-O binary) $^ $@
+$(obj)/%.efi: $(obj)/%.so
+ $(call cmd,efi_objcopy)
+
+quiet_cmd_efi_ld = LD $@
+cmd_efi_ld = $(LD) -nostdlib -znocombreloc -T $(EFI_LDS_PATH) -shared \
+ -Bsymbolic $^ -o $@
+
EFI_LDS_PATH = $(srctree)/arch/$(ARCH)/lib/$(EFI_LDS)
$(obj)/helloworld.so: $(EFI_LDS_PATH)
$(obj)/helloworld.so: $(obj)/helloworld.o arch/$(ARCH)/lib/$(EFI_CRT0) \
arch/$(ARCH)/lib/$(EFI_RELOC)
- $(LD) -nostdlib -znocombreloc -T $(EFI_LDS_PATH) -shared -Bsymbolic \
- $^ -o $@
+ $(call cmd,efi_ld)
# ACPI
# ---------------------------------------------------------------------------
CONFIG_AM335X_USB0_MODE
CONFIG_AM335X_USB1
CONFIG_AM335X_USB1_MODE
-CONFIG_AM33XX
CONFIG_AM437X_USB2PHY2_HOST
CONFIG_AMBAPP_IOAREA
CONFIG_AMCC_DEF_ENV
CONFIG_API
CONFIG_APUS_FAST_EXCEPT
CONFIG_AP_SH4A_4A
-CONFIG_ARCH_AAED2000
-CONFIG_ARCH_ADI_COYOTE
CONFIG_ARCH_ADPAG101P
-CONFIG_ARCH_AT91RM9200DK
-CONFIG_ARCH_AUTCPU12
-CONFIG_ARCH_BAST
-CONFIG_ARCH_CATS
-CONFIG_ARCH_CDB89712
-CONFIG_ARCH_CEIVA
-CONFIG_ARCH_CLEP7212
CONFIG_ARCH_CPU_INIT
CONFIG_ARCH_CSB226
CONFIG_ARCH_DMA_PIO_WORDS
CONFIG_ARCH_EARLY_INIT_R
-CONFIG_ARCH_EBSA110
-CONFIG_ARCH_EBSA285
-CONFIG_ARCH_EDB7211
-CONFIG_ARCH_ENP2611
-CONFIG_ARCH_FORTUNET
-CONFIG_ARCH_GUMSTIX
-CONFIG_ARCH_H1940
-CONFIG_ARCH_H5400
-CONFIG_ARCH_H7201
-CONFIG_ARCH_H7202
CONFIG_ARCH_HAS_ILOG2_U32
CONFIG_ARCH_HAS_ILOG2_U64
CONFIG_ARCH_INNOKOM
-CONFIG_ARCH_IQ31244
-CONFIG_ARCH_IQ80321
-CONFIG_ARCH_IQ80331
-CONFIG_ARCH_IXCDP1100
-CONFIG_ARCH_IXDP2400
-CONFIG_ARCH_IXDP2401
-CONFIG_ARCH_IXDP2800
-CONFIG_ARCH_IXDP2801
-CONFIG_ARCH_IXDP425
CONFIG_ARCH_KIRKWOOD
-CONFIG_ARCH_KS8695
-CONFIG_ARCH_L7200
CONFIG_ARCH_LUBBOCK
CONFIG_ARCH_MAP_SYSMEM
CONFIG_ARCH_MISC_INIT
-CONFIG_ARCH_MX1ADS
-CONFIG_ARCH_NETWINDER
-CONFIG_ARCH_OMAP2
CONFIG_ARCH_OMAP4
CONFIG_ARCH_ORION5X
-CONFIG_ARCH_P720T
-CONFIG_ARCH_PERSONAL_SERVER
CONFIG_ARCH_PLEB
CONFIG_ARCH_PXA_CERF
CONFIG_ARCH_PXA_IDP
CONFIG_ARCH_RMOBILE_BOARD_STRING
CONFIG_ARCH_RMOBILE_EXTRAM_BOOT
-CONFIG_ARCH_RPC
-CONFIG_ARCH_S3C2440
-CONFIG_ARCH_SHARK
CONFIG_ARCH_TEGRA
CONFIG_ARCH_USE_BUILTIN_BSWAP
-CONFIG_ARCH_VERSATILE_PB
-CONFIG_ARCH_VIPER
CONFIG_ARC_MMU_VER
CONFIG_ARC_SERIAL
CONFIG_ARC_UART_BASE
CONFIG_ARMV7_SECURE_BASE
CONFIG_ARMV7_SECURE_MAX_SIZE
CONFIG_ARMV7_SECURE_RESERVE_SIZE
-CONFIG_ARMV8_PSCI
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
CONFIG_ARMV8_SWITCH_TO_EL1
CONFIG_ARM_ARCH_CP15_ERRATA
CONFIG_ATMEL_MCI_8BIT
CONFIG_ATMEL_NAND_HWECC
CONFIG_ATMEL_NAND_HW_PMECC
-CONFIG_ATMEL_SDHCI0
-CONFIG_ATMEL_SDHCI1
-CONFIG_ATMEL_SPI
CONFIG_ATMEL_SPI0
-CONFIG_ATMEL_USART
CONFIG_ATNGW100
CONFIG_ATNGW100MKII
CONFIG_ATSTK1000
CONFIG_BCH_CONST_PARAMS
CONFIG_BCH_CONST_T
CONFIG_BCM2835_GPIO
-CONFIG_BCM2835_SDHCI
CONFIG_BCM283X_MU_SERIAL
CONFIG_BCM_SF2_ETH
CONFIG_BCM_SF2_ETH_DEFAULT_PORT
CONFIG_BOARD_TAURUS
CONFIG_BOARD_TYPES
CONFIG_BOOGER
-CONFIG_BOOKE
CONFIG_BOOM
CONFIG_BOOTARGS
CONFIG_BOOTARGS_AXM
CONFIG_BOOT_DIR
CONFIG_BOOT_FROM_XMD
CONFIG_BOOT_MODE_BIT
-CONFIG_BOOT_NAND
-CONFIG_BOOT_ONENAND
CONFIG_BOOT_OS_NET
CONFIG_BOOT_PARAMS_ADDR
CONFIG_BOOT_PCI
CONFIG_CF_ATASEL_DIS
CONFIG_CF_ATASEL_ENA
CONFIG_CF_DSPI
-CONFIG_CF_QSPI
CONFIG_CF_SBF
CONFIG_CF_SPI
CONFIG_CF_V2
CONFIG_CMD_PCI_ENUM
CONFIG_CMD_PCMCIA
CONFIG_CMD_PORTIO
-CONFIG_CMD_PXE
CONFIG_CMD_READ
CONFIG_CMD_REGINFO
CONFIG_CMD_REISER
CONFIG_DDR_ECC_ENABLE
CONFIG_DDR_ECC_INIT_VIA_DMA
CONFIG_DDR_FIXED_SIZE
-CONFIG_DDR_FREQ
CONFIG_DDR_HCLK
CONFIG_DDR_HYB25D512160BF
CONFIG_DDR_II
CONFIG_DEEP_SLEEP
CONFIG_DEFAULT
CONFIG_DEFAULT_CONSOLE
-CONFIG_DEFAULT_FDT_FILE
CONFIG_DEFAULT_IMMR
CONFIG_DEFAULT_KERNEL_COMMAND_LINE
CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC
CONFIG_DFU_ALT_BOOT_SD
CONFIG_DFU_ALT_SYSTEM
CONFIG_DFU_ENV_SETTINGS
-CONFIG_DFU_MMC
CONFIG_DFU_MTD
-CONFIG_DFU_NAND
-CONFIG_DFU_RAM
-CONFIG_DFU_SF
CONFIG_DHCP_MIN_EXT_LEN
CONFIG_DIALOG_POWER
CONFIG_DIGSY_MTC
CONFIG_DISCOVER_PHY
CONFIG_DISPLAY_AER_xxxx
CONFIG_DISPLAY_BOARDINFO_LATE
-CONFIG_DISPLAY_CPUINFO
CONFIG_DLVISION
CONFIG_DLVISION_10G
CONFIG_DM9000_BASE
CONFIG_DYNAMIC_MMC_DEVNO
CONFIG_E1000_NO_NVM
CONFIG_E300
-CONFIG_E500
-CONFIG_E500MC
CONFIG_E5500
-CONFIG_E6500
CONFIG_EBCAW_VAL
CONFIG_EBC_PPC4xx_IBM_VER1
CONFIG_EBIU_AMBCTL0_VAL
CONFIG_EP9315
CONFIG_EP93XX
CONFIG_EP93XX_NO_FLASH_CFG
-CONFIG_EP93XX_SPI
-CONFIG_EP93XX_SPI_MMC
CONFIG_EPH_POWER_EN
CONFIG_EPOLL
CONFIG_ESBC_ADDR_64BIT
CONFIG_FASTBOOT_FLASH_FILLBUF_SIZE
CONFIG_FASTBOOT_FLASH_NAND_DEV
CONFIG_FASTBOOT_FLASH_NAND_TRIMFFS
-CONFIG_FASTBOOT_GPT_NAME
CONFIG_FAST_FLASH_BIT
CONFIG_FAT_WRITE
CONFIG_FB_ADDR
CONFIG_FDTFILE
CONFIG_FDT_ENV_ADDR
CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-CONFIG_FDT_FIXUP_PARTITIONS
CONFIG_FDT_FIXUP_PCI_IRQ
CONFIG_FEATURE_CLEAN_UP
CONFIG_FEATURE_COMMAND_EDITING
CONFIG_FEC_ENET
CONFIG_FEC_ENET_DEV
CONFIG_FEC_FIXED_SPEED
-CONFIG_FEC_MXC
CONFIG_FEC_MXC_25M_REF_CLK
CONFIG_FEC_MXC_PHYADDR
CONFIG_FEC_MXC_SWAP_PACKET
CONFIG_FO300
CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
CONFIG_FORMIKE
-CONFIG_FPGA_ALTERA
CONFIG_FPGA_COUNT
-CONFIG_FPGA_CYCLON2
CONFIG_FPGA_DELAY
CONFIG_FPGA_SOCFPGA
CONFIG_FPGA_SPARTAN2
CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
CONFIG_FSL_DDR_INTERACTIVE
CONFIG_FSL_DDR_SYNC_REFRESH
-CONFIG_FSL_DEBUG_SERVER
CONFIG_FSL_DEEP_SLEEP
CONFIG_FSL_DEVICE_DISABLE
CONFIG_FSL_DIU_CH7301
CONFIG_FSL_LAYERSCAPE
CONFIG_FSL_LBC
CONFIG_FSL_LINFLEXUART
-CONFIG_FSL_LS_PPA
CONFIG_FSL_MC9SDZ60
CONFIG_FSL_MC_ENET
CONFIG_FSL_MEMAC
CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
CONFIG_FSL_QIXIS_V2
CONFIG_FSL_SATA
-CONFIG_FSL_SATA_ERRATUM_A001
CONFIG_FSL_SATA_V2
CONFIG_FSL_SDHC_V2_3
CONFIG_FSL_SDRAM_TYPE
CONFIG_IMX_HDMI
CONFIG_IMX_NAND
CONFIG_IMX_OTP
-CONFIG_IMX_THERMAL
CONFIG_IMX_VIDEO_SKIP
CONFIG_IMX_WATCHDOG
CONFIG_INETSPACE_V2
CONFIG_JTAG_CONSOLE
CONFIG_JTAG_CONSOLE_TIMEOUT
CONFIG_JUPITER
-CONFIG_K2E_EVM
-CONFIG_K2G_EVM
-CONFIG_K2HK_EVM
-CONFIG_K2L_EVM
CONFIG_KALLSYMS
CONFIG_KASAN
CONFIG_KATMAI
CONFIG_KONA
CONFIG_KONA_GPIO
CONFIG_KONA_RESET_S
-CONFIG_KONA_SDHCI
CONFIG_KPROBES
CONFIG_KS8851_MLL
CONFIG_KS8851_MLL_BASEADDR
CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
CONFIG_LQ038J7DH53
-CONFIG_LS1012A
CONFIG_LS102XA
CONFIG_LS102XA_STREAM_ID
CONFIG_LS1043A
CONFIG_MACB2_PHY
CONFIG_MACB3_PHY
CONFIG_MACB_SEARCH_PHY
-CONFIG_MACH_A0
-CONFIG_MACH_A2F
-CONFIG_MACH_ABACUS
-CONFIG_MACH_ABB_GMA_1_1
-CONFIG_MACH_ABILENE
-CONFIG_MACH_ABLE
-CONFIG_MACH_ACER_A5
-CONFIG_MACH_ACER_A8
-CONFIG_MACH_ACER_GAUGUIN
-CONFIG_MACH_ACER_MAYA
-CONFIG_MACH_ACMENETUSFOXG20
-CONFIG_MACH_ACMEROVER1
-CONFIG_MACH_ACRO37XBRD
-CONFIG_MACH_ACS5K
-CONFIG_MACH_ACSX106
-CONFIG_MACH_ADSSPHERE
-CONFIG_MACH_AEBL
-CONFIG_MACH_AF4000
-CONFIG_MACH_AFEB9260
-CONFIG_MACH_AG11005
-CONFIG_MACH_AG5EVM
-CONFIG_MACH_AKITA
-CONFIG_MACH_AMK_A4
-CONFIG_MACH_AML_M5900
-CONFIG_MACH_AMS_DELTA
-CONFIG_MACH_ANCHOVY
-CONFIG_MACH_ANTARES
-CONFIG_MACH_ANTERO
-CONFIG_MACH_ANUBIS
-CONFIG_MACH_ANW6410
-CONFIG_MACH_AP4EVB
-CONFIG_MACH_APALIS_T30
-CONFIG_MACH_APP3K_ROBIN
-CONFIG_MACH_AQUARIUS
-CONFIG_MACH_AQUILA
-CONFIG_MACH_ARCOM_VULCAN
-CONFIG_MACH_ARCOM_ZEUS
-CONFIG_MACH_ARK9431
-CONFIG_MACH_ARMADA_XP_DB
-CONFIG_MACH_ARMADILLO460
-CONFIG_MACH_ARMADILLO5X0
-CONFIG_MACH_ARMADILLO800EVA
-CONFIG_MACH_ARMCORE
-CONFIG_MACH_ARMLEX4210
-CONFIG_MACH_ARMLGUEST
-CONFIG_MACH_AROWANA
-CONFIG_MACH_ARTHUR
-CONFIG_MACH_ARUBA
-CONFIG_MACH_AS1167
-CONFIG_MACH_ASL_PHOENIX
-CONFIG_MACH_ASPEN
CONFIG_MACH_ASPENITE
-CONFIG_MACH_AST2200
-CONFIG_MACH_AT2440EVB
-CONFIG_MACH_AT572D940HFEB
-CONFIG_MACH_AT91CAP7STK
-CONFIG_MACH_AT91CAP7XDK
-CONFIG_MACH_AT91CAP9ADK
-CONFIG_MACH_AT91EB01
-CONFIG_MACH_AT91RM9200EK
-CONFIG_MACH_AT91SAM9260EK
-CONFIG_MACH_AT91SAM9261EK
-CONFIG_MACH_AT91SAM9263DESK16L
-CONFIG_MACH_AT91SAM9263EK
-CONFIG_MACH_AT91SAM9263OTLITE
-CONFIG_MACH_AT91SAM9G10EK
-CONFIG_MACH_AT91SAM9G20EK
-CONFIG_MACH_AT91SAM9G20EK_2MMC
-CONFIG_MACH_AT91SAM9G45EKES
-CONFIG_MACH_AT91SAM9M10G45EK
-CONFIG_MACH_AT91SAM9RLEK
-CONFIG_MACH_AT91SAM9X5EK
-CONFIG_MACH_ATDGP318
-CONFIG_MACH_ATEB9200
-CONFIG_MACH_ATHENE
-CONFIG_MACH_ATLAS5_C1
-CONFIG_MACH_AUTOBOT
-CONFIG_MACH_AVENGERS_LITE
-CONFIG_MACH_AVILA
-CONFIG_MACH_AWM2
-CONFIG_MACH_AX502
-CONFIG_MACH_AX8008
-CONFIG_MACH_B5500
-CONFIG_MACH_BASI
-CONFIG_MACH_BCM2708
-CONFIG_MACH_BCM589X
-CONFIG_MACH_BCMHANA_SV
-CONFIG_MACH_BCMHANA_TABLET
-CONFIG_MACH_BCMRING
-CONFIG_MACH_BEECT
-CONFIG_MACH_BIGDISK
-CONFIG_MACH_BIO3K
-CONFIG_MACH_BIPNET
-CONFIG_MACH_BLISS
-CONFIG_MACH_BLISSC
-CONFIG_MACH_BLUECHEESE
-CONFIG_MACH_BLUEPOINT
-CONFIG_MACH_BLUESHARK
-CONFIG_MACH_BOCKW
-CONFIG_MACH_BONAIRE
-CONFIG_MACH_BORABORA
-CONFIG_MACH_BORZOI
-CONFIG_MACH_BROWNSTONE
-CONFIG_MACH_BSTBRD
-CONFIG_MACH_BTMAVB101
-CONFIG_MACH_BTMAWB101
-CONFIG_MACH_BUBBA3
-CONFIG_MACH_BUG
-CONFIG_MACH_BUG20
-CONFIG_MACH_BURY_BL7582
-CONFIG_MACH_BURY_BPS5270
-CONFIG_MACH_BV07
-CONFIG_MACH_C2MMI
-CONFIG_MACH_CALLISTO
-CONFIG_MACH_CAM60
-CONFIG_MACH_CAPC7117
-CONFIG_MACH_CARDHU
-CONFIG_MACH_CARMEVA
-CONFIG_MACH_CAYENNE
-CONFIG_MACH_CC9P9360DEV
-CONFIG_MACH_CC9P9360JS
-CONFIG_MACH_CCMX53
-CONFIG_MACH_CCMX53JS
-CONFIG_MACH_CCWMX51MUT
-CONFIG_MACH_CCWMX53
-CONFIG_MACH_CCWMX53JS
-CONFIG_MACH_CENTRO
-CONFIG_MACH_CETUS9263
-CONFIG_MACH_CHACHA
-CONFIG_MACH_CHALTEN_XA1
-CONFIG_MACH_CHARON
-CONFIG_MACH_CLOD
-CONFIG_MACH_CM4745
-CONFIG_MACH_CM_A510
-CONFIG_MACH_CM_T35
-CONFIG_MACH_CM_T3517
-CONFIG_MACH_CM_T3730
-CONFIG_MACH_CM_X300
-CONFIG_MACH_CNS2133EVB
-CONFIG_MACH_CNS21XX
-CONFIG_MACH_CNS3420VB
-CONFIG_MACH_COBRAL138
-CONFIG_MACH_COCONUT
-CONFIG_MACH_COLIBRI
-CONFIG_MACH_COLIBRI300
-CONFIG_MACH_COLIBRI320
-CONFIG_MACH_COLIBRI_T20
-CONFIG_MACH_COLIBRI_T30
-CONFIG_MACH_CONTROLTEK9G20
-CONFIG_MACH_CORETEC_VCX7400
-CONFIG_MACH_CORGI
-CONFIG_MACH_CPUAT9G20
-CONFIG_MACH_CPX2
-CONFIG_MACH_CRANEBOARD
-CONFIG_MACH_CRUX
-CONFIG_MACH_CSB337
-CONFIG_MACH_CSB637
-CONFIG_MACH_CSB726
-CONFIG_MACH_CSC
-CONFIG_MACH_CTBU_GEN2
-CONFIG_MACH_CTERA_PLUG_C2
-CONFIG_MACH_CURACAO
-CONFIG_MACH_CV2201
-CONFIG_MACH_CV2202
-CONFIG_MACH_CV2203
-CONFIG_MACH_CWAM1808
-CONFIG_MACH_CWDM365
-CONFIG_MACH_CWME9210
-CONFIG_MACH_CWME9210JS
-CONFIG_MACH_CWMX233
-CONFIG_MACH_D2NET
-CONFIG_MACH_D2NET_V2
-CONFIG_MACH_D2PLUG
-CONFIG_MACH_DA850_K5
-CONFIG_MACH_DAINTREE_CWAC
-CONFIG_MACH_DATAWAY
CONFIG_MACH_DAVINCI_CALIMAIN
-CONFIG_MACH_DAVINCI_DA830_EVM
CONFIG_MACH_DAVINCI_DA850_EVM
-CONFIG_MACH_DAVINCI_DM355_EVM
-CONFIG_MACH_DAVINCI_DM355_MMM
-CONFIG_MACH_DAVINCI_DM365_BV
-CONFIG_MACH_DAVINCI_DM365_DVR
-CONFIG_MACH_DAVINCI_DM365_EVM
-CONFIG_MACH_DAVINCI_DM6467TEVM
-CONFIG_MACH_DAVINCI_DM6467_EVM
-CONFIG_MACH_DAVINCI_EVM
-CONFIG_MACH_DAVINCI_PICTO
-CONFIG_MACH_DAWAD7
-CONFIG_MACH_DB78X00_BP
-CONFIG_MACH_DB88F5281
-CONFIG_MACH_DB88F6281_BP
-CONFIG_MACH_DDNAS
-CONFIG_MACH_DDPLUG
-CONFIG_MACH_DDS
-CONFIG_MACH_DEEP_R_EK_1
-CONFIG_MACH_DEVIXP
-CONFIG_MACH_DEVKIT8000
-CONFIG_MACH_DGM3240
-CONFIG_MACH_DIMMSAM9G20
-CONFIG_MACH_DIMM_IMX28
-CONFIG_MACH_DIMM_MX257
-CONFIG_MACH_DINGO
-CONFIG_MACH_DIR665
-CONFIG_MACH_DM355_LEOPARD
-CONFIG_MACH_DM365_CV100
-CONFIG_MACH_DM368_LEOPARD
-CONFIG_MACH_DM3730_SOM_LV
-CONFIG_MACH_DM3730_TORPEDO
-CONFIG_MACH_DM6441_ESP
-CONFIG_MACH_DM6446_ADBOX
-CONFIG_MACH_DMA6410
-CONFIG_MACH_DMA_THUNDERBUG
-CONFIG_MACH_DMW96
-CONFIG_MACH_DNS323
CONFIG_MACH_DOCKSTAR
-CONFIG_MACH_DOORBOY
-CONFIG_MACH_DOUBLESHOT
-CONFIG_MACH_DOVE_AVNG_V3
-CONFIG_MACH_DOVE_DB
-CONFIG_MACH_DP6XX
-CONFIG_MACH_DRAGONET
-CONFIG_MACH_DSM320
-CONFIG_MACH_DSMG600
-CONFIG_MACH_DURIAN
-CONFIG_MACH_DYNASTY
-CONFIG_MACH_E10
-CONFIG_MACH_E330
-CONFIG_MACH_E350
-CONFIG_MACH_E400
-CONFIG_MACH_E740
-CONFIG_MACH_E750
-CONFIG_MACH_E800
-CONFIG_MACH_EA20
-CONFIG_MACH_EA2478DEVKIT
-CONFIG_MACH_EAG_CI4000
-CONFIG_MACH_EASYCRRH
-CONFIG_MACH_EC4350SDB
-CONFIG_MACH_EC4350TBM
-CONFIG_MACH_ECBAT91
-CONFIG_MACH_ECO920
-CONFIG_MACH_ECUV5
-CONFIG_MACH_EDB9301
-CONFIG_MACH_EDB9302
-CONFIG_MACH_EDB9302A
-CONFIG_MACH_EDB9307
-CONFIG_MACH_EDB9307A
-CONFIG_MACH_EDB9312
-CONFIG_MACH_EDB9315
-CONFIG_MACH_EDB9315A
-CONFIG_MACH_EDISON
CONFIG_MACH_EDMINIV2
-CONFIG_MACH_EDMINI_V2
-CONFIG_MACH_EELX2
-CONFIG_MACH_EIGEN_TTR
-CONFIG_MACH_ELEPHANT
-CONFIG_MACH_ELKE
-CONFIG_MACH_ELOG
-CONFIG_MACH_EM1SY
-CONFIG_MACH_EM7210
-CONFIG_MACH_EMERALD
-CONFIG_MACH_EM_X270
-CONFIG_MACH_ENCORE
-CONFIG_MACH_ENDIAN_MINI
-CONFIG_MACH_EP80219
-CONFIG_MACH_EPC10
-CONFIG_MACH_EPIPHAN
-CONFIG_MACH_ES2440
-CONFIG_MACH_ESATA_SHEEVAPLUG
-CONFIG_MACH_ESL_MOBILIS_A
-CONFIG_MACH_ESL_MOBILIS_B
-CONFIG_MACH_ESL_WAVE_A
-CONFIG_MACH_ESL_WAVE_B
-CONFIG_MACH_ESPRESSO
-CONFIG_MACH_ETHERPRO_ISP
-CONFIG_MACH_ETNA
-CONFIG_MACH_EUKREA_CPUIMX25SD
-CONFIG_MACH_EUKREA_CPUIMX35SD
-CONFIG_MACH_EUKREA_CPUIMX51
-CONFIG_MACH_EUKREA_CPUIMX51SD
-CONFIG_MACH_EVA2000
-CONFIG_MACH_EVSY
-CONFIG_MACH_EXEDA
-CONFIG_MACH_EXPRESS
-CONFIG_MACH_EXPRESSCT
-CONFIG_MACH_EXPRESSH
-CONFIG_MACH_EXPRESS_KT
-CONFIG_MACH_EZX_A1200
-CONFIG_MACH_EZX_A780
-CONFIG_MACH_EZX_A910
-CONFIG_MACH_EZX_E2
-CONFIG_MACH_EZX_E6
-CONFIG_MACH_EZX_E680
-CONFIG_MACH_FA9X27
-CONFIG_MACH_FFCORE
-CONFIG_MACH_FLEXIBITY
-CONFIG_MACH_FLINT
-CONFIG_MACH_FLYER
-CONFIG_MACH_FRISMS
-CONFIG_MACH_FRRHWCDMA60W
-CONFIG_MACH_FSG
-CONFIG_MACH_FSM9XXX_FFA
-CONFIG_MACH_FSM9XXX_SURF
-CONFIG_MACH_FS_S5PC100
-CONFIG_MACH_FUJI
-CONFIG_MACH_FWBD_0404
-CONFIG_MACH_G3EVM
-CONFIG_MACH_G4EVM
-CONFIG_MACH_GATEWAY7001
-CONFIG_MACH_GENEVA_B5
-CONFIG_MACH_GESBC9312
-CONFIG_MACH_GFS_SPM
-CONFIG_MACH_GINGER
-CONFIG_MACH_GIRA_KNXIP_ROUTER
-CONFIG_MACH_GLANTANK
-CONFIG_MACH_GNET_SGCE
-CONFIG_MACH_GNET_SGME
-CONFIG_MACH_GNET_SLC
CONFIG_MACH_GOFLEXHOME
-CONFIG_MACH_GOFLEXNET
-CONFIG_MACH_GOLDENGATE
CONFIG_MACH_GONI
-CONFIG_MACH_GORAMO_MLR
-CONFIG_MACH_GPSDISPLAY
-CONFIG_MACH_GREECO
-CONFIG_MACH_GSIA18S
-CONFIG_MACH_GSL_DIAMOND
-CONFIG_MACH_GSNCOMM
-CONFIG_MACH_GTA04
-CONFIG_MACH_GTIB
-CONFIG_MACH_GTL_IT5100
-CONFIG_MACH_GTWX5715
-CONFIG_MACH_GT_I5700
-CONFIG_MACH_GUPPY
-CONFIG_MACH_GURNARD
CONFIG_MACH_GURUPLUG
-CONFIG_MACH_GW2361
-CONFIG_MACH_H1600
-CONFIG_MACH_H4700
-CONFIG_MACH_HABA_KNX_EXPLORER
-CONFIG_MACH_HALIBUT
-CONFIG_MACH_HAMMERHEAD
-CONFIG_MACH_HARMONY
-CONFIG_MACH_HARVEST_DESOTO
-CONFIG_MACH_HAWKS
-CONFIG_MACH_HDGU
-CONFIG_MACH_HDMINI
-CONFIG_MACH_HDNVP
-CONFIG_MACH_HELIOS_V1
-CONFIG_MACH_HELIOS_V2
-CONFIG_MACH_HERALD
-CONFIG_MACH_HERRING
-CONFIG_MACH_HIMALAYA
-CONFIG_MACH_HJSDU
-CONFIG_MACH_HKDKC100
-CONFIG_MACH_HMT
-CONFIG_MACH_HOLIDAY
-CONFIG_MACH_HREFV60
-CONFIG_MACH_HSGX6D
-CONFIG_MACH_HTCMEGA
-CONFIG_MACH_HTCTORNADO
-CONFIG_MACH_HTC_HD_MINI
-CONFIG_MACH_HTC_SPV_M700
-CONFIG_MACH_HUASHAN
-CONFIG_MACH_HUSKY
-CONFIG_MACH_HWGW6410
-CONFIG_MACH_IAM28
-CONFIG_MACH_ICON
-CONFIG_MACH_ICONG
-CONFIG_MACH_ICONNECT
-CONFIG_MACH_ICONTROL
-CONFIG_MACH_ICON_G
-CONFIG_MACH_ICS_IF_VOIP
-CONFIG_MACH_IDEA6410
-CONFIG_MACH_IGEP0020
-CONFIG_MACH_IGEP0030
-CONFIG_MACH_IGEP0032
-CONFIG_MACH_IJ3K_2440
-CONFIG_MACH_IMATE8502
-CONFIG_MACH_IMX27IPCAM
-CONFIG_MACH_IMX27LITE
-CONFIG_MACH_IMX27_VISSTRIM_M10
-CONFIG_MACH_INCOME
-CONFIG_MACH_INETSPACE_V2
-CONFIG_MACH_INHAND_APEIRON
-CONFIG_MACH_INHAND_FURY
-CONFIG_MACH_INHAND_SIREN
-CONFIG_MACH_INTELMOTE2
-CONFIG_MACH_IOMEGA_IX2_200
-CONFIG_MACH_IQ80332
-CONFIG_MACH_IQ81340MC
-CONFIG_MACH_IQ81340SC
-CONFIG_MACH_ISC3
-CONFIG_MACH_IXDP2351
-CONFIG_MACH_IXDP28X5
-CONFIG_MACH_IXDP465
-CONFIG_MACH_IXDPG425
-CONFIG_MACH_JANUS
-CONFIG_MACH_JIGEN
-CONFIG_MACH_JIVE
-CONFIG_MACH_JOCPU550
-CONFIG_MACH_KAEN
-CONFIG_MACH_KAFA
-CONFIG_MACH_KB9200
-CONFIG_MACH_KEV7A400
-CONFIG_MACH_KINGDOM
-CONFIG_MACH_KIXRP435
-CONFIG_MACH_KMM2M01
-CONFIG_MACH_KMP_AM17_01
CONFIG_MACH_KM_KIRKWOOD
-CONFIG_MACH_KOI
-CONFIG_MACH_KRONOS
-CONFIG_MACH_KT_SBC_SAM9_1
-CONFIG_MACH_KUROBOX_PRO
-CONFIG_MACH_KX33XX
-CONFIG_MACH_KZM9D
-CONFIG_MACH_KZM9G
-CONFIG_MACH_KZM_ARM11_01
-CONFIG_MACH_LANREADYFN511
-CONFIG_MACH_LAUSANNE
-CONFIG_MACH_LB88RC8480
-CONFIG_MACH_LEAD
-CONFIG_MACH_LEGACY
-CONFIG_MACH_LEMON
-CONFIG_MACH_LIBRA
-CONFIG_MACH_LIGHTNING
-CONFIG_MACH_LILLY1131
-CONFIG_MACH_LINKSTATION_CHLV2
-CONFIG_MACH_LINKSTATION_LSCHL
-CONFIG_MACH_LINKSTATION_LS_HGL
-CONFIG_MACH_LINKSTATION_MINI
-CONFIG_MACH_LINKSTATION_PRO
-CONFIG_MACH_LITTLETON
-CONFIG_MACH_LOFT
-CONFIG_MACH_LOGICPD_PXA270
-CONFIG_MACH_LPC24XX
-CONFIG_MACH_LPD7A400
-CONFIG_MACH_LPD7A404
-CONFIG_MACH_LQ2
-CONFIG_MACH_LS9G20
-CONFIG_MACH_LSWXL
-CONFIG_MACH_M502
-CONFIG_MACH_MACH_SDH001
-CONFIG_MACH_MACKEREL
-CONFIG_MACH_MAGICIAN
-CONFIG_MACH_MAGX_ZN5
-CONFIG_MACH_MAHIMAHI
-CONFIG_MACH_MAINSTONE
-CONFIG_MACH_MANUAE
-CONFIG_MACH_MAPLE1
-CONFIG_MACH_MARVEL
-CONFIG_MACH_MARVELC
-CONFIG_MACH_MARVELCT
-CONFIG_MACH_MARVELL_JASPER
-CONFIG_MACH_MATRIX505
-CONFIG_MACH_MATRIX518
-CONFIG_MACH_MAXIMASP
-CONFIG_MACH_MB3
-CONFIG_MACH_MECHA
-CONFIG_MACH_MENO_QNG
-CONFIG_MACH_MESON
-CONFIG_MACH_MESON_6236M
-CONFIG_MACH_MESON_8626M
-CONFIG_MACH_MESSINA
-CONFIG_MACH_MIC256
-CONFIG_MACH_MICCPT
-CONFIG_MACH_MICRO9
-CONFIG_MACH_MICRO9L
-CONFIG_MACH_MICRO9M
-CONFIG_MACH_MICRO9S
-CONFIG_MACH_MIF10P
-CONFIG_MACH_MIMAS
-CONFIG_MACH_MINI210
-CONFIG_MACH_MINI2440
-CONFIG_MACH_MINI6410
-CONFIG_MACH_MINI8168
-CONFIG_MACH_MIOA502
-CONFIG_MACH_MIOA701
-CONFIG_MACH_MIONE
-CONFIG_MACH_MIOS_V1
-CONFIG_MACH_MITYOMAPL138
-CONFIG_MACH_MMM
-CONFIG_MACH_MONCH
-CONFIG_MACH_MONE
-CONFIG_MACH_MOON
-CONFIG_MACH_MORA
-CONFIG_MACH_MR301A
-CONFIG_MACH_MSM7X25_FFA
-CONFIG_MACH_MSM7X25_SURF
-CONFIG_MACH_MSM7X27A_FFA
-CONFIG_MACH_MSM7X27A_RUMI3
-CONFIG_MACH_MSM7X27A_SURF
-CONFIG_MACH_MSM7X27_FFA
-CONFIG_MACH_MSM7X27_SURF
-CONFIG_MACH_MSM7X30_FFA
-CONFIG_MACH_MSM7X30_FLUID
-CONFIG_MACH_MSM7X30_SURF
-CONFIG_MACH_MSM8960_APQ
-CONFIG_MACH_MSM8960_CDP
-CONFIG_MACH_MSM8960_FLUID
-CONFIG_MACH_MSM8960_MDP
-CONFIG_MACH_MSM8960_RUMI3
-CONFIG_MACH_MSM8960_SIM
-CONFIG_MACH_MSM8X55_SVLTE_FFA
-CONFIG_MACH_MSM8X55_SVLTE_SURF
-CONFIG_MACH_MSM8X60_FFA
-CONFIG_MACH_MSM8X60_FLUID
-CONFIG_MACH_MSM8X60_QRDC
-CONFIG_MACH_MSM8X60_QT
-CONFIG_MACH_MSM8X60_RUMI3
-CONFIG_MACH_MSM8X60_SIM
-CONFIG_MACH_MSM8X60_SURF
-CONFIG_MACH_MSS2
-CONFIG_MACH_MULTHSU
-CONFIG_MACH_MV2120
-CONFIG_MACH_MV88F6281GTW_GE
-CONFIG_MACH_MVBLX
-CONFIG_MACH_MX21ADS
-CONFIG_MACH_MX23EVK
-CONFIG_MACH_MX257SOL
-CONFIG_MACH_MX257SX
-CONFIG_MACH_MX25_3DS
-CONFIG_MACH_MX25_E2S_UC
-CONFIG_MACH_MX27ADS
-CONFIG_MACH_MX27SU2
-CONFIG_MACH_MX27_3DS
-CONFIG_MACH_MX27_WMULTRA
-CONFIG_MACH_MX28EVK
-CONFIG_MACH_MX31ADS
-CONFIG_MACH_MX31LITE
-CONFIG_MACH_MX31MOBOARD
-CONFIG_MACH_MX31_3DS
-CONFIG_MACH_MX35_3DS
-CONFIG_MACH_MX50_ARM2
-CONFIG_MACH_MX50_RDP
-CONFIG_MACH_MX51EREBUS
-CONFIG_MACH_MX51_3DS
-CONFIG_MACH_MX51_ASTER7
-CONFIG_MACH_MX51_BABBAGE
-CONFIG_MACH_MX51_BRAVO
-CONFIG_MACH_MX51_EFIKAMX
-CONFIG_MACH_MX51_EFIKASB
-CONFIG_MACH_MX51_GGC
-CONFIG_MACH_MX51_MORAY
-CONFIG_MACH_MX51_TULIP
-CONFIG_MACH_MX53_ARD
-CONFIG_MACH_MX53_EVK
-CONFIG_MACH_MX53_LOCO
-CONFIG_MACH_MX53_SMD
-CONFIG_MACH_MX61_ARD
-CONFIG_MACH_MXC25_TOPAZ
-CONFIG_MACH_MXLADS
-CONFIG_MACH_MXT_TD60
-CONFIG_MACH_MXT_TD61
-CONFIG_MACH_N2100
-CONFIG_MACH_N30
-CONFIG_MACH_N35
-CONFIG_MACH_NAJAY_A9263
-CONFIG_MACH_NANOS
-CONFIG_MACH_NANOZOOM
-CONFIG_MACH_NAS100D
-CONFIG_MACH_NAS4220B
-CONFIG_MACH_NAS6210
-CONFIG_MACH_NAVEFIHID
-CONFIG_MACH_NAXY1200
-CONFIG_MACH_NAXY400
-CONFIG_MACH_NB31
-CONFIG_MACH_NCP
-CONFIG_MACH_NDA_EVM
-CONFIG_MACH_NEC_MP900
-CONFIG_MACH_NEO1973_GTA02
-CONFIG_MACH_NEOCORE926
-CONFIG_MACH_NERY_1000
-CONFIG_MACH_NET2BIG
-CONFIG_MACH_NET2BIG_NAND_V2
-CONFIG_MACH_NET2BIG_V2
-CONFIG_MACH_NET5BIG_NAND_V2
-CONFIG_MACH_NET5BIG_V2
-CONFIG_MACH_NETSPACE_LITE_V2
-CONFIG_MACH_NETSPACE_MAX_V2
-CONFIG_MACH_NETSPACE_V2
-CONFIG_MACH_NETVIZ
-CONFIG_MACH_NETWALKER
-CONFIG_MACH_NEUROS_OSD2
-CONFIG_MACH_NEXCODER_2440
-CONFIG_MACH_NITROGEN_IMX51
-CONFIG_MACH_NITROGEN_IMX53
-CONFIG_MACH_NITROGEN_VM_IMX51
-CONFIG_MACH_NMH
-CONFIG_MACH_NOKIA770
-CONFIG_MACH_NOKIA_N800
-CONFIG_MACH_NOKIA_N810
-CONFIG_MACH_NOKIA_N810_WIMAX
-CONFIG_MACH_NOKIA_RM680
-CONFIG_MACH_NOKIA_RX51
-CONFIG_MACH_NOMADIK
-CONFIG_MACH_NOTLE
-CONFIG_MACH_NS2416
-CONFIG_MACH_NS2816TB
-CONFIG_MACH_NS2816_NTNB
-CONFIG_MACH_NS2816_NTPAD
-CONFIG_MACH_NSB3AST
-CONFIG_MACH_NSK330
-CONFIG_MACH_NSLU2
-CONFIG_MACH_NSSLSBOARD
-CONFIG_MACH_NS_K330
-CONFIG_MACH_NUC700EVB
-CONFIG_MACH_NUC710EVB
-CONFIG_MACH_NUC740EVB
-CONFIG_MACH_NUC745EVB
-CONFIG_MACH_NUC932EVB
-CONFIG_MACH_NUC950TS
-CONFIG_MACH_NURI
-CONFIG_MACH_NV1000
-CONFIG_MACH_NXDB500
-CONFIG_MACH_NXDKN
-CONFIG_MACH_NXEB500HMI
-CONFIG_MACH_OCE_NIGMA
-CONFIG_MACH_OMAP2EVM
-CONFIG_MACH_OMAP3505NOVA8
-CONFIG_MACH_OMAP3517EVM
-CONFIG_MACH_OMAP3530_LV_SOM
-CONFIG_MACH_OMAP3621_EDP1
-CONFIG_MACH_OMAP3EVM
-CONFIG_MACH_OMAP3SMARTDISPLAY
-CONFIG_MACH_OMAP3_BAIA
-CONFIG_MACH_OMAP3_BC10
-CONFIG_MACH_OMAP3_BEAGLE
-CONFIG_MACH_OMAP3_BRAILLO
-CONFIG_MACH_OMAP3_IBIZA
-CONFIG_MACH_OMAP3_PANDORA
-CONFIG_MACH_OMAP3_RFS200
-CONFIG_MACH_OMAP3_TDM3730
-CONFIG_MACH_OMAP3_TORPEDO
-CONFIG_MACH_OMAP3_WALDO1
-CONFIG_MACH_OMAP4_PANDA
-CONFIG_MACH_OMAP5_SEVM
-CONFIG_MACH_OMAPL138_CASE_A3
-CONFIG_MACH_OMAPL138_EUROPALC
-CONFIG_MACH_OMAPL138_HAWKBOARD
CONFIG_MACH_OMAPL138_LCDK
-CONFIG_MACH_OMAP_2430SDP
-CONFIG_MACH_OMAP_3430SDP
-CONFIG_MACH_OMAP_3630SDP
-CONFIG_MACH_OMAP_4430SDP
-CONFIG_MACH_OMAP_APOLLON
-CONFIG_MACH_OMAP_BENDER
-CONFIG_MACH_OMAP_FSAMPLE
-CONFIG_MACH_OMAP_GENERIC
-CONFIG_MACH_OMAP_H2
-CONFIG_MACH_OMAP_H3
-CONFIG_MACH_OMAP_H4
-CONFIG_MACH_OMAP_INNOVATOR
-CONFIG_MACH_OMAP_LDP
-CONFIG_MACH_OMAP_MCOP
-CONFIG_MACH_OMAP_OSK
-CONFIG_MACH_OMAP_PALMTE
-CONFIG_MACH_OMAP_PALMTT
-CONFIG_MACH_OMAP_PALMZ71
-CONFIG_MACH_OMAP_PERSEUS2
-CONFIG_MACH_OMAP_ZOOM2
-CONFIG_MACH_OMAP_ZOOM3
-CONFIG_MACH_OMN_AT91SAM9G20
-CONFIG_MACH_ONEARM
CONFIG_MACH_OPENRD_BASE
-CONFIG_MACH_OPENRD_CLIENT
-CONFIG_MACH_OPENRD_ULTIMATE
-CONFIG_MACH_ORATISAES
-CONFIG_MACH_ORATISLINK
-CONFIG_MACH_ORIGEN
-CONFIG_MACH_OSIRIS
-CONFIG_MACH_OSLO_AMUNDSEN
-CONFIG_MACH_OTOM
-CONFIG_MACH_OVERO
-CONFIG_MACH_OVERO_CTU_INERTIAL
-CONFIG_MACH_P87_SMARTSIM
-CONFIG_MACH_PALMLD
-CONFIG_MACH_PALMT5
-CONFIG_MACH_PALMTC
-CONFIG_MACH_PALMTE2
-CONFIG_MACH_PALMTX
-CONFIG_MACH_PALMZ72
-CONFIG_MACH_PAZ00
-CONFIG_MACH_PC7302
-CONFIG_MACH_PC7308
-CONFIG_MACH_PC9260_V2
-CONFIG_MACH_PCA100
-CONFIG_MACH_PCA102
-CONFIG_MACH_PCATS_OVERLAY
-CONFIG_MACH_PCM027
-CONFIG_MACH_PCM037
-CONFIG_MACH_PCM038
-CONFIG_MACH_PCM043
-CONFIG_MACH_PCM048
-CONFIG_MACH_PCM049
-CONFIG_MACH_PCONTROL_G20
-CONFIG_MACH_PEC_HC2
-CONFIG_MACH_PEC_TC
-CONFIG_MACH_PEMP_OMAP3_APOLLO
-CONFIG_MACH_PGS_SITARA
-CONFIG_MACH_PHILHWANI
-CONFIG_MACH_PHY3250
-CONFIG_MACH_PICASSO
-CONFIG_MACH_PICO
-CONFIG_MACH_PICOCOM3
-CONFIG_MACH_PICOCOM4
-CONFIG_MACH_PICOTUX2XX
-CONFIG_MACH_PIVICC
-CONFIG_MACH_PNX4008
-CONFIG_MACH_POLYSAT1
-CONFIG_MACH_POODLE
-CONFIG_MACH_PORTUXG20
-CONFIG_MACH_POV15HD
-CONFIG_MACH_PREMIERWAVE_EN
-CONFIG_MACH_PRIMA2_EVB
-CONFIG_MACH_PTX7510
-CONFIG_MACH_PTX7545
-CONFIG_MACH_PUNICA
-CONFIG_MACH_PUPITRE
-CONFIG_MACH_PVM2030
-CONFIG_MACH_PWB3090
-CONFIG_MACH_PXWNAS_500_1000
-CONFIG_MACH_PYRAMID
-CONFIG_MACH_QBC9263
-CONFIG_MACH_QIL_A9260
-CONFIG_MACH_QONG
-CONFIG_MACH_QSD8X50A_ST1_5
-CONFIG_MACH_QSD8X50_SURF
-CONFIG_MACH_QSD8X72_FFA
-CONFIG_MACH_QSD8X72_SURF
-CONFIG_MACH_QT2410
-CONFIG_MACH_QUAD_SALSA
-CONFIG_MACH_QUICKSTEP
-CONFIG_MACH_R1801E
-CONFIG_MACH_RASCAL
-CONFIG_MACH_RAUMFELD_CONNECTOR
-CONFIG_MACH_RAUMFELD_RC
-CONFIG_MACH_RAUMFELD_SPEAKER
-CONFIG_MACH_RD78X00_MASA
-CONFIG_MACH_RD88F5181L_FXO
-CONFIG_MACH_RD88F5181L_GE
-CONFIG_MACH_RD88F5182
-CONFIG_MACH_RD88F6183AP_GE
-CONFIG_MACH_RD88F6192_NAS
-CONFIG_MACH_RD88F6281
-CONFIG_MACH_RDSTOR
-CONFIG_MACH_RE2REV20
-CONFIG_MACH_RE2REV21
-CONFIG_MACH_REAL6410
-CONFIG_MACH_REALVIEW_EB
-CONFIG_MACH_REALVIEW_PB1176
-CONFIG_MACH_REALVIEW_PB11MP
-CONFIG_MACH_REALVIEW_PBA8
-CONFIG_MACH_REALVIEW_PBX
-CONFIG_MACH_REMUS
-CONFIG_MACH_REXMAS
-CONFIG_MACH_RFL109145_SSRV
-CONFIG_MACH_RHINO
-CONFIG_MACH_RIB
-CONFIG_MACH_RIDER
-CONFIG_MACH_RIOT_BEI2
-CONFIG_MACH_RIOT_X37
-CONFIG_MACH_ROADRUNNER
-CONFIG_MACH_ROCKHOPPER
-CONFIG_MACH_ROVERPCS8
-CONFIG_MACH_ROVERX7
-CONFIG_MACH_ROVER_G8
-CONFIG_MACH_RPC353
-CONFIG_MACH_RUBY
-CONFIG_MACH_RUBYS
-CONFIG_MACH_RUMP
-CONFIG_MACH_RUT100
-CONFIG_MACH_RV082
-CONFIG_MACH_RX1950
-CONFIG_MACH_RX3715
-CONFIG_MACH_S3C2413
-CONFIG_MACH_S5500
-CONFIG_MACH_S5PC110_CRESPO
-CONFIG_MACH_SAAR
-CONFIG_MACH_SAARB
-CONFIG_MACH_SAARB_MG1
-CONFIG_MACH_SAGA
-CONFIG_MACH_SALUDA
-CONFIG_MACH_SAM9REPEATER
-CONFIG_MACH_SAM9_L9260
-CONFIG_MACH_SANTIAGO
-CONFIG_MACH_SAPPHIRE
-CONFIG_MACH_SBC3530
-CONFIG_MACH_SBC6000X
-CONFIG_MACH_SBCA11
-CONFIG_MACH_SC575IPC
-CONFIG_MACH_SC575PLC
-CONFIG_MACH_SCB9328
-CONFIG_MACH_SCIPHONE_G2
-CONFIG_MACH_SDI_ESS_9263
-CONFIG_MACH_SDVR
-CONFIG_MACH_SEABOARD
-CONFIG_MACH_SERRANO
-CONFIG_MACH_SFFSDR
-CONFIG_MACH_SGH_I740
-CONFIG_MACH_SHARESPACE
CONFIG_MACH_SHEEVAPLUG
-CONFIG_MACH_SHENZHOU
-CONFIG_MACH_SHEPHERD
-CONFIG_MACH_SHOOTER
-CONFIG_MACH_SHOOTER_CT
-CONFIG_MACH_SHOOTER_U
-CONFIG_MACH_SHORTLOIN
-CONFIG_MACH_SIEMENS_L0
-CONFIG_MACH_SIMPLENET
-CONFIG_MACH_SIMTEC_KIRKMOD
-CONFIG_MACH_SIM_ONE
-CONFIG_MACH_SKY25
-CONFIG_MACH_SKY6410
-CONFIG_MACH_SM1K
-CONFIG_MACH_SMARTQ5
-CONFIG_MACH_SMARTQ7
-CONFIG_MACH_SMARTQV3
-CONFIG_MACH_SMARTQV5
-CONFIG_MACH_SMARTQV7
-CONFIG_MACH_SMDK2412
-CONFIG_MACH_SMDK2413
-CONFIG_MACH_SMDK2416
-CONFIG_MACH_SMDK2443
-CONFIG_MACH_SMDK6410
-CONFIG_MACH_SMDK6440
-CONFIG_MACH_SMDK6442
-CONFIG_MACH_SMDK6450
-CONFIG_MACH_SMDKC100
-CONFIG_MACH_SMDKC110
-CONFIG_MACH_SMDKC210
-CONFIG_MACH_SMDKV210
-CONFIG_MACH_SMDKV310
-CONFIG_MACH_SNAPPER_9260
-CONFIG_MACH_SNAPPER_CL15
-CONFIG_MACH_SOFTWINNER
-CONFIG_MACH_SOLI_01
-CONFIG_MACH_SPADE
-CONFIG_MACH_SPADE_LTE
-CONFIG_MACH_SPDM
-CONFIG_MACH_SPEAR1310
-CONFIG_MACH_SPEAR1340
-CONFIG_MACH_SPEAR300
-CONFIG_MACH_SPEAR310
-CONFIG_MACH_SPEAR320
-CONFIG_MACH_SPEAR600
-CONFIG_MACH_SPEAR900
CONFIG_MACH_SPECIFIC
-CONFIG_MACH_SPICA
-CONFIG_MACH_SPITZ
-CONFIG_MACH_SPLENDOR
-CONFIG_MACH_SPX_SAKURA
-CONFIG_MACH_SPYPLUG
-CONFIG_MACH_SSC
-CONFIG_MACH_STAMP9G20
-CONFIG_MACH_STAMP9G45
-CONFIG_MACH_STARGATE2
-CONFIG_MACH_STEELYARD
-CONFIG_MACH_STELLA
-CONFIG_MACH_STMP378X
-CONFIG_MACH_STMP37XX
-CONFIG_MACH_STRASBOURG
-CONFIG_MACH_STRASBOURG_A2
-CONFIG_MACH_STRETCHS7000
-CONFIG_MACH_SUNFIRE
-CONFIG_MACH_SUNFLOWER
-CONFIG_MACH_SVCID
-CONFIG_MACH_SVP5500
-CONFIG_MACH_SVP8500V1
-CONFIG_MACH_SVP8500V2
-CONFIG_MACH_SWARCOEXTMODEM
-CONFIG_MACH_SWEDA_TMS2
-CONFIG_MACH_SX1
-CONFIG_MACH_SYNERGY
-CONFIG_MACH_SYNOLOGY_6282
-CONFIG_MACH_T20
-CONFIG_MACH_T5325
-CONFIG_MACH_T5388P
-CONFIG_MACH_T55
-CONFIG_MACH_TAG
-CONFIG_MACH_TAGW
-CONFIG_MACH_TANNA
-CONFIG_MACH_TAVOREVB
-CONFIG_MACH_TAVOREVB3
-CONFIG_MACH_TCC8000_SDK
-CONFIG_MACH_TCT_HAMMER
-CONFIG_MACH_TD3_REV1
-CONFIG_MACH_TEENOTE
-CONFIG_MACH_TEGRA_DAYTONA
-CONFIG_MACH_TEGRA_E1165
-CONFIG_MACH_TEGRA_SWORDFISH
-CONFIG_MACH_TEGRA_VOGUE
-CONFIG_MACH_TEM3X30
-CONFIG_MACH_TENDERLOIN
-CONFIG_MACH_TERASTATION_PRO2
-CONFIG_MACH_TERASTATION_WXL
-CONFIG_MACH_TERA_PRO2_RACK
-CONFIG_MACH_TETON_BGA
-CONFIG_MACH_THALES_ADC
-CONFIG_MACH_THALES_CBC
-CONFIG_MACH_THEBE
-CONFIG_MACH_TI8148EVM
-CONFIG_MACH_TI8168EVM
-CONFIG_MACH_TIMU
-CONFIG_MACH_TIN307
-CONFIG_MACH_TIN510
-CONFIG_MACH_TINY_GURNARD
-CONFIG_MACH_TITAN
-CONFIG_MACH_TJINC1000
-CONFIG_MACH_TM_EFDC
-CONFIG_MACH_TN200
-CONFIG_MACH_TNETV107X
-CONFIG_MACH_TNY_T3530
-CONFIG_MACH_TONGA2_TFTTIMER
-CONFIG_MACH_TOP9000
-CONFIG_MACH_TOP9000_BSL
-CONFIG_MACH_TOP9000_EVAL
-CONFIG_MACH_TOP9000_SU
-CONFIG_MACH_TOP9000_TCU
-CONFIG_MACH_TORBRECK
-CONFIG_MACH_TORNADO3240
-CONFIG_MACH_TOSA
-CONFIG_MACH_TOUCHBOOK
-CONFIG_MACH_TPT_2_0
-CONFIG_MACH_TQ6410
-CONFIG_MACH_TQMA35
-CONFIG_MACH_TQMA9263
-CONFIG_MACH_TRANSCEDE
-CONFIG_MACH_TREO680
-CONFIG_MACH_TRICORDER
-CONFIG_MACH_TRIDENT
-CONFIG_MACH_TRIMSLICE
-CONFIG_MACH_TRIPEL
-CONFIG_MACH_TRITIP
-CONFIG_MACH_TRIZEPS4
-CONFIG_MACH_TRIZEPS4WL
-CONFIG_MACH_TROUT
-CONFIG_MACH_TS209
-CONFIG_MACH_TS219
-CONFIG_MACH_TS3
-CONFIG_MACH_TS409
-CONFIG_MACH_TS41X
-CONFIG_MACH_TS42XX
-CONFIG_MACH_TS47XX
-CONFIG_MACH_TS4800
-CONFIG_MACH_TS48XX
-CONFIG_MACH_TS72XX
-CONFIG_MACH_TS75XX
-CONFIG_MACH_TS78XX
-CONFIG_MACH_TSOPLOADER
-CONFIG_MACH_TSUNAGI
-CONFIG_MACH_TTC_DKB
-CONFIG_MACH_TUBE
-CONFIG_MACH_TULIP
-CONFIG_MACH_TUNA
-CONFIG_MACH_TUXRAIL
-CONFIG_MACH_TX28
-CONFIG_MACH_TX53
CONFIG_MACH_TYPE
CONFIG_MACH_TYPE_COMPAT_REV
-CONFIG_MACH_U300
-CONFIG_MACH_U5500
-CONFIG_MACH_UBISYS_P9D_EVP
-CONFIG_MACH_UEMD
-CONFIG_MACH_UNINO1
-CONFIG_MACH_UNISDEV
-CONFIG_MACH_UNISENSE_MMM
-CONFIG_MACH_UNIT2S
-CONFIG_MACH_UNIVERSAL_C210
-CONFIG_MACH_USB_A9260
-CONFIG_MACH_USB_A9263
-CONFIG_MACH_USDLOADER
-CONFIG_MACH_UTM300
-CONFIG_MACH_VALDEZ
-CONFIG_MACH_VANGOGH
-CONFIG_MACH_VC0718
-CONFIG_MACH_VENTANA
-CONFIG_MACH_VERDI
-CONFIG_MACH_VERDI_LTE
-CONFIG_MACH_VERIDIS_A300
-CONFIG_MACH_VERSATILE_AB
-CONFIG_MACH_VEXPRESS
-CONFIG_MACH_VIGOR
-CONFIG_MACH_VIPRINET
-CONFIG_MACH_VIT_IBOX
-CONFIG_MACH_VIVO
-CONFIG_MACH_VIVOW_CT
-CONFIG_MACH_VMX25
-CONFIG_MACH_VMX51
-CONFIG_MACH_VMX53
-CONFIG_MACH_VOICEBLUE
-CONFIG_MACH_VPAC270
-CONFIG_MACH_VPR200
-CONFIG_MACH_VR1000
-CONFIG_MACH_VSTMS
-CONFIG_MACH_VVBOX_SDLITE2
-CONFIG_MACH_VVBOX_SDORIG2
-CONFIG_MACH_VVBOX_SDPRO4
-CONFIG_MACH_W21
-CONFIG_MACH_W90N960EVB
-CONFIG_MACH_W90P910EVB
-CONFIG_MACH_W90P950EVB
-CONFIG_MACH_WARIO
-CONFIG_MACH_WASABI
-CONFIG_MACH_WATSON_EFM_PLUGIN
-CONFIG_MACH_WB40N
-CONFIG_MACH_WBD111
-CONFIG_MACH_WBD222
-CONFIG_MACH_WG302V2
-CONFIG_MACH_WHISTLER
-CONFIG_MACH_WLAN_COMPUTER
-CONFIG_MACH_WLF_CRAGG_6410
-CONFIG_MACH_WM8505_7IN_NETBOOK
-CONFIG_MACH_WM8650REFBOARD
-CONFIG_MACH_WN802T
-CONFIG_MACH_WNR854T
-CONFIG_MACH_WRT350N_V2
-CONFIG_MACH_WTPLUG
-CONFIG_MACH_XARINA
-CONFIG_MACH_XCEP
-CONFIG_MACH_XILINX
-CONFIG_MACH_XILINX_EP107
-CONFIG_MACH_XSBASE255
-CONFIG_MACH_YANOMAMI
-CONFIG_MACH_YL9200
-CONFIG_MACH_Z3_814X_MOD
-CONFIG_MACH_Z3_816X_MOD
-CONFIG_MACH_ZIPIT2
-CONFIG_MACH_ZMX25
-CONFIG_MACH_ZYLONITE
-CONFIG_MACH_ZYLONITE2
CONFIG_MACPWR
CONFIG_MACRESET_TIMEOUT
CONFIG_MAC_ADDR_IN_EEPROM
CONFIG_MASK_AER_AO
CONFIG_MAX_DSP_CPUS
CONFIG_MAX_FPGA_DEVICES
-CONFIG_MAX_I2C_NUM
CONFIG_MAX_MEM_MAPPED
CONFIG_MAX_PKT
CONFIG_MAX_RAM_BANK_SIZE
CONFIG_MMCROOT
CONFIG_MMC_DEFAULT_DEV
CONFIG_MMC_RPMB_TRACE
-CONFIG_MMC_SDHCI_IO_ACCESSORS
-CONFIG_MMC_SDMA
CONFIG_MMC_SPI
CONFIG_MMC_SPI_BUS
CONFIG_MMC_SPI_CRC_ON
CONFIG_MMC_SPI_CS
CONFIG_MMC_SPI_CS_EPGIO
CONFIG_MMC_SPI_MODE
-CONFIG_MMC_SPI_NPOWER_EGPIO
-CONFIG_MMC_SPI_POWER_EGPIO
CONFIG_MMC_SPI_SPEED
CONFIG_MMC_SUNXI
CONFIG_MMC_SUNXI_SLOT
CONFIG_MV_ETH_RXQ
CONFIG_MV_I2C_NUM
CONFIG_MV_I2C_REG
-CONFIG_MV_SDHCI
CONFIG_MX23
CONFIG_MX25
CONFIG_MX25_CLK32
CONFIG_MXC_NAND_IP_REGS_BASE
CONFIG_MXC_NAND_REGS_BASE
CONFIG_MXC_SPI
-CONFIG_MXC_UART
CONFIG_MXC_UART_BASE
CONFIG_MXC_USB_FLAGS
CONFIG_MXC_USB_PORT
CONFIG_NAND_MPC5121_NFC
CONFIG_NAND_MXC
CONFIG_NAND_MXC_V1_1
-CONFIG_NAND_MXS
CONFIG_NAND_NDFC
CONFIG_NAND_OMAP_ECCSCHEME
CONFIG_NAND_OMAP_ELM
CONFIG_NAND_OMAP_GPMC_PREFETCH
CONFIG_NAND_OMAP_GPMC_WSCFG
CONFIG_NAND_PLAT
-CONFIG_NAND_S3C2410
CONFIG_NAND_SECBOOT
CONFIG_NAND_SPL
CONFIG_NAND_U_BOOT
CONFIG_NS16550_MIN_FUNCTIONS
CONFIG_NS8382X
CONFIG_NS87308
-CONFIG_NUM_DDR_CONTROLLERS
CONFIG_NUM_DSP_CPUS
CONFIG_NUM_PAMU
CONFIG_OCLK_DIV
CONFIG_OFF_PADCONF
CONFIG_OF_
CONFIG_OF_IDE_FIXUP
-CONFIG_OF_PLATDATA
CONFIG_OF_SPI
CONFIG_OF_SPI_FLASH
CONFIG_OF_STDOUT_PATH
CONFIG_OMAP3_ZOOM1
CONFIG_OMAP4430
CONFIG_OMAP54X
-CONFIG_OMAP_COMMON
CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
CONFIG_PCI_NOSCAN
CONFIG_PCI_OHCI
CONFIG_PCI_OHCI_DEVNO
-CONFIG_PCI_PNP
CONFIG_PCI_PREF_BUS
CONFIG_PCI_PREF_PHYS
CONFIG_PCI_PREF_SIZE
CONFIG_POST_UART
CONFIG_POST_WATCHDOG
CONFIG_POWER
-CONFIG_POWER_BATTERY
-CONFIG_POWER_BATTERY_TRATS
-CONFIG_POWER_BATTERY_TRATS2
-CONFIG_POWER_FG
-CONFIG_POWER_FG_MAX17042
-CONFIG_POWER_FG_MAX77693
CONFIG_POWER_FSL
CONFIG_POWER_FSL_MC13892
CONFIG_POWER_FSL_MC34704
CONFIG_POWER_I2C
CONFIG_POWER_LTC3676
CONFIG_POWER_LTC3676_I2C_ADDR
-CONFIG_POWER_MAX77686
CONFIG_POWER_MAX77696
CONFIG_POWER_MAX77696_I2C_ADDR
-CONFIG_POWER_MAX8997
-CONFIG_POWER_MAX8998
-CONFIG_POWER_MUIC
-CONFIG_POWER_MUIC_MAX77693
-CONFIG_POWER_MUIC_MAX8997
CONFIG_POWER_PFUZE100
CONFIG_POWER_PFUZE100_I2C_ADDR
CONFIG_POWER_PFUZE3000
CONFIG_POWER_PFUZE3000_I2C_ADDR
-CONFIG_POWER_PMIC_MAX77693
CONFIG_POWER_SPI
CONFIG_POWER_TPS62362
CONFIG_POWER_TPS65090_EC
CONFIG_RTC_RTC4543
CONFIG_RTC_RV3029
CONFIG_RTC_RX8025
-CONFIG_RTC_S3C24X0
CONFIG_RTC_X1205
CONFIG_RUN_FROM_DDR0
CONFIG_RUN_FROM_DDR1
CONFIG_S3C2410_NAND_HWECC
CONFIG_S3C2440
CONFIG_S3C24X0
-CONFIG_S3C24XX_CUSTOM_NAND_TIMING
CONFIG_S3C24XX_TACLS
CONFIG_S3C24XX_TWRPH0
CONFIG_S3C24XX_TWRPH1
CONFIG_S5PC100
CONFIG_S5PC110
CONFIG_S5P_PA_SYSRAM
-CONFIG_S5P_SDHCI
CONFIG_S6E63D6
CONFIG_S6E8AX0
-CONFIG_SA1100_ADSBITSY
-CONFIG_SA1100_ASSABET
-CONFIG_SA1100_BADGE4
-CONFIG_SA1100_BRUTUS
-CONFIG_SA1100_CERF
-CONFIG_SA1100_COLLIE
-CONFIG_SA1100_CONSUS
-CONFIG_SA1100_FLEXANET
-CONFIG_SA1100_GRAPHICSCLIENT
-CONFIG_SA1100_GRAPHICSMASTER
-CONFIG_SA1100_H3100
-CONFIG_SA1100_H3600
-CONFIG_SA1100_HACKKIT
-CONFIG_SA1100_JORNADA720
-CONFIG_SA1100_LART
-CONFIG_SA1100_NANOENGINE
-CONFIG_SA1100_PFS168
-CONFIG_SA1100_PLEB
-CONFIG_SA1100_PT_SYSTEM3
-CONFIG_SA1100_SHANNON
-CONFIG_SA1100_SIMPAD
-CONFIG_SA1100_XP860
CONFIG_SABRELITE
CONFIG_SAMA5D2
CONFIG_SAMA5D3
CONFIG_SATA1
CONFIG_SATA2
CONFIG_SATAPWR
-CONFIG_SATA_CEVA
CONFIG_SATA_DWC
CONFIG_SATA_MV
CONFIG_SATA_SIL
CONFIG_SCSI_SYM53C8XX
CONFIG_SC_TIMER_CLK
CONFIG_SDCARD
-CONFIG_SDHCI
CONFIG_SDRAM_BANK0
CONFIG_SDRAM_BANK1
CONFIG_SDRAM_ECC
CONFIG_SD_BOOT_QSPI
CONFIG_SECBOOT
CONFIG_SECURE_BL1_ONLY
-CONFIG_SECURE_BOOT
CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
CONFIG_SECURITY
CONFIG_SEC_DEQ_TIMEOUT
CONFIG_SPL_CMT_DEBUG
CONFIG_SPL_COMMON_INIT_DDR
CONFIG_SPL_CONSOLE
-CONFIG_SPL_DISPLAY_PRINT
CONFIG_SPL_ETH_DEVICE
CONFIG_SPL_FLUSH_IMAGE
CONFIG_SPL_FRAMEWORK
CONFIG_SPL_NAND_WORKSPACE
CONFIG_SPL_NO_CPU_SUPPORT_CODE
CONFIG_SPL_OMAP3_ID_NAND
-CONFIG_SPL_OS_BOOT
CONFIG_SPL_PAD_TO
CONFIG_SPL_PANIC_ON_RAW_IMAGE
CONFIG_SPL_PBL_PAD
CONFIG_STM32_HSE_HZ
CONFIG_STM32_HZ
CONFIG_STM32_SERIAL
-CONFIG_STORAGE_EMMC
CONFIG_STRESS
CONFIG_STRIDER
CONFIG_STRIDER_CON
CONFIG_SYS_DDR_ZQ_CNTL
CONFIG_SYS_DDR_ZQ_CONTROL
CONFIG_SYS_DEBUG
-CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE
CONFIG_SYS_DEBUG_SERVER_FW_ADDR
CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-CONFIG_SYS_DEBUG_SERVER_TIMEOUT
CONFIG_SYS_DECREMENT_PATTERNS
CONFIG_SYS_DEFAULT_IMMR
CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
CONFIG_SYS_FPGA_WAIT_CONFIG
CONFIG_SYS_FPGA_WAIT_INIT
CONFIG_SYS_FPGA_xxx
-CONFIG_SYS_FSL_A004447_SVR_REV
CONFIG_SYS_FSL_AIOP1_BASE
CONFIG_SYS_FSL_AIOP1_SIZE
CONFIG_SYS_FSL_B4860QDS_XFI_ERR
CONFIG_SYS_FSL_DCSR_SIZE
CONFIG_SYS_FSL_DCU_BE
CONFIG_SYS_FSL_DCU_LE
-CONFIG_SYS_FSL_DDR
-CONFIG_SYS_FSL_DDR1
-CONFIG_SYS_FSL_DDR2
CONFIG_SYS_FSL_DDR2_ADDR
-CONFIG_SYS_FSL_DDR3
CONFIG_SYS_FSL_DDR3L
CONFIG_SYS_FSL_DDR3_ADDR
-CONFIG_SYS_FSL_DDR4
-CONFIG_SYS_FSL_DDRC_ARM_GEN3
-CONFIG_SYS_FSL_DDRC_GEN1
-CONFIG_SYS_FSL_DDRC_GEN2
-CONFIG_SYS_FSL_DDRC_GEN3
-CONFIG_SYS_FSL_DDRC_GEN4
-CONFIG_SYS_FSL_DDR_86XX
CONFIG_SYS_FSL_DDR_ADDR
-CONFIG_SYS_FSL_DDR_BE
CONFIG_SYS_FSL_DDR_EMU
CONFIG_SYS_FSL_DDR_INTLV_256B
-CONFIG_SYS_FSL_DDR_LE
CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
-CONFIG_SYS_FSL_DDR_VER
CONFIG_SYS_FSL_DRAM_BASE1
CONFIG_SYS_FSL_DRAM_BASE2
CONFIG_SYS_FSL_DRAM_BASE3
CONFIG_SYS_FSL_DSP_DDR_ADDR
CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
-CONFIG_SYS_FSL_ERRATUM_A004468
-CONFIG_SYS_FSL_ERRATUM_A004477
-CONFIG_SYS_FSL_ERRATUM_A004508
-CONFIG_SYS_FSL_ERRATUM_A004510
-CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
-CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
-CONFIG_SYS_FSL_ERRATUM_A004580
-CONFIG_SYS_FSL_ERRATUM_A004699
-CONFIG_SYS_FSL_ERRATUM_A004849
-CONFIG_SYS_FSL_ERRATUM_A005125
-CONFIG_SYS_FSL_ERRATUM_A005434
-CONFIG_SYS_FSL_ERRATUM_A005812
-CONFIG_SYS_FSL_ERRATUM_A005871
-CONFIG_SYS_FSL_ERRATUM_A006261
-CONFIG_SYS_FSL_ERRATUM_A006379
-CONFIG_SYS_FSL_ERRATUM_A006384
-CONFIG_SYS_FSL_ERRATUM_A006475
-CONFIG_SYS_FSL_ERRATUM_A006593
-CONFIG_SYS_FSL_ERRATUM_A007075
-CONFIG_SYS_FSL_ERRATUM_A007186
-CONFIG_SYS_FSL_ERRATUM_A007212
-CONFIG_SYS_FSL_ERRATUM_A007798
-CONFIG_SYS_FSL_ERRATUM_A008044
-CONFIG_SYS_FSL_ERRATUM_A008336
-CONFIG_SYS_FSL_ERRATUM_A008378
-CONFIG_SYS_FSL_ERRATUM_A008407
-CONFIG_SYS_FSL_ERRATUM_A008511
-CONFIG_SYS_FSL_ERRATUM_A008514
-CONFIG_SYS_FSL_ERRATUM_A008585
CONFIG_SYS_FSL_ERRATUM_A008751
-CONFIG_SYS_FSL_ERRATUM_A008850
-CONFIG_SYS_FSL_ERRATUM_A009635
-CONFIG_SYS_FSL_ERRATUM_A009660
-CONFIG_SYS_FSL_ERRATUM_A009663
-CONFIG_SYS_FSL_ERRATUM_A009801
-CONFIG_SYS_FSL_ERRATUM_A009803
-CONFIG_SYS_FSL_ERRATUM_A009929
-CONFIG_SYS_FSL_ERRATUM_A009942
-CONFIG_SYS_FSL_ERRATUM_A010165
CONFIG_SYS_FSL_ERRATUM_A_004934
-CONFIG_SYS_FSL_ERRATUM_CPC_A002
-CONFIG_SYS_FSL_ERRATUM_CPC_A003
-CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
-CONFIG_SYS_FSL_ERRATUM_DDR_115
-CONFIG_SYS_FSL_ERRATUM_DDR_A003
-CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-CONFIG_SYS_FSL_ERRATUM_ESDHC111
-CONFIG_SYS_FSL_ERRATUM_ESDHC13
-CONFIG_SYS_FSL_ERRATUM_ESDHC135
-CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
-CONFIG_SYS_FSL_ERRATUM_I2C_A004447
-CONFIG_SYS_FSL_ERRATUM_IFC_A002769
-CONFIG_SYS_FSL_ERRATUM_IFC_A003399
-CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
-CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
-CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
-CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
-CONFIG_SYS_FSL_ERRATUM_P1010_A003549
-CONFIG_SYS_FSL_ERRATUM_SEC_A003571
-CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
-CONFIG_SYS_FSL_ERRATUM_USB14
CONFIG_SYS_FSL_ESDHC_ADDR
CONFIG_SYS_FSL_ESDHC_BE
CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET
CONFIG_SYS_FSL_FMAN_ADDR
CONFIG_SYS_FSL_GUTS_ADDR
-CONFIG_SYS_FSL_HAS_DP_DDR
CONFIG_SYS_FSL_I2C
CONFIG_SYS_FSL_I2C2_OFFSET
CONFIG_SYS_FSL_I2C2_SLAVE
CONFIG_SYS_FSL_I2C_OFFSET
CONFIG_SYS_FSL_I2C_SLAVE
CONFIG_SYS_FSL_I2C_SPEED
-CONFIG_SYS_FSL_IFC_BANK_COUNT
CONFIG_SYS_FSL_IFC_BASE
CONFIG_SYS_FSL_IFC_BASE1
CONFIG_SYS_FSL_IFC_BASE2
CONFIG_SYS_FSL_QMAN_ADDR
CONFIG_SYS_FSL_QMAN_OFFSET
CONFIG_SYS_FSL_QMAN_V3
-CONFIG_SYS_FSL_QORIQ_CHASSIS1
-CONFIG_SYS_FSL_QORIQ_CHASSIS2
CONFIG_SYS_FSL_QSPI_AHB
CONFIG_SYS_FSL_QSPI_BASE
CONFIG_SYS_FSL_QSPI_BASE1
CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET
CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR
CONFIG_SYS_FSL_SEC_ADDR
-CONFIG_SYS_FSL_SEC_BE
-CONFIG_SYS_FSL_SEC_COMPAT
CONFIG_SYS_FSL_SEC_IDX_OFFSET
-CONFIG_SYS_FSL_SEC_LE
CONFIG_SYS_FSL_SEC_MON_BE
CONFIG_SYS_FSL_SEC_MON_LE
CONFIG_SYS_FSL_SEC_OFFSET
CONFIG_SYS_FSL_SFP_VER_3_4
CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
CONFIG_SYS_FSL_SNVS_LE
-CONFIG_SYS_FSL_SP_ADDR
-CONFIG_SYS_FSL_SP_LOOPBACK_DUART
-CONFIG_SYS_FSL_SP_VSG_GIC_ADDR
-CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1
-CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2
-CONFIG_SYS_FSL_SRDS_1
-CONFIG_SYS_FSL_SRDS_2
CONFIG_SYS_FSL_SRDS_3
CONFIG_SYS_FSL_SRDS_4
CONFIG_SYS_FSL_SRDS_NUM_PLLS
CONFIG_SYS_FSL_SRIO_OFFSET
CONFIG_SYS_FSL_SRK_LE
CONFIG_SYS_FSL_TBCLK_DIV
-CONFIG_SYS_FSL_THREADS_PER_CORE
CONFIG_SYS_FSL_TIMER_ADDR
CONFIG_SYS_FSL_USB1_ADDR
CONFIG_SYS_FSL_USB1_PHY_ENABLE
CONFIG_SYS_GRLIB_SINGLE_BUS
CONFIG_SYS_HALT_BEFOR_RAM_JUMP
CONFIG_SYS_HAS_NO_CACHE
-CONFIG_SYS_HAS_SERDES
CONFIG_SYS_HELP_CMD_WIDTH
CONFIG_SYS_HID0_FINAL
CONFIG_SYS_HID0_INIT
CONFIG_SYS_I2C_MAX1237_ADDR
CONFIG_SYS_I2C_MAX_HOPS
CONFIG_SYS_I2C_MODULE
-CONFIG_SYS_I2C_MXC
CONFIG_SYS_I2C_MXC_I2C1
CONFIG_SYS_I2C_MXC_I2C2
CONFIG_SYS_I2C_MXC_I2C3
CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
-CONFIG_SYS_LS_MC_FW_ADDR
CONFIG_SYS_LS_MC_FW_IN_DDR
-CONFIG_SYS_LS_MC_FW_IN_NOR
CONFIG_SYS_LS_PPA_FW_ADDR
CONFIG_SYS_LS_PPA_FW_IN_XIP
CONFIG_SYS_LS_PPA_FW_IN_xxx
CONFIG_SYS_MMC_U_BOOT_OFFS
CONFIG_SYS_MMC_U_BOOT_SIZE
CONFIG_SYS_MMC_U_BOOT_START
-CONFIG_SYS_MMDC_CORE_ADDR_PARTITION
-CONFIG_SYS_MMDC_CORE_CONTROL_1
-CONFIG_SYS_MMDC_CORE_CONTROL_2
-CONFIG_SYS_MMDC_CORE_MISC
-CONFIG_SYS_MMDC_CORE_ODT_TIMING
-CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY
-CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL
-CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT
-CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY
-CONFIG_SYS_MMDC_CORE_REFRESH_CTL
-CONFIG_SYS_MMDC_CORE_TIMING_CFG_0
-CONFIG_SYS_MMDC_CORE_TIMING_CFG_1
-CONFIG_SYS_MMDC_CORE_TIMING_CFG_2
-CONFIG_SYS_MMDC_PHY_MEASURE_UNIT
-CONFIG_SYS_MMDC_PHY_ODT_CTRL
-CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG
-CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL
CONFIG_SYS_MM_TOP_HIDE
CONFIG_SYS_MONITOR_
CONFIG_SYS_MONITOR_BASE
CONFIG_SYS_MSC1_VAL
CONFIG_SYS_MSC2_VAL
CONFIG_SYS_MTDPARTS_RUNTIME
-CONFIG_SYS_MVEBU_PLL_CLOCK
CONFIG_SYS_MVFS
CONFIG_SYS_MX5_CLK32
CONFIG_SYS_MX5_HCLK
CONFIG_SYS_NS87308_UART2_BASE
CONFIG_SYS_NUM_ADDR_MAP
CONFIG_SYS_NUM_CPC
-CONFIG_SYS_NUM_DDR_CTLRS
CONFIG_SYS_NUM_FM1_10GEC
CONFIG_SYS_NUM_FM1_DTSEC
CONFIG_SYS_NUM_FM2_10GEC
CONFIG_SYS_NUM_FMAN
CONFIG_SYS_NUM_I2C_BUSES
CONFIG_SYS_NUM_IRQS
-CONFIG_SYS_NUM_TLBCAMS
CONFIG_SYS_NVRAM_ACCESS_ROUTINE
CONFIG_SYS_NVRAM_BASE
CONFIG_SYS_NVRAM_BASE_ADDR
CONFIG_SYS_OSD_DH
CONFIG_SYS_OSD_SCREENS
CONFIG_SYS_OSPR_OFFSET
-CONFIG_SYS_OS_BASE
-CONFIG_SYS_P4080_ERRATUM_CPU22
-CONFIG_SYS_P4080_ERRATUM_PCIE_A003
-CONFIG_SYS_P4080_ERRATUM_SERDES8
-CONFIG_SYS_P4080_ERRATUM_SERDES9
-CONFIG_SYS_P4080_ERRATUM_SERDES_A001
-CONFIG_SYS_P4080_ERRATUM_SERDES_A005
CONFIG_SYS_PACNT
CONFIG_SYS_PADAT
CONFIG_SYS_PADDR
CONFIG_SYS_POST_WORD_ADDR
CONFIG_SYS_POWER_MANAGER
CONFIG_SYS_PPC4XX_USB_ADDR
-CONFIG_SYS_PPC64
CONFIG_SYS_PPC_DDR_WIMGE
-CONFIG_SYS_PPC_E500_DEBUG_TLB
CONFIG_SYS_PQSPAR
CONFIG_SYS_PRELIM_OR_AM
CONFIG_SYS_PROMPT_HUSH_PS2
CONFIG_SYS_RTC_SETUP
CONFIG_SYS_RV3029_TCR
CONFIG_SYS_RX_ETH_BUFFER
-CONFIG_SYS_S3C2410_NAND_HWECC
CONFIG_SYS_SATA
CONFIG_SYS_SATA1
CONFIG_SYS_SATA1_FLAGS
CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS
CONFIG_SYS_SSD_BASE
CONFIG_SYS_SSD_BASE_PHYS
-CONFIG_SYS_SSP_PORT
CONFIG_SYS_SST_SECT
CONFIG_SYS_SST_SECTSZ
CONFIG_SYS_STACKSIZE
CONFIG_SYS_VSC7385_BR_PRELIM
CONFIG_SYS_VSC7385_OR_PRELIM
CONFIG_SYS_VSC7385_SIZE
-CONFIG_SYS_VSC8601_SKEWFIX
CONFIG_SYS_VXWORKS_MAC_PTR
CONFIG_SYS_WATCHDOG_FLAGS_ADDR
CONFIG_SYS_WATCHDOG_FREQ
CONFIG_SYS_ZYNQ_QSPI_WAIT
CONFIG_SYS_ZYNQ_SPI_WAIT
CONFIG_SYS_i2C_FSL
-CONFIG_T1023RDB
-CONFIG_T1024RDB
-CONFIG_T1040QDS
-CONFIG_T2080QDS
-CONFIG_T2080RDB
-CONFIG_T2081QDS
CONFIG_TAM3517_SETTINGS
CONFIG_TAM3517_SW3_SETTINGS
CONFIG_TCA642X
CONFIG_USB_EXT2_BOOT
CONFIG_USB_FAT_BOOT
CONFIG_USB_FREQ
-CONFIG_USB_FUNCTION_DFU
CONFIG_USB_FUNCTION_MASS_STORAGE
CONFIG_USB_FUNCTION_THOR
CONFIG_USB_GADGET_AMD5536UDC
CONFIG_USB_OHCI_EP93XX
CONFIG_USB_OHCI_LPC32XX
CONFIG_USB_OHCI_NEW
-CONFIG_USB_OHCI_S3C24XX
CONFIG_USB_OHCI_SUNXI
CONFIG_USB_OMAP3
CONFIG_USB_OTG
CONFIG_USB_XHCI_KEYSTONE
CONFIG_USB_XHCI_OMAP
CONFIG_USB_XHCI_PCI
-CONFIG_USB_XHCI_ZYNQMP
CONFIG_USER_LOWLEVEL_INIT
-CONFIG_USE_ARCH_MEMCPY
-CONFIG_USE_ARCH_MEMSET
CONFIG_USE_FDT
CONFIG_USE_INTERRUPT
CONFIG_USE_IRQ
CONFIG_VIDEO_DA8XX
CONFIG_VIDEO_DT_SIMPLEFB
CONFIG_VIDEO_FONT_4X6
-CONFIG_VIDEO_IPUV3
CONFIG_VIDEO_LCD_I2C_BUS
CONFIG_VIDEO_LOGO
CONFIG_VIDEO_MB862xx
CONFIG_XR16L2751
CONFIG_XSENGINE
CONFIG_XTFPGA
-CONFIG_YAFFS2
CONFIG_YAFFSFS_PROVIDE_VALUES
CONFIG_YAFFS_AUTO_UNICODE
CONFIG_YAFFS_CASE_INSENSITIVE
if (!ret) {
ret = fit_add_verification_data(params->keydir, dest_blob, ptr,
params->comment,
- params->require_keys);
+ params->require_keys,
+ params->engine_id);
}
if (dest_blob) {
static int fit_image_setup_sig(struct image_sign_info *info,
const char *keydir, void *fit, const char *image_name,
- int noffset, const char *require_keys)
+ int noffset, const char *require_keys, const char *engine_id)
{
const char *node_name;
char *algo_name;
info->checksum = image_get_checksum_algo(algo_name);
info->crypto = image_get_crypto_algo(algo_name);
info->require_keys = require_keys;
+ info->engine_id = engine_id;
if (!info->checksum || !info->crypto) {
printf("Unsupported signature algorithm (%s) for '%s' signature node in '%s' image node\n",
algo_name, node_name, image_name);
* @size: size of data in bytes
* @comment: Comment to add to signature nodes
* @require_keys: Mark all keys as 'required'
+ * @engine_id: Engine to use for signing
* @return 0 if ok, -1 on error
*/
static int fit_image_process_sig(const char *keydir, void *keydest,
void *fit, const char *image_name,
int noffset, const void *data, size_t size,
- const char *comment, int require_keys)
+ const char *comment, int require_keys, const char *engine_id)
{
struct image_sign_info info;
struct image_region region;
int ret;
if (fit_image_setup_sig(&info, keydir, fit, image_name, noffset,
- require_keys ? "image" : NULL))
+ require_keys ? "image" : NULL, engine_id))
return -1;
node_name = fit_get_name(fit, noffset, NULL);
* @image_noffset: Requested component image node
* @comment: Comment to add to signature nodes
* @require_keys: Mark all keys as 'required'
+ * @engine_id: Engine to use for signing
* @return: 0 on success, <0 on failure
*/
int fit_image_add_verification_data(const char *keydir, void *keydest,
void *fit, int image_noffset, const char *comment,
- int require_keys)
+ int require_keys, const char *engine_id)
{
const char *image_name;
const void *data;
strlen(FIT_SIG_NODENAME))) {
ret = fit_image_process_sig(keydir, keydest,
fit, image_name, noffset, data, size,
- comment, require_keys);
+ comment, require_keys, engine_id);
}
if (ret)
return ret;
static int fit_config_process_sig(const char *keydir, void *keydest,
void *fit, const char *conf_name, int conf_noffset,
- int noffset, const char *comment, int require_keys)
+ int noffset, const char *comment, int require_keys,
+ const char *engine_id)
{
struct image_sign_info info;
const char *node_name;
return -1;
if (fit_image_setup_sig(&info, keydir, fit, conf_name, noffset,
- require_keys ? "conf" : NULL))
+ require_keys ? "conf" : NULL, engine_id))
return -1;
ret = info.crypto->sign(&info, region, region_count, &value,
static int fit_config_add_verification_data(const char *keydir, void *keydest,
void *fit, int conf_noffset, const char *comment,
- int require_keys)
+ int require_keys, const char *engine_id)
{
const char *conf_name;
int noffset;
strlen(FIT_SIG_NODENAME))) {
ret = fit_config_process_sig(keydir, keydest,
fit, conf_name, conf_noffset, noffset, comment,
- require_keys);
+ require_keys, engine_id);
}
if (ret)
return ret;
}
int fit_add_verification_data(const char *keydir, void *keydest, void *fit,
- const char *comment, int require_keys)
+ const char *comment, int require_keys,
+ const char *engine_id)
{
int images_noffset, confs_noffset;
int noffset;
* i.e. component image node.
*/
ret = fit_image_add_verification_data(keydir, keydest,
- fit, noffset, comment, require_keys);
+ fit, noffset, comment, require_keys, engine_id);
if (ret)
return ret;
}
noffset = fdt_next_subnode(fit, noffset)) {
ret = fit_config_add_verification_data(keydir, keydest,
fit, noffset, comment,
- require_keys);
+ require_keys,
+ engine_id);
if (ret)
return ret;
}
bool external_data; /* Store data outside the FIT */
bool quiet; /* Don't output text in normal operation */
unsigned int external_offset; /* Add padding to external data */
+ const char *engine_id; /* Engine to use for signing */
};
/*
" -i => input filename for ramdisk file\n");
#ifdef CONFIG_FIT_SIGNATURE
fprintf(stderr,
- "Signing / verified boot options: [-E] [-k keydir] [-K dtb] [ -c <comment>] [-p addr] [-r]\n"
+ "Signing / verified boot options: [-E] [-k keydir] [-K dtb] [ -c <comment>] [-p addr] [-r] [-N engine]\n"
" -E => place data outside of the FIT structure\n"
" -k => set directory containing private keys\n"
" -K => write public keys to this .dtb file\n"
" -c => add comment in signature node\n"
" -F => re-sign existing FIT image\n"
" -p => place external data at a static position\n"
- " -r => mark keys used as 'required' in dtb\n");
+ " -r => mark keys used as 'required' in dtb\n"
+ " -N => engine to use for signing (pkcs11)\n");
#else
fprintf(stderr,
"Signing / verified boot not supported (CONFIG_FIT_SIGNATURE undefined)\n");
int opt;
while ((opt = getopt(argc, argv,
- "a:A:b:c:C:d:D:e:Ef:Fk:i:K:ln:p:O:rR:qsT:vVx")) != -1) {
+ "a:A:b:c:C:d:D:e:Ef:Fk:i:K:ln:N:p:O:rR:qsT:vVx")) != -1) {
switch (opt) {
case 'a':
params.addr = strtoull(optarg, &ptr, 16);
case 'n':
params.imagename = optarg;
break;
+ case 'N':
+ params.engine_id = optarg;
+ break;
case 'O':
params.os = genimg_get_os_id(optarg);
if (params.os < 0) {
projects / platform / kernel / u-boot.git / commitdiff