scsi: ufs: ufs-qcom: Add support for finding max gear on new platforms

Starting from Qcom UFS version 4.0, vendor specific REG_UFS_PARAM0 register
can be used to determine the maximum gear supported by the controller.

Suggested-by: Can Guo <quic_cang@quicinc.com>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 3370fa4..5e7ba3b 100644 (file)
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -282,6 +282,8 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
                 * Hence downgrade the maximum supported gear to HS-G2.
                 */
                return UFS_HS_G2;
+       } else if (host->hw_ver.major >= 0x4) {
+               return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0));
        }
 
        /* Default is HS-G3 */

diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 6cb9705..f744a9e 100644 (file)
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -94,6 +94,10 @@ enum {
 #define TMRLUT_HW_CGC_EN       BIT(6)
 #define OCSC_HW_CGC_EN         BIT(7)
 
+/* bit definitions for REG_UFS_PARAM0 */
+#define MAX_HS_GEAR_MASK       GENMASK(6, 4)
+#define UFS_QCOM_MAX_GEAR(x)   FIELD_GET(MAX_HS_GEAR_MASK, (x))
+
 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
 #define TEST_BUS_SUB_SEL_MASK  GENMASK(4, 0)  /* All XXX_SEL fields are 5 bits wide */