clk: imx: imx8mq: correct error handling path
authorPeng Fan <peng.fan@nxp.com>
Sun, 1 Oct 2023 12:26:18 +0000 (20:26 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Mon, 20 Nov 2023 10:51:56 +0000 (11:51 +0100)
[ Upstream commit 577ad169966e6e75b10e004389a3f79813e84b5d ]

Avoid memory leak in error handling path. It does not make
much sense for the SoC without clk driver, to make program behavior
correct, let's fix it.

Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <error27@gmail.com>
Closes: https://lore.kernel.org/r/202309240551.e46NllPa-lkp@intel.com/
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20231001122618.194498-1-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/clk/imx/clk-imx8mq.c

index 882dcad..0a75814 100644 (file)
@@ -288,8 +288,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
        void __iomem *base;
        int err;
 
-       clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
-                                         IMX8MQ_CLK_END), GFP_KERNEL);
+       clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MQ_CLK_END), GFP_KERNEL);
        if (WARN_ON(!clk_hw_data))
                return -ENOMEM;
 
@@ -306,10 +305,12 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
        hws[IMX8MQ_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4");
 
        np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
-       base = of_iomap(np, 0);
+       base = devm_of_iomap(dev, np, 0, NULL);
        of_node_put(np);
-       if (WARN_ON(!base))
-               return -ENOMEM;
+       if (WARN_ON(IS_ERR(base))) {
+               err = PTR_ERR(base);
+               goto unregister_hws;
+       }
 
        hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
        hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
@@ -395,8 +396,10 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 
        np = dev->of_node;
        base = devm_platform_ioremap_resource(pdev, 0);
-       if (WARN_ON(IS_ERR(base)))
-               return PTR_ERR(base);
+       if (WARN_ON(IS_ERR(base))) {
+               err = PTR_ERR(base);
+               goto unregister_hws;
+       }
 
        /* CORE */
        hws[IMX8MQ_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mq_a53_sels, base + 0x8000);