dma_apbh: dma-controller@80004000 {
compatible = "fsl,imx23-dma-apbh";
reg = <0x80004000 0x2000>;
- interrupts = <0 14 20 0
- 13 13 13 13>;
+ interrupts = <0>, <14>, <20>, <0>,
+ <13>, <13>, <13>, <13>;
#dma-cells = <1>;
dma-channels = <8>;
clocks = <&clks 15>;
dma_apbx: dma-apbx@80024000 {
compatible = "fsl,imx23-dma-apbx";
reg = <0x80024000 0x2000>;
- interrupts = <7 5 9 26
- 19 0 25 23
- 60 58 9 0
- 0 0 0 0>;
+ interrupts = <7>, <5>, <9>, <26>,
+ <19>, <0>, <25>, <23>,
+ <60>, <58>, <9>, <0>,
+ <0>, <0>, <0>, <0>;
interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
"saif0", "empty", "auart0-rx", "auart0-tx",
"auart1-rx", "auart1-tx", "saif1", "empty",
dcp: crypto@80028000 {
compatible = "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
- interrupts = <53 54>;
+ interrupts = <53>, <54>;
status = "okay";
};
lcdif@80030000 {
compatible = "fsl,imx23-lcdif";
reg = <0x80030000 2000>;
- interrupts = <46 45>;
+ interrupts = <46>, <45>;
clocks = <&clks 38>;
status = "disabled";
};
lradc: lradc@80050000 {
compatible = "fsl,imx23-lradc";
reg = <0x80050000 0x2000>;
- interrupts = <36 37 38 39 40 41 42 43 44>;
+ interrupts = <36>, <37>, <38>, <39>, <40>,
+ <41>, <42>, <43>, <44>;
status = "disabled";
clocks = <&clks 26>;
#io-channel-cells = <1>;
timrot@80068000 {
compatible = "fsl,imx23-timrot", "fsl,timrot";
reg = <0x80068000 0x2000>;
- interrupts = <28 29 30 31>;
+ interrupts = <28>, <29>, <30>, <31>;
clocks = <&clks 28>;
};
dma_apbh: dma-controller@80004000 {
compatible = "fsl,imx28-dma-apbh";
reg = <0x80004000 0x2000>;
- interrupts = <82 83 84 85
- 88 88 88 88
- 88 88 88 88
- 87 86 0 0>;
+ interrupts = <82>, <83>, <84>, <85>,
+ <88>, <88>, <88>, <88>,
+ <88>, <88>, <88>, <88>,
+ <87>, <86>, <0>, <0>;
#dma-cells = <1>;
dma-channels = <16>;
clocks = <&clks 25>;
dma_apbx: dma-apbx@80024000 {
compatible = "fsl,imx28-dma-apbx";
reg = <0x80024000 0x2000>;
- interrupts = <78 79 66 0
- 80 81 68 69
- 70 71 72 73
- 74 75 76 77>;
+ interrupts = <78>, <79>, <66>, <0>,
+ <80>, <81>, <68>, <69>,
+ <70>, <71>, <72>, <73>,
+ <74>, <75>, <76>, <77>;
#dma-cells = <1>;
dma-channels = <16>;
clocks = <&clks 26>;
dcp: crypto@80028000 {
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
- interrupts = <52 53 54>;
+ interrupts = <52>, <53>, <54>;
status = "okay";
};
lradc: lradc@80050000 {
compatible = "fsl,imx28-lradc";
reg = <0x80050000 0x2000>;
- interrupts = <10 14 15 16 17 18 19
- 20 21 22 23 24 25>;
+ interrupts = <10>, <14>, <15>, <16>, <17>, <18>, <19>,
+ <20>, <21>, <22>, <23>, <24>, <25>;
status = "disabled";
clocks = <&clks 41>;
#io-channel-cells = <1>;
timer: timrot@80068000 {
compatible = "fsl,imx28-timrot", "fsl,timrot";
reg = <0x80068000 0x2000>;
- interrupts = <48 49 50 51>;
+ interrupts = <48>, <49>, <50>, <51>;
clocks = <&clks 26>;
};